coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 45d5ca7 ARM: Separate the early console (romstage) from the bootblock console.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3671 -gerrit commit 45d5ca75097d8d787700de3bbeabb343a4d7710a Author: Gabe Black <gabeblack(a)google.com> Date: Thu Jun 6 00:21:20 2013 -0700 ARM: Separate the early console (romstage) from the bootblock console. It might be that you want an early console in romstage before RAM is up, but you can't or don't want to support the console all the way back in the bootblock. By making the console in those two different environments configurable seperately that becomes possible. On the 5250 console output as early as the bootblock works, but on the 5420 it only starts working in the ROM stage after clocks have been initialized. Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- src/arch/armv7/bootblock_simple.c | 2 +- src/console/Kconfig | 10 ++++++++++ src/console/Makefile.inc | 2 +- src/console/console.c | 3 ++- src/cpu/samsung/Kconfig | 1 + src/cpu/samsung/exynos5250/Makefile.inc | 12 ++++++------ src/cpu/samsung/exynos5420/Makefile.inc | 12 ++++++------ src/include/console/console.h | 3 ++- src/mainboard/emulation/qemu-armv7/Makefile.inc | 2 +- 10 files changed, 31 insertions(+), 18 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index a48aa67..882d0f2 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -163,7 +163,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD ramstage-y += exception.c ramstage-y += exception_asm.S -bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c bootblock-y += cache.c romstage-y += cache.c diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 5d0fe7e..541175c 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -68,7 +68,7 @@ void main(void) bootblock_mainboard_init(); } -#ifdef CONFIG_EARLY_CONSOLE +#ifdef CONFIG_BOOTBLOCK_CONSOLE console_init(); #endif diff --git a/src/console/Kconfig b/src/console/Kconfig index dc41fd3..f62cfdd 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,5 +1,15 @@ menu "Console" +config DEFAULT_BOOTBLOCK_CONSOLE + bool + default n + +config BOOTBLOCK_CONSOLE + bool "Enable early (bootblock) console output." + default DEFAULT_BOOTBLOCK_CONSOLE + help + Use console during the bootblock if supported + config DEFAULT_EARLY_CONSOLE bool default n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index ed2287e..9edec3c 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -14,7 +14,7 @@ romstage-y += console.c romstage-y += post.c romstage-y += die.c -bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c bootblock-y += console.c bootblock-y += die.c diff --git a/src/console/console.c b/src/console/console.c index 2f7de02..c53adc6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -101,7 +101,8 @@ int console_tst_byte(void) void console_init(void) { -#if CONFIG_EARLY_CONSOLE +#if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ + !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 3b6df9e..54f4ed1 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -2,6 +2,7 @@ config CPU_SAMSUNG_EXYNOS5250 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL + select DEFAULT_BOOTBLOCK_CONSOLE select DEFAULT_EARLY_CONSOLE bool default n diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index dcc783d..663f532 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -6,14 +6,14 @@ INTERMEDIATE += exynos5250_add_bl1 bootblock-y += spi.c bootblock-y += pinmux.c mct.c power.c # Clock is required for UART -bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c -bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c -bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-y += wakeup.c bootblock-y += gpio.c -bootblock-$(CONFIG_EARLY_CONSOLE) += pwm.c -bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c romstage-y += clock.c diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index c3416c4..1dddd21 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -6,14 +6,14 @@ INTERMEDIATE += exynos5420_add_bl1 bootblock-y += spi.c bootblock-y += pinmux.c mct.c power.c # Clock is required for UART -bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c -bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c -bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-y += wakeup.c bootblock-y += gpio.c -bootblock-$(CONFIG_EARLY_CONSOLE) += pwm.c -bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c romstage-y += clock.c diff --git a/src/include/console/console.h b/src/include/console/console.h index 9112f35..2f5f18e 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -77,7 +77,8 @@ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE +#if defined(__BOOT_BLOCK__) && !CONFIG_BOOTBLOCK_CONSOLE || \ + (defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__)) && !CONFIG_EARLY_CONSOLE static inline void printk(int LEVEL, const char *fmt, ...); static inline void printk(int LEVEL, const char *fmt, ...) { diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index 46ecfed..431d9ab 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -22,6 +22,6 @@ bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c ramstage-y += uart.c

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New patch to review for coreboot: e00f621 google/pit: Don't spew output with GPIO config
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3670 -gerrit commit e00f6216e893753ee2bd42760784d69af8ee8093 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 12:51:02 2013 -0700 google/pit: Don't spew output with GPIO config There are hundreds of GPIOs on the Exynos5420. Don't always print all of them per default. Change-Id: I2152ab760e31a335dbcd9d6ad32cd1eaae4b89bc Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/mainboard.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 77d48f9..dccb095 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -201,6 +201,8 @@ static void mainboard_init(device_t dev) set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); + + // FIXME: should timeout do { udelay(50); } while (!exynos_dp_hotplug()); @@ -228,7 +230,8 @@ static void mainboard_init(device_t dev) if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); - gpio_info(); + // Uncomment to get excessive GPIO output: + // gpio_info(); } static void mainboard_enable(device_t dev)

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New patch to review for coreboot: 9312d8a arch: clean up Kconfig and Makefile
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3669 -gerrit commit 9312d8a902d47cb046a0b184478e67a0974e3b7e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 29 13:10:56 2013 -0700 arch: clean up Kconfig and Makefile remove some unused code Change-Id: I41602fb391c1910c588a4f9dcc7c2edefe8ab5bc Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Kconfig | 17 ----------------- src/arch/x86/Kconfig | 12 ------------ src/arch/x86/lib/Makefile.inc | 1 - 3 files changed, 30 deletions(-) diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 488ca97..7f4d75e 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -1,9 +1,5 @@ menu "Architecture (armv7)" -config EABI_COMPAT - bool "Toolchain is EABI compatible" - default n - # Maximum reboot count # TODO: Improve description. config MAX_REBOOT_CNT @@ -36,17 +32,4 @@ config UPDATE_IMAGE is a suitable file for further processing. The bootblock will not be modified. -config BOOTBLOCK_SOC_INIT - string - -# FIXME: Should cache policy be set on a per-CPU basis? -# FIXME(dhendrix): Stefan sayz to make a smart decision and not prompt the user. -config ARM_DCACHE_POLICY_WRITEBACK - bool - default y - -config ARM_DCACHE_POLICY_WRITETHROUGH - bool - default n - endmenu diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..95fc172 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -103,14 +103,6 @@ config HAVE_ARCH_MEMCPY bool default y -config BIG_ENDIAN - bool - default n - -config LITTLE_ENDIAN - bool - default !BIG_ENDIAN - config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS @@ -119,10 +111,6 @@ config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS bool default n -config PCI_CONF2 - bool - default n - config HPET_ADDRESS hex default 0xfed00000 if !HPET_ADDRESS_OVERRIDE diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 7cdd3c6..56e4171 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c

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New patch to review for coreboot: 56af8d5 exynos5420: Clear the framebuffer before making it uncacheable
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3668 -gerrit commit 56af8d54b45160b18daa2d03f63ed3f68aadfe63 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 15:24:13 2013 -0700 exynos5420: Clear the framebuffer before making it uncacheable If we clear the framebuffer and then flush it back to memory using cache operations, the writes are going to be full cachelines at a time. If we make it uncacheable first, the writes will be serialized writes of whatever sized chunks memset uses, probably 4 bytes or less. Change-Id: I960f87a370e97f9e91236ad796d931573bb3dbb8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 1d51174..6e360bf 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev) lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ + /* * We need to clean and invalidate the framebuffer region and disable * caching as well. We assume that our dcache <--> memory address @@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); - memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); }

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New patch to review for coreboot: dabab7f exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3667 -gerrit commit dabab7f79844df79c43adb108d50a367dd6cee53 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 15:21:48 2013 -0700 exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer At one time it seemed to be necessary to disable and then re-enable the MMU when setting the framebuffer to be uncache-able due to bugs in the MMU management code. Since those bugs have been fixed, this is no longer necessary. Change-Id: I7ce825cf5eaaa95119364d780cba0935752e4632 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index e83c16a..1d51174 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -105,15 +105,11 @@ static void exynos_displayport_init(device_t dev) * Note: We may want to do something clever to ensure the framebuffer * region is aligned such that we don't change dcache policy for other * stuff inadvertantly. - * - * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); dcache_clean_invalidate_by_mva(lower, upper - lower); - dcache_mmu_disable(); mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); - dcache_mmu_enable(); mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG,

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New patch to review for coreboot: 92a81b2 exynos5420: Simplify the graphics code by eliminating the unused color map
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3666 -gerrit commit 92a81b2fc88235862519e2b245a62881af56b390 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 15:17:44 2013 -0700 exynos5420: Simplify the graphics code by eliminating the unused color map The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: I29bc17488539dbe695908e47f0b80c07e102e17d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.c | 21 +++++---------------- src/cpu/samsung/exynos5420/dp-core.h | 16 ++++------------ src/cpu/samsung/exynos5420/fb.c | 29 ++++++++--------------------- src/mainboard/google/pit/mainboard.c | 2 +- 4 files changed, 18 insertions(+), 50 deletions(-) diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 0abc0a3..e83c16a 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -68,12 +68,10 @@ static void exynos_displayport_init(device_t dev) /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. */ - vidinfo_t vi; struct exynos5_fimd_panel panel; unsigned long int fb_size; u32 lcdbase; - memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); panel.is_dp = 1; /* Display I/F is eDP */ @@ -94,18 +92,10 @@ static void exynos_displayport_init(device_t dev) panel.xres = conf->xres; panel.yres = conf->yres; - vi.vl_col = conf->xres; - vi.vl_row = conf->yres; - vi.vl_bpix = conf->bpp; - /* - * The size is a magic number from hardware. Allocate enough for the - * frame buffer and color map. - */ + /* The size is a magic number from hardware. */ fb_size = conf->xres * conf->yres * (conf->bpp / 8); - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); - printk(BIOS_SPEW, "LCD colormap base is %p\n", (void *)(lcdbase)); - mmio_resource(dev, 0, lcdbase/KiB, 64); - vi.cmap = (void *)lcdbase; + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); + printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); /* * We need to clean and invalidate the framebuffer region and disable @@ -119,18 +109,17 @@ static void exynos_displayport_init(device_t dev) * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); - uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); + uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); dcache_clean_invalidate_by_mva(lower, upper - lower); dcache_mmu_disable(); mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); dcache_mmu_enable(); - lcdbase += 64*KiB; mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ - ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); + ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5420/dp-core.h b/src/cpu/samsung/exynos5420/dp-core.h index 7b81037..62144e3 100644 --- a/src/cpu/samsung/exynos5420/dp-core.h +++ b/src/cpu/samsung/exynos5420/dp-core.h @@ -117,14 +117,6 @@ struct s5p_dp_device { struct link_train link_train; }; -/* this struct is used by mainboards to pass mode info to the driver */ -typedef struct vidinfo { - u16 vl_col; - u16 vl_row; - u8 vl_bpix; - u16 *cmap; -} vidinfo_t; - /* s5p_dp_reg.c */ /* @@ -260,9 +252,9 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; -void fb_init(vidinfo_t *panel_info, void *lcdbase, - struct exynos5_fimd_panel *pd); +void fb_init(unsigned long int fb_size, void *lcdbase, + struct exynos5_fimd_panel *pd); int dp_controller_init(struct s5p_dp_device *dp_device); -int lcd_ctrl_init(vidinfo_t *panel_info, - struct exynos5_fimd_panel *panel_data, void *lcdbase); +int lcd_ctrl_init(unsigned long int fb_size, + struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* CPU_SAMSUNG_EXYNOS5420_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5420/fb.c b/src/cpu/samsung/exynos5420/fb.c index d4c3d44..760f5ee 100644 --- a/src/cpu/samsung/exynos5420/fb.c +++ b/src/cpu/samsung/exynos5420/fb.c @@ -116,32 +116,21 @@ static void fimd_bypass(void) sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } -/* Calculate the size of Framebuffer from the resolution */ -static u32 calc_fbsize(vidinfo_t *panel_info) -{ - /* They had PAGE_SIZE here instead of 4096. - * but that's a totally arbitrary number -- everything nowadays - * has lots of page sizes. - * So keep it obvious. - */ - return ALIGN((panel_info->vl_col * panel_info->vl_row * - ((1<<panel_info->vl_bpix) / 8)), 4096); -} - /* * Initialize display controller. * * @param lcdbase pointer to the base address of framebuffer. * @pd pointer to the main panel_data structure */ -void fb_init(vidinfo_t *panel_info, void *lcdbase, - struct exynos5_fimd_panel *pd) +void fb_init(unsigned long int fb_size, void *lcdbase, + struct exynos5_fimd_panel *pd) { unsigned int val; - u32 fbsize; struct exynos5_fimd *fimd = samsung_get_base_fimd(); struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl(); + fb_size = ALIGN(fb_size, 4096); + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); writel(val, &fimd->vidcon0); @@ -161,9 +150,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, writel(val, &disp_ctrl->vidtcon2); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); - - fbsize = calc_fbsize(panel_info); - writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + writel((unsigned int)lcdbase + fb_size, &fimd->vidw00add1b0); writel(pd->xres * 2, &fimd->vidw00add2); @@ -586,12 +573,12 @@ int dp_controller_init(struct s5p_dp_device *dp_device) * @param lcdbase Base address of LCD frame buffer * @return 0 if ok, -ve error code on error */ -int lcd_ctrl_init(vidinfo_t *panel_info, - struct exynos5_fimd_panel *panel_data, void *lcdbase) +int lcd_ctrl_init(unsigned long int fb_size, + struct exynos5_fimd_panel *panel_data, void *lcdbase) { int ret = 0; fimd_bypass(); - fb_init(panel_info, lcdbase, panel_data); + fb_init(fb_size, lcdbase, panel_data); return ret; } diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 11b72c5..77d48f9 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -198,7 +198,7 @@ static void mainboard_init(device_t dev) disable_usb30_pll(); fb_addr = cbmem_find(CBMEM_ID_CONSOLE); - set_vbe_mode_info_valid(&edid, (uintptr_t)(fb_addr) + 64*KiB); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); do {

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New patch to review for coreboot: 2832aa9 exynos5420: Fix some problems with the clock management code.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3665 -gerrit commit 2832aa97ffa733b183f44b0b9e77ee07f541e761 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Jun 6 00:14:08 2013 -0700 exynos5420: Fix some problems with the clock management code. The code which figured out the rate of the input clock to a peripheral was doing several things wrong. First, it was using the wrong values when determing what the source of a clock was set to. Second, it was using the wrong offset into that register to find the current source setting. This change fixes the constants which select a clock source which get some more things working, but doesn't attempt to fix the bit position table. Change-Id: Id7482ee1c78cec274353bae3ce2dccb84705c66a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 11 ++++--- src/cpu/samsung/exynos5420/clock.c | 65 +++++++++++++++++--------------------- 2 files changed, 36 insertions(+), 40 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index b98a673..3d60b28 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -35,9 +35,13 @@ enum periph_id; #define SPLL 7 enum pll_src_bit { - EXYNOS_SRC_MPLL = 6, - EXYNOS_SRC_EPLL, - EXYNOS_SRC_VPLL, + EXYNOS_SRC_CPLL = 1, + EXYNOS_SRC_DPLL = 2, + EXYNOS_SRC_MPLL = 3, + EXYNOS_SRC_SPLL = 4, + EXYNOS_SRC_IPLL = 5, + EXYNOS_SRC_EPLL = 6, + EXYNOS_SRC_RPLL = 7, }; /* * @@ -46,7 +50,6 @@ enum pll_src_bit { */ struct clk_bit_info { s8 src_bit; /* offset in register to clock source field */ - s8 n_src_bits; /* number of bits in 'src_bit' field */ s8 div_bit; s8 prediv_bit; }; diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index fd15486..6e4701a 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -30,39 +30,35 @@ /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { - {0, 4, 0, -1}, - {4, 4, 4, -1}, - {8, 4, 8, -1}, - {12, 4, 12, -1}, - {0, 4, 0, 8}, - {4, 4, 16, 24}, - {8, 4, 0, 8}, - {12, 4, 16, 24}, - {-1, -1, -1, -1}, - {16, 4, 0, 8}, /* PERIPH_ID_SROMC */ - {20, 4, 16, 24}, - {24, 4, 0, 8}, - {0, 4, 0, 4}, - {4, 4, 12, 16}, - {-1, 4, -1, -1}, - {-1, 4, -1, -1}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, /* PERIPH_ID_I2S1 */ - {24, 1, 20, -1}, /* PERIPH_ID_SATA */ + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, /* PERIPH_ID_SROMC */ + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, }; /* Epll Clock division values to achive different frequency output */ @@ -221,9 +217,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case EXYNOS_SRC_EPLL: sclk = get_pll_clk(EPLL); break; - case EXYNOS_SRC_VPLL: - sclk = get_pll_clk(VPLL); - break; default: return 0; }

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New patch to review for coreboot: 0608c26 armv7: Reserve space BL1 and checksum header by specifying bootblock offset.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3664 -gerrit commit 0608c2606d5c972ed311275cd9bd8b9528934f24 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jun 11 21:55:58 2013 -0700 armv7: Reserve space BL1 and checksum header by specifying bootblock offset. Not all ARM systems need "BL1", and the layout of BL* and bootblock may be different (ex, Exynos 5250 may use a new BL1 with variable length checksum header). To support that better, define the real base address (and ROM offset) of boot block, and then we can post-processing ROM image file by filling data / checksum and any other information. Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 3 ++- src/arch/armv7/bootblock.inc | 8 -------- src/arch/armv7/bootblock.lds | 3 +-- src/cpu/samsung/exynos5250/Kconfig | 34 +++++++++++++++++++------------- src/cpu/samsung/exynos5420/Kconfig | 40 +++++++++++++++++++++++--------------- 5 files changed, 47 insertions(+), 41 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 91d36e0..a48aa67 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -48,7 +48,8 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # TODO Change -b to Kconfig variable. $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \ + -B $(objcbfs)/bootblock.bin -a 64 \ + -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ -o $(CONFIG_CBFS_ROM_OFFSET) @printf " CBFS $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index bac32e2..b2c993a 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -29,14 +29,6 @@ * MA 02111-1307 USA */ -.section ".bl1", "a", %progbits -_bl1: - /* For now we have to live with a first stage boot loader - * on ARM, which is 8KB in size and it is prepended to the - * reset vector - */ - .skip (CONFIG_BL1_SIZE_KB * 1024) - .section ".start", "a", %progbits .globl _start _start: b reset diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds index 6f6040d..8370396 100644 --- a/src/arch/armv7/bootblock.lds +++ b/src/arch/armv7/bootblock.lds @@ -25,12 +25,11 @@ OUTPUT_ARCH(arm) TARGET(binary) SECTIONS { - ROMLOC = CONFIG_BOOTBLOCK_BASE - (CONFIG_BL1_SIZE_KB * 1024); + ROMLOC = CONFIG_BOOTBLOCK_BASE; /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; - *(.bl1); *(.start); *(.id); *(.text); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 5f5add4..75d1178 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -10,9 +10,26 @@ config EXYNOS_ACE_SHA bool default n -config BL1_SIZE_KB - int - default 8 +# ROM image layout. +# +# 0x0000: vendor-provided BL1 (8k). +# 0x2000: bootblock +# 0x2010-0x2090: reserved for CBFS master header. +# 0xA000: Free for CBFS data. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x2000 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x2010 + +config CBFS_ROM_OFFSET + # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0A000 + # Example SRAM/iRAM map for Exynos5250 platform: # @@ -50,17 +67,6 @@ config STACK_SIZE hex default 0x1000 -config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - hex "offset of CBFS data in ROM" - default 0x0A000 - -# TODO Change this to some better address not overlapping bootblock when -# cbfstool supports creating header in arbitrary location. -config CBFS_HEADER_ROM_OFFSET - hex "offset of master CBFS header in ROM" - default 0x2040 - # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 93ece2e..406ffd2 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -10,20 +10,39 @@ config EXYNOS_ACE_SHA bool default n -config BL1_SIZE_KB - int - default 8 +# ROM image layout. +# +# 0x0000: vendor-provided BL1 (8k). +# 0x2000: variable length bootblock checksum header +# 0x2010: bootblock +# 0x2020-0x20A0: reserved for CBFS master header. +# 0xA000: Free for CBFS data. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x2010 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x2020 + +config CBFS_ROM_OFFSET + # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0A000 + # Example SRAM/iRAM map for Exynos5420 platform: # # 0x0202_0000: vendor-provided BL1 -# 0x0202_4400: bootblock, assume up to 32KB in size +# 0x0202_4400: variable length bootblock checksum header. +# 0x0202_4410: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. # 0x0207_4000: stack pointer config BOOTBLOCK_BASE hex - default 0x02024400 + default 0x02024410 config ROMSTAGE_BASE hex @@ -50,17 +69,6 @@ config STACK_SIZE hex default 0x1000 -config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - hex "offset of CBFS data in ROM" - default 0x0A000 - -# TODO Change this to some better address not overlapping bootblock when -# cbfstool supports creating header in arbitrary location. -config CBFS_HEADER_ROM_OFFSET - hex "offset of master CBFS header in ROM" - default 0x2040 - # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS

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New patch to review for coreboot: c66c7ef cpu: Add CPU microcode file to cbfs with 16-byte alignment
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3663 -gerrit commit c66c7ef971c0ff3645147cda70d37c69015d91b8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 11 16:36:37 2013 -0500 cpu: Add CPU microcode file to cbfs with 16-byte alignment On x86 there is a 16-byte alignment requirement for the addresses containing the CPU microcode. The cbfs files containing the microcode are used in memory-mapped fashion when loading new mircocode. Therefore, the data payload's address/offset of a cbfs file in flash dictates the resulting alignment. Fix this by processing the CPU microcode cbfs file separately as it uses $(CBFSTOOL) to find the proper location within the provided rom image. Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 3 ++- src/arch/x86/Makefile.inc | 3 ++- src/cpu/Makefile.inc | 20 ++++++++++++++------ 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index a249655..91d36e0 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -46,7 +46,7 @@ prebuild-files = \ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # TODO Change -b to Kconfig variable. -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ @@ -56,6 +56,7 @@ $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuil -f $(objcbfs)/romstage.elf -b 0 \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7f1b7b2..0faf140 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -61,11 +61,12 @@ prebuild-files = \ $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m x86 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 \ -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 09d36ec..a860f67 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -15,17 +15,17 @@ subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 ## Rules for building the microcode blob in CBFS ################################################################################ +cpu_ucode_cbfs_name = cpu_microcode_blob.bin + # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) -cbfs-files-y += cpu_microcode_blob.bin -cpu_microcode_blob.bin-type = 0x53 -cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cbfs_include_ucode = y endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y) -cbfs-files-y += cpu_microcode_blob.bin -cpu_microcode_blob.bin-type = 0x53 -cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin +cbfs_include_ucode = y endif # In case we have more than one "source" (cough) files containing microcode, we @@ -42,3 +42,11 @@ $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -j .data -O binary $< $@ + +ifeq ($(cbfs_include_ucode),y) +# Add CPU microcode to specified rom image $(1) +add-cpu-microcode-to-cbfs = \ + $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 -b +else +add-cpu-microcode-to-cbfs = true +endif

1 0

New patch to review for coreboot: e7fb318 Exynos: Change BL1 (boot loader 1) file name.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3662 -gerrit commit e7fb318b0b273a3a0d4cbbdc0452f10d46ee1de2 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jun 10 14:45:39 2013 -0700 Exynos: Change BL1 (boot loader 1) file name. Change every "boot loader 1" to be same file name in different folders. Change-Id: I4c9f342bb7395feceaa981279c6a65b4d8386945 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/cpu/samsung/exynos5420/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e55b1a0..dcc783d 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -51,5 +51,5 @@ ramstage-y += fb.c exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" - dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \ + dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 4099b12..c3416c4 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -51,5 +51,5 @@ ramstage-y += fb.c exynos5420_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5420 BL1\n" - dd if=3rdparty/cpu/samsung/exynos5420/E5420.nbl1.bin \ + dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1

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coreboot-gerrit July 2013