coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 5e9d98a google/snow: Don't spew output with GPIO config
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3661 -gerrit commit 5e9d98a083904aee73448282b6e978ee23320caf Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 17 10:34:25 2013 -0700 google/snow: Don't spew output with GPIO config There are hundreds of GPIOs on the Exynos5250. Don't always print all of them per default. Change-Id: Ie349f2a4117883302b743027ed13cc9705b804f8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/mainboard.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 76605bb..a0d6a61 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -229,6 +229,8 @@ static void mainboard_init(device_t dev) set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); + + // FIXME: should timeout do { udelay(50); } while (!exynos_dp_hotplug()); @@ -256,7 +258,8 @@ static void mainboard_init(device_t dev) if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); - gpio_info(); + // Uncomment to get excessive GPIO output: + // gpio_info(); } static void mainboard_enable(device_t dev)

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New patch to review for coreboot: 7c1f9a9 Drop ELF remains from boot code
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3660 -gerrit commit 7c1f9a906ef62564eb348264f362cf6b07216f7d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 24 15:09:36 2013 -0700 Drop ELF remains from boot code This stuff is not used, so let's drop it. Change-Id: I671a5e87855b4c59622cafacdefe466ab3d70143 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/boot.c | 202 ++---------------- src/arch/armv7/include/arch/stages.h | 1 + src/arch/armv7/stages.c | 6 +- src/arch/x86/boot/boot.c | 84 +------- src/arch/x86/include/arch/stages.h | 1 + src/include/boot/elf.h | 403 ----------------------------------- src/include/boot/elf_boot.h | 89 -------- src/lib/hardwaremain.c | 1 - src/lib/selfboot.c | 3 +- 9 files changed, 29 insertions(+), 761 deletions(-) diff --git a/src/arch/armv7/boot.c b/src/arch/armv7/boot.c index ab531be..6774802 100644 --- a/src/arch/armv7/boot.c +++ b/src/arch/armv7/boot.c @@ -1,189 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console/console.h> -#include <ip_checksum.h> -#include <boot/elf.h> -#include <boot/elf_boot.h> -#include <string.h> -#include <cpu/x86/multiboot.h> #include <arch/stages.h> - -#ifndef CMD_LINE -#define CMD_LINE "" -#endif - - - -#define UPSZ(X) ((sizeof(X) + 3) &~3) - -static struct { - Elf_Bhdr hdr; - Elf_Nhdr ft_hdr; - unsigned char ft_desc[UPSZ(FIRMWARE_TYPE)]; - Elf_Nhdr bl_hdr; - unsigned char bl_desc[UPSZ(BOOTLOADER)]; - Elf_Nhdr blv_hdr; - unsigned char blv_desc[UPSZ(BOOTLOADER_VERSION)]; - Elf_Nhdr cmd_hdr; - unsigned char cmd_desc[UPSZ(CMD_LINE)]; -} elf_boot_notes = { - .hdr = { - .b_signature = 0x0E1FB007, - .b_size = sizeof(elf_boot_notes), - .b_checksum = 0, - .b_records = 4, - }, - .ft_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(FIRMWARE_TYPE), - .n_type = EBN_FIRMWARE_TYPE, - }, - .ft_desc = FIRMWARE_TYPE, - .bl_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(BOOTLOADER), - .n_type = EBN_BOOTLOADER_NAME, - }, - .bl_desc = BOOTLOADER, - .blv_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(BOOTLOADER_VERSION), - .n_type = EBN_BOOTLOADER_VERSION, - }, - .blv_desc = BOOTLOADER_VERSION, - .cmd_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(CMD_LINE), - .n_type = EBN_COMMAND_LINE, - }, - .cmd_desc = CMD_LINE, -}; - - -int elf_check_arch(Elf_ehdr *ehdr) -{ - return ( - ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && - (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && - (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) - ); - -} - void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) { - extern unsigned char _ram_seg, _eram_seg; - unsigned long lb_start, lb_size; - unsigned long adjust, adjusted_boot_notes; - - elf_boot_notes.hdr.b_checksum = - compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); - - lb_start = (unsigned long)&_ram_seg; - lb_size = (unsigned long)(&_eram_seg - &_ram_seg); - adjust = buffer + size - lb_start; - - adjusted_boot_notes = (unsigned long)&elf_boot_notes; - adjusted_boot_notes += adjust; - - printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); - printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); - printk(BIOS_SPEW, "lb_size = 0x%08lx\n", lb_size); - printk(BIOS_SPEW, "adjust = 0x%08lx\n", adjust); - printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); - printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); - printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); - + printk(BIOS_SPEW, "entry = %p\n", entry); stage_exit(entry); -#if 0 - /* FIXME: do we need any of this? */ - /* Jump to kernel */ - __asm__ __volatile__( - " cld \n\t" - /* Save the callee save registers... */ - " pushl %%esi\n\t" - " pushl %%edi\n\t" - " pushl %%ebx\n\t" - /* Save the parameters I was passed */ - " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ - " pushl %1\n\t" /* 12 buffer */ - " pushl %2\n\t" /* 8 lb_size */ - " pushl %3\n\t" /* 4 entry */ - " pushl %4\n\t" /* 0 elf_boot_notes */ - /* Compute the adjustment */ - " xorl %%eax, %%eax\n\t" - " subl 16(%%esp), %%eax\n\t" - " addl 12(%%esp), %%eax\n\t" - " addl 8(%%esp), %%eax\n\t" - " movl %%eax, 20(%%esp)\n\t" - /* Place a copy of coreboot in its new location */ - /* Move ``longs'' the coreboot size is 4 byte aligned */ - " movl 12(%%esp), %%edi\n\t" - " addl 8(%%esp), %%edi\n\t" - " movl 16(%%esp), %%esi\n\t" - " movl 8(%%esp), %%ecx\n\n" - " shrl $2, %%ecx\n\t" - " rep movsl\n\t" - - /* Adjust the stack pointer to point into the new coreboot image */ - " addl 20(%%esp), %%esp\n\t" - /* Adjust the instruction pointer to point into the new coreboot image */ - " movl $1f, %%eax\n\t" - " addl 20(%%esp), %%eax\n\t" - " jmp *%%eax\n\t" - "1: \n\t" - - /* Copy the coreboot bounce buffer over coreboot */ - /* Move ``longs'' the coreboot size is 4 byte aligned */ - " movl 16(%%esp), %%edi\n\t" - " movl 12(%%esp), %%esi\n\t" - " movl 8(%%esp), %%ecx\n\t" - " shrl $2, %%ecx\n\t" - " rep movsl\n\t" - - /* Now jump to the loaded image */ - " movl %5, %%eax\n\t" - " movl 0(%%esp), %%ebx\n\t" - " call *4(%%esp)\n\t" - - /* The loaded image returned? */ - " cli \n\t" - " cld \n\t" - - /* Copy the saved copy of coreboot where coreboot runs */ - /* Move ``longs'' the coreboot size is 4 byte aligned */ - " movl 16(%%esp), %%edi\n\t" - " movl 12(%%esp), %%esi\n\t" - " addl 8(%%esp), %%esi\n\t" - " movl 8(%%esp), %%ecx\n\t" - " shrl $2, %%ecx\n\t" - " rep movsl\n\t" - - /* Adjust the stack pointer to point into the old coreboot image */ - " subl 20(%%esp), %%esp\n\t" - - /* Adjust the instruction pointer to point into the old coreboot image */ - " movl $1f, %%eax\n\t" - " subl 20(%%esp), %%eax\n\t" - " jmp *%%eax\n\t" - "1: \n\t" - - /* Drop the parameters I was passed */ - " addl $24, %%esp\n\t" - - /* Restore the callee save registers */ - " popl %%ebx\n\t" - " popl %%edi\n\t" - " popl %%esi\n\t" - - :: - "ri" (lb_start), "ri" (buffer), "ri" (lb_size), - "ri" (entry), -#if CONFIG_MULTIBOOT - "ri"(mbi), "ri" (MB_MAGIC2) -#else - "ri"(adjusted_boot_notes), "ri" (0x0E1FB007) -#endif - ); -#endif } diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/armv7/include/arch/stages.h index 671c02b..3fd54b9 100644 --- a/src/arch/armv7/include/arch/stages.h +++ b/src/arch/armv7/include/arch/stages.h @@ -24,5 +24,6 @@ extern void main(void); void stage_entry(void) __attribute__((section(".text.stage_entry.armv7"))); void stage_exit(void *); +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); #endif diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index e26dbe5..0d2072d 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * Copyright 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * + */ + +/* * This file contains entry/exit functions for each stage during coreboot * execution (bootblock entry and ramstage exit will depend on external * loading. diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 4892c5e..7fc433d 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -1,81 +1,14 @@ #include <console/console.h> +#include <arch/stages.h> #include <ip_checksum.h> -#include <boot/elf.h> -#include <boot/elf_boot.h> #include <string.h> #include <cpu/x86/multiboot.h> - -#ifndef CMD_LINE -#define CMD_LINE "" -#endif - - - -#define UPSZ(X) ((sizeof(X) + 3) &~3) - -static struct { - Elf_Bhdr hdr; - Elf_Nhdr ft_hdr; - unsigned char ft_desc[UPSZ(FIRMWARE_TYPE)]; - Elf_Nhdr bl_hdr; - unsigned char bl_desc[UPSZ(BOOTLOADER)]; - Elf_Nhdr blv_hdr; - unsigned char blv_desc[UPSZ(BOOTLOADER_VERSION)]; - Elf_Nhdr cmd_hdr; - unsigned char cmd_desc[UPSZ(CMD_LINE)]; -} elf_boot_notes = { - .hdr = { - .b_signature = 0x0E1FB007, - .b_size = sizeof(elf_boot_notes), - .b_checksum = 0, - .b_records = 4, - }, - .ft_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(FIRMWARE_TYPE), - .n_type = EBN_FIRMWARE_TYPE, - }, - .ft_desc = FIRMWARE_TYPE, - .bl_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(BOOTLOADER), - .n_type = EBN_BOOTLOADER_NAME, - }, - .bl_desc = BOOTLOADER, - .blv_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(BOOTLOADER_VERSION), - .n_type = EBN_BOOTLOADER_VERSION, - }, - .blv_desc = BOOTLOADER_VERSION, - .cmd_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(CMD_LINE), - .n_type = EBN_COMMAND_LINE, - }, - .cmd_desc = CMD_LINE, -}; - - -int elf_check_arch(Elf_ehdr *ehdr) -{ - return ( - ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && - (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && - (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) - ); - -} - #if CONFIG_RELOCATABLE_RAMSTAGE /* When the ramstage is relocatable the elf loading ensures an elf image cannot * be loaded over the ramstage code. */ void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) { - elf_boot_notes.hdr.b_checksum = - compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); - /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" @@ -90,8 +23,6 @@ void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) "r" (entry), #if CONFIG_MULTIBOOT "b"(mbi), "a" (MB_MAGIC2) -#else - "b"(&elf_boot_notes), "a" (0x0E1FB007) #endif ); } @@ -100,25 +31,14 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) { extern unsigned char _ram_seg, _eram_seg; unsigned long lb_start, lb_size; - unsigned long adjust, adjusted_boot_notes; - - elf_boot_notes.hdr.b_checksum = - compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); lb_start = (unsigned long)&_ram_seg; lb_size = (unsigned long)(&_eram_seg - &_ram_seg); - adjust = buffer + size - lb_start; - - adjusted_boot_notes = (unsigned long)&elf_boot_notes; - adjusted_boot_notes += adjust; printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); printk(BIOS_SPEW, "lb_size = 0x%08lx\n", lb_size); - printk(BIOS_SPEW, "adjust = 0x%08lx\n", adjust); printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); - printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); - printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); /* Jump to kernel */ __asm__ __volatile__( @@ -206,7 +126,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) #if CONFIG_MULTIBOOT "ri"(mbi), "ri" (MB_MAGIC2) #else - "ri"(adjusted_boot_notes), "ri" (0x0E1FB007) + "ri"(0), "ri" (0) #endif ); } diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 3dea427..8cbf5da 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -23,4 +23,5 @@ #include <arch/cpu.h> void asmlinkage copy_and_run(void); +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); #endif diff --git a/src/include/boot/elf.h b/src/include/boot/elf.h deleted file mode 100644 index 5be96be..0000000 --- a/src/include/boot/elf.h +++ /dev/null @@ -1,403 +0,0 @@ -#ifndef ELF_H -#define ELF_H - -/* Standard ELF types. */ - -#include <stdint.h> -#include <stddef.h> -#include <arch/boot/boot.h> - -/* Type for a 16-bit quantity. */ -typedef uint16_t Elf32_Half; -typedef uint16_t Elf64_Half; - -/* Types for signed and unsigned 32-bit quantities. */ -typedef uint32_t Elf32_Word; -typedef int32_t Elf32_Sword; -typedef uint32_t Elf64_Word; -typedef int32_t Elf64_Sword; - -/* Types for signed and unsigned 64-bit quantities. */ -typedef uint64_t Elf32_Xword; -typedef int64_t Elf32_Sxword; -typedef uint64_t Elf64_Xword; -typedef int64_t Elf64_Sxword; - -/* Type of addresses. */ -typedef uint32_t Elf32_Addr; -typedef uint64_t Elf64_Addr; - -/* Type of file offsets. */ -typedef uint32_t Elf32_Off; -typedef uint64_t Elf64_Off; - -/* Type for section indices, which are 16-bit quantities. */ -typedef uint16_t Elf32_Section; -typedef uint16_t Elf64_Section; - -/* Type of symbol indices. */ -typedef uint32_t Elf32_Symndx; -typedef uint64_t Elf64_Symndx; - - -/* The ELF file header. This appears at the start of every ELF file. */ - -#define EI_NIDENT (16) - -typedef struct -{ - unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ - Elf32_Half e_type; /* Object file type */ - Elf32_Half e_machine; /* Architecture */ - Elf32_Word e_version; /* Object file version */ - Elf32_Addr e_entry; /* Entry point virtual address */ - Elf32_Off e_phoff; /* Program header table file offset */ - Elf32_Off e_shoff; /* Section header table file offset */ - Elf32_Word e_flags; /* Processor-specific flags */ - Elf32_Half e_ehsize; /* ELF header size in bytes */ - Elf32_Half e_phentsize; /* Program header table entry size */ - Elf32_Half e_phnum; /* Program header table entry count */ - Elf32_Half e_shentsize; /* Section header table entry size */ - Elf32_Half e_shnum; /* Section header table entry count */ - Elf32_Half e_shstrndx; /* Section header string table index */ -} Elf32_Ehdr; - -typedef struct -{ - unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ - Elf64_Half e_type; /* Object file type */ - Elf64_Half e_machine; /* Architecture */ - Elf64_Word e_version; /* Object file version */ - Elf64_Addr e_entry; /* Entry point virtual address */ - Elf64_Off e_phoff; /* Program header table file offset */ - Elf64_Off e_shoff; /* Section header table file offset */ - Elf64_Word e_flags; /* Processor-specific flags */ - Elf64_Half e_ehsize; /* ELF header size in bytes */ - Elf64_Half e_phentsize; /* Program header table entry size */ - Elf64_Half e_phnum; /* Program header table entry count */ - Elf64_Half e_shentsize; /* Section header table entry size */ - Elf64_Half e_shnum; /* Section header table entry count */ - Elf64_Half e_shstrndx; /* Section header string table index */ -} Elf64_Ehdr; - -/* Fields in the e_ident array. The EI_* macros are indices into the - array. The macros under each EI_* macro are the values the byte - may have. */ - -#define EI_MAG0 0 /* File identification byte 0 index */ -#define ELFMAG0 0x7f /* Magic number byte 0 */ - -#define EI_MAG1 1 /* File identification byte 1 index */ -#define ELFMAG1 'E' /* Magic number byte 1 */ - -#define EI_MAG2 2 /* File identification byte 2 index */ -#define ELFMAG2 'L' /* Magic number byte 2 */ - -#define EI_MAG3 3 /* File identification byte 3 index */ -#define ELFMAG3 'F' /* Magic number byte 3 */ - -/* Conglomeration of the identification bytes, for easy testing as a word. */ -#define ELFMAG "\177ELF" -#define SELFMAG 4 - -#define EI_CLASS 4 /* File class byte index */ -#define ELFCLASSNONE 0 /* Invalid class */ -#define ELFCLASS32 1 /* 32-bit objects */ -#define ELFCLASS64 2 /* 64-bit objects */ -#define ELFCLASSNUM 3 - -#define EI_DATA 5 /* Data encoding byte index */ -#define ELFDATANONE 0 /* Invalid data encoding */ -#define ELFDATA2LSB 1 /* 2's complement, little endian */ -#define ELFDATA2MSB 2 /* 2's complement, big endian */ -#define ELFDATANUM 3 - -#define EI_VERSION 6 /* File version byte index */ - /* Value must be EV_CURRENT */ - -#define EI_OSABI 7 /* OS ABI identification */ -#define ELFOSABI_SYSV 0 /* UNIX System V ABI */ -#define ELFOSABI_HPUX 1 /* HP-UX */ -#define ELFOSABI_ARM 97 /* ARM */ -#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ - -#define EI_ABIVERSION 8 /* ABI version */ - -#define EI_PAD 9 /* Byte index of padding bytes */ - -/* Legal values for e_type (object file type). */ - -#define ET_NONE 0 /* No file type */ -#define ET_REL 1 /* Relocatable file */ -#define ET_EXEC 2 /* Executable file */ -#define ET_DYN 3 /* Shared object file */ -#define ET_CORE 4 /* Core file */ -#define ET_NUM 5 /* Number of defined types */ -#define ET_LOPROC 0xff00 /* Processor-specific */ -#define ET_HIPROC 0xffff /* Processor-specific */ - -/* Legal values for e_machine (architecture). */ - -#define EM_NONE 0 /* No machine */ -#define EM_M32 1 /* AT&T WE 32100 */ -#define EM_SPARC 2 /* SUN SPARC */ -#define EM_386 3 /* Intel 80386 */ -#define EM_68K 4 /* Motorola m68k family */ -#define EM_88K 5 /* Motorola m88k family */ -#define EM_486 6 /* Intel 80486 */ -#define EM_860 7 /* Intel 80860 */ -#define EM_MIPS 8 /* MIPS R3000 big-endian */ -#define EM_S370 9 /* Amdahl */ -#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */ -#define EM_RS6000 11 /* RS6000 */ - -#define EM_PARISC 15 /* HPPA */ -#define EM_nCUBE 16 /* nCUBE */ -#define EM_VPP500 17 /* Fujitsu VPP500 */ -#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -#define EM_960 19 /* Intel 80960 */ -#define EM_PPC 20 /* PowerPC */ - -#define EM_V800 36 /* NEC V800 series */ -#define EM_FR20 37 /* Fujitsu FR20 */ -#define EM_RH32 38 /* TRW RH32 */ -#define EM_MMA 39 /* Fujitsu MMA */ -#define EM_ARM 40 /* ARM */ -#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -#define EM_SH 42 /* Hitachi SH */ -#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -#define EM_TRICORE 44 /* Siemens Tricore */ -#define EM_ARC 45 /* Argonaut RISC Core */ -#define EM_H8_300 46 /* Hitachi H8/300 */ -#define EM_H8_300H 47 /* Hitachi H8/300H */ -#define EM_H8S 48 /* Hitachi H8S */ -#define EM_H8_500 49 /* Hitachi H8/500 */ -#define EM_IA_64 50 /* Intel Merced */ -#define EM_MIPS_X 51 /* Stanford MIPS-X */ -#define EM_COLDFIRE 52 /* Motorola Coldfire */ -#define EM_68HC12 53 /* Motorola M68HC12 */ -#define EM_NUM 54 - -/* If it is necessary to assign new unofficial EM_* values, please - pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the - chances of collision with official or non-GNU unofficial values. */ - -#define EM_ALPHA 0x9026 - -/* Legal values for e_version (version). */ - -#define EV_NONE 0 /* Invalid ELF version */ -#define EV_CURRENT 1 /* Current version */ -#define EV_NUM 2 - - -/* Program segment header. */ - -typedef struct -{ - Elf32_Word p_type; /* Segment type */ - Elf32_Off p_offset; /* Segment file offset */ - Elf32_Addr p_vaddr; /* Segment virtual address */ - Elf32_Addr p_paddr; /* Segment physical address */ - Elf32_Word p_filesz; /* Segment size in file */ - Elf32_Word p_memsz; /* Segment size in memory */ - Elf32_Word p_flags; /* Segment flags */ - Elf32_Word p_align; /* Segment alignment */ -} Elf32_Phdr; - -typedef struct -{ - Elf64_Word p_type; /* Segment type */ - Elf64_Word p_flags; /* Segment flags */ - Elf64_Off p_offset; /* Segment file offset */ - Elf64_Addr p_vaddr; /* Segment virtual address */ - Elf64_Addr p_paddr; /* Segment physical address */ - Elf64_Xword p_filesz; /* Segment size in file */ - Elf64_Xword p_memsz; /* Segment size in memory */ - Elf64_Xword p_align; /* Segment alignment */ -} Elf64_Phdr; - -/* Legal values for p_type (segment type). */ - -#define PT_NULL 0 /* Program header table entry unused */ -#define PT_LOAD 1 /* Loadable program segment */ -#define PT_DYNAMIC 2 /* Dynamic linking information */ -#define PT_INTERP 3 /* Program interpreter */ -#define PT_NOTE 4 /* Auxiliary information */ -#define PT_SHLIB 5 /* Reserved */ -#define PT_PHDR 6 /* Entry for header table itself */ -#define PT_NUM 7 /* Number of defined types. */ -#define PT_LOOS 0x60000000 /* Start of OS-specific */ -#define PT_HIOS 0x6fffffff /* End of OS-specific */ -#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -#define PT_HIPROC 0x7fffffff /* End of processor-specific */ - -/* Legal values for p_flags (segment flags). */ - -#define PF_X (1 << 0) /* Segment is executable */ -#define PF_W (1 << 1) /* Segment is writable */ -#define PF_R (1 << 2) /* Segment is readable */ -#define PF_MASKPROC 0xf0000000 /* Processor-specific */ - - -/* Note section contents. Each entry in the note section begins with - a header of a fixed form. */ - -typedef struct -{ - Elf32_Word n_namesz; /* Length of the note's name. */ - Elf32_Word n_descsz; /* Length of the note's descriptor. */ - Elf32_Word n_type; /* Type of the note. */ -} Elf32_Nhdr; - -typedef struct -{ - Elf64_Word n_namesz; /* Length of the note's name. */ - Elf64_Word n_descsz; /* Length of the note's descriptor. */ - Elf64_Word n_type; /* Type of the note. */ -} Elf64_Nhdr; - -/* Known names of notes. */ - -/* Solaris entries in the note section have this name. */ -#define ELF_NOTE_SOLARIS "SUNW Solaris" - -/* Note entries for GNU systems have this name. */ -#define ELF_NOTE_GNU "GNU" - - -/* Defined types of notes for Solaris. */ - -/* Value of descriptor (one word) is desired pagesize for the binary. */ -#define ELF_NOTE_PAGESIZE_HINT 1 - - -/* Defined note types for GNU systems. */ - -/* ABI information. The descriptor consists of words: - word 0: OS descriptor - word 1: major version of the ABI - word 2: minor version of the ABI - word 3: subminor version of the ABI -*/ -#define ELF_NOTE_ABI 1 - -/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI - note section entry. */ -#define ELF_NOTE_OS_LINUX 0 -#define ELF_NOTE_OS_GNU 1 -#define ELF_NOTE_OS_SOLARIS2 2 - - -/* Motorola 68k specific definitions. */ - -/* Intel 80386 specific definitions. */ - -/* SUN SPARC specific definitions. */ - -/* Values for Elf64_Ehdr.e_flags. */ - -#define EF_SPARCV9_MM 3 -#define EF_SPARCV9_TSO 0 -#define EF_SPARCV9_PSO 1 -#define EF_SPARCV9_RMO 2 -#define EF_SPARC_EXT_MASK 0xFFFF00 -#define EF_SPARC_SUN_US1 0x000200 -#define EF_SPARC_HAL_R1 0x000400 - -/* MIPS R3000 specific definitions. */ - -/* Legal values for e_flags field of Elf32_Ehdr. */ - -#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -#define EF_MIPS_PIC 2 /* Contains PIC code */ -#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -#define EF_MIPS_XGOT 8 -#define EF_MIPS_64BIT_WHIRL 16 -#define EF_MIPS_ABI2 32 -#define EF_MIPS_ABI_ON32 64 -#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ - -/* Legal values for MIPS architecture level. */ - -#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ - -/* Legal values for p_type field of Elf32_Phdr. */ - -#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -#define PT_MIPS_OPTIONS 0x70000002 - -/* Special program header types. */ - -#define PF_MIPS_LOCAL 0x10000000 - - -/* HPPA specific definitions. */ - -/* Legal values for e_flags field of Elf32_Ehdr. */ - -#define EF_PARISC_TRAPNL 1 /* Trap nil pointer dereference. */ -#define EF_PARISC_EXT 2 /* Program uses arch. extensions. */ -#define EF_PARISC_ARCH 0xffff0000 /* Architecture version. */ -/* Defined values are: - 0x020b PA-RISC 1.0 big-endian - 0x0210 PA-RISC 1.1 big-endian - 0x028b PA-RISC 1.0 little-endian - 0x0290 PA-RISC 1.1 little-endian -*/ - - -/* Alpha specific definitions. */ - -/* Legal values for e_flags field of Elf64_Ehdr. */ - -#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ - - -/* PowerPC specific declarations */ - -/* ARM specific declarations */ - -/* Processor specific flags for the ELF header e_flags field. */ -#define EF_ARM_RELEXEC 0x01 -#define EF_ARM_HASENTRY 0x02 -#define EF_ARM_INTERWORK 0x04 -#define EF_ARM_APCS_26 0x08 -#define EF_ARM_APCS_FLOAT 0x10 -#define EF_ARM_PIC 0x20 -#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -#define EF_NEW_ABI 0x80 -#define EF_OLD_ABI 0x100 - -/* ARM-specific program header flags */ -#define PF_ARM_SB 0x10000000 /* Segment contains the location - addressed by the static base */ - -#if ELF_CLASS == ELFCLASS32 -typedef Elf32_Ehdr Elf_ehdr; -typedef Elf32_Phdr Elf_phdr; -#endif - -#if ELF_CLASS == ELFCLASS64 -typedef Elf64_Ehdr Elf_ehdr; -typedef Elf64_Phdr Elf_phdr; -#endif - -int elf_check_arch(Elf_ehdr *ehdr); -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long bounce_size); -struct lb_memory; -int elfboot(struct lb_memory *mem); -/* Temporary compile fix, FILO should be dropped from coreboot */ -int filo(struct lb_memory *mem); - -#define FIRMWARE_TYPE "coreboot" -#define BOOTLOADER "elfboot" -#define BOOTLOADER_VERSION "1.3" - -#endif /* elf.h */ diff --git a/src/include/boot/elf_boot.h b/src/include/boot/elf_boot.h deleted file mode 100644 index b119bab..0000000 --- a/src/include/boot/elf_boot.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef ELF_BOOT_H -#define ELF_BOOT_H - -#include <stdint.h> - -/* This defines the structure of a table of parameters useful for ELF - * bootable images. These parameters are all passed and generated - * by the bootloader to the booted image. For simplicity and - * consistency the Elf Note format is reused. - * - * All of the information must be Position Independent Data. - * That is it must be safe to relocate the whole ELF boot parameter - * block without changing the meaning or correctnes of the data. - * Additionally it must be safe to permute the order of the ELF notes - * to any possible permutation without changing the meaning or correctness - * of the data. - * - */ - -#define ELF_HEAD_SIZE (8*1024) -#define ELF_BOOT_MAGIC 0x0E1FB007 - -typedef uint16_t Elf_Half; -typedef uint32_t Elf_Word; -typedef uint64_t Elf_Xword; - -typedef struct -{ - Elf_Word b_signature; /* "0x0E1FB007" */ - Elf_Word b_size; - Elf_Half b_checksum; - Elf_Half b_records; -} Elf_Bhdr; - -typedef struct -{ - Elf_Word n_namesz; /* Length of the note's name. */ - Elf_Word n_descsz; /* Length of the note's descriptor. */ - Elf_Word n_type; /* Type of the note. */ -} Elf_Nhdr; - - -/* For standard notes n_namesz must be zero */ -/* All of the following standard note types provide a single null - * terminated string in the descriptor. - */ -#define EBN_FIRMWARE_TYPE 0x00000001 -/* On platforms that support multiple classes of firmware this field - * specifies the class of firmware you are loaded under. - */ -#define EBN_BOOTLOADER_NAME 0x00000002 -/* This specifies just the name of the bootloader for easy comparison */ -#define EBN_BOOTLOADER_VERSION 0x00000003 -/* This specifies the version of the bootlader */ -#define EBN_COMMAND_LINE 0x00000004 -/* This specifies a command line that can be set by user interaction, - * and is provided as a free form string to the loaded image. - */ - - -/* Standardized Elf image notes for booting... The name for all of these is ELFBoot */ - -#define ELF_NOTE_BOOT "ELFBoot" - -#define EIN_PROGRAM_NAME 0x00000001 -/* The program in this ELF file */ -#define EIN_PROGRAM_VERSION 0x00000002 -/* The version of the program in this ELF file */ -#define EIN_PROGRAM_CHECKSUM 0x00000003 -/* ip style checksum of the memory image. */ - - -/* Linux image notes for booting... The name for all of these is Linux */ - -#define LINUX_NOTE_BOOT "Linux" - -#define LIN_COMMAND_LINE 0x00000001 -/* The command line to pass to the loaded kernel. */ -#define LIN_ROOT_DEV 0x00000002 -/* The root dev to pass to the loaded kernel. */ -#define LIN_RAMDISK_FLAGS 0x00000003 -/* Various old ramdisk flags */ -#define LIN_INITRD_START 0x00000004 -/* Start of the ramdisk in bytes */ -#define LIN_INITRD_SIZE 0x00000005 -/* Size of the ramdisk in bytes */ - - -#endif /* ELF_BOOT_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a1803ed..898e910 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -31,7 +31,6 @@ #include <stdlib.h> #include <reset.h> #include <boot/tables.h> -#include <boot/elf.h> #include <cbfs.h> #include <lib.h> #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 4ebe109..6d60285 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -19,11 +19,10 @@ */ #include <arch/byteorder.h> +#include <arch/stages.h> #include <console/console.h> #include <cpu/cpu.h> #include <fallback.h> -#include <boot/elf.h> -#include <boot/elf_boot.h> #include <boot/coreboot_tables.h> #include <stdint.h> #include <stdlib.h>

1 0

New patch to review for coreboot: 3895151 ARMv7: flatten arch/armv7 source tree
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3659 -gerrit commit 38951512433087bce6c6a9d17572cc469e80cc47 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 24 14:38:48 2013 -0700 ARMv7: flatten arch/armv7 source tree With only 19 source files it doesn't make a whole lot of sense to create sub directories in arch/armv7, especially since the files were distributed somewhat randomly. Change-Id: I029c7848e915edf1737e1c401c034837c95d179d Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 25 ++- src/arch/armv7/boot.c | 189 +++++++++++++++++++++++ src/arch/armv7/boot/Makefile.inc | 12 -- src/arch/armv7/boot/boot.c | 189 ----------------------- src/arch/armv7/boot/tables.c | 79 ---------- src/arch/armv7/cache.c | 308 +++++++++++++++++++++++++++++++++++++ src/arch/armv7/div0.c | 33 ++++ src/arch/armv7/eabi_compat.c | 31 ++++ src/arch/armv7/early_console.c | 81 ++++++++++ src/arch/armv7/id.inc | 18 +++ src/arch/armv7/interrupts.c | 197 ++++++++++++++++++++++++ src/arch/armv7/lib/Makefile.inc | 20 --- src/arch/armv7/lib/cache.c | 308 ------------------------------------- src/arch/armv7/lib/div0.c | 33 ---- src/arch/armv7/lib/eabi_compat.c | 31 ---- src/arch/armv7/lib/early_console.c | 81 ---------- src/arch/armv7/lib/id.inc | 18 --- src/arch/armv7/lib/interrupts.c | 197 ------------------------ src/arch/armv7/lib/memcpy.S | 243 ----------------------------- src/arch/armv7/lib/memset.S | 126 --------------- src/arch/armv7/lib/mmu.c | 157 ------------------- src/arch/armv7/memcpy.S | 243 +++++++++++++++++++++++++++++ src/arch/armv7/memset.S | 126 +++++++++++++++ src/arch/armv7/mmu.c | 157 +++++++++++++++++++ src/arch/armv7/tables.c | 79 ++++++++++ 25 files changed, 1486 insertions(+), 1495 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 1045774..a249655 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -161,6 +161,29 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD ramstage-y += exception.c ramstage-y += exception_asm.S +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-y += cache.c + +romstage-y += cache.c +romstage-y += div0.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c + +ramstage-y += div0.c +#ramstage-y += interrupts.c +#ramstage-y += memcpy.S +#ramstage-y += memset.S +ramstage-y += cache.c +ramstage-y += mmu.c + +romstage-y += eabi_compat.c +ramstage-y += eabi_compat.c +bootblock-y += eabi_compat.c + +ramstage-y += boot.c +ramstage-y += tables.c + +$(obj)/arch/armv7/coreboot_table.ramstage.o : $(OPTION_TABLE_H) + romstage-srcs += $(objgenerated)/crt0.s ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) @@ -194,7 +217,7 @@ bootblock_lds = $(src)/arch/armv7/bootblock.lds bootblock_lds += $(chipset_bootblock_lds) bootblock_inc += $(src)/arch/armv7/bootblock.inc -bootblock_inc += $(src)/arch/armv7/lib/id.inc +bootblock_inc += $(src)/arch/armv7/id.inc bootblock_inc += $(chipset_bootblock_inc) bootblock_inc += $(objgenerated)/bootblock.inc diff --git a/src/arch/armv7/boot.c b/src/arch/armv7/boot.c new file mode 100644 index 0000000..ab531be --- /dev/null +++ b/src/arch/armv7/boot.c @@ -0,0 +1,189 @@ +#include <console/console.h> +#include <ip_checksum.h> +#include <boot/elf.h> +#include <boot/elf_boot.h> +#include <string.h> +#include <cpu/x86/multiboot.h> +#include <arch/stages.h> + + +#ifndef CMD_LINE +#define CMD_LINE "" +#endif + + + +#define UPSZ(X) ((sizeof(X) + 3) &~3) + +static struct { + Elf_Bhdr hdr; + Elf_Nhdr ft_hdr; + unsigned char ft_desc[UPSZ(FIRMWARE_TYPE)]; + Elf_Nhdr bl_hdr; + unsigned char bl_desc[UPSZ(BOOTLOADER)]; + Elf_Nhdr blv_hdr; + unsigned char blv_desc[UPSZ(BOOTLOADER_VERSION)]; + Elf_Nhdr cmd_hdr; + unsigned char cmd_desc[UPSZ(CMD_LINE)]; +} elf_boot_notes = { + .hdr = { + .b_signature = 0x0E1FB007, + .b_size = sizeof(elf_boot_notes), + .b_checksum = 0, + .b_records = 4, + }, + .ft_hdr = { + .n_namesz = 0, + .n_descsz = sizeof(FIRMWARE_TYPE), + .n_type = EBN_FIRMWARE_TYPE, + }, + .ft_desc = FIRMWARE_TYPE, + .bl_hdr = { + .n_namesz = 0, + .n_descsz = sizeof(BOOTLOADER), + .n_type = EBN_BOOTLOADER_NAME, + }, + .bl_desc = BOOTLOADER, + .blv_hdr = { + .n_namesz = 0, + .n_descsz = sizeof(BOOTLOADER_VERSION), + .n_type = EBN_BOOTLOADER_VERSION, + }, + .blv_desc = BOOTLOADER_VERSION, + .cmd_hdr = { + .n_namesz = 0, + .n_descsz = sizeof(CMD_LINE), + .n_type = EBN_COMMAND_LINE, + }, + .cmd_desc = CMD_LINE, +}; + + +int elf_check_arch(Elf_ehdr *ehdr) +{ + return ( + ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && + (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && + (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) + ); + +} + +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +{ + extern unsigned char _ram_seg, _eram_seg; + unsigned long lb_start, lb_size; + unsigned long adjust, adjusted_boot_notes; + + elf_boot_notes.hdr.b_checksum = + compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); + + lb_start = (unsigned long)&_ram_seg; + lb_size = (unsigned long)(&_eram_seg - &_ram_seg); + adjust = buffer + size - lb_start; + + adjusted_boot_notes = (unsigned long)&elf_boot_notes; + adjusted_boot_notes += adjust; + + printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); + printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); + printk(BIOS_SPEW, "lb_size = 0x%08lx\n", lb_size); + printk(BIOS_SPEW, "adjust = 0x%08lx\n", adjust); + printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); + printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); + printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); + + stage_exit(entry); +#if 0 + /* FIXME: do we need any of this? */ + /* Jump to kernel */ + __asm__ __volatile__( + " cld \n\t" + /* Save the callee save registers... */ + " pushl %%esi\n\t" + " pushl %%edi\n\t" + " pushl %%ebx\n\t" + /* Save the parameters I was passed */ + " pushl $0\n\t" /* 20 adjust */ + " pushl %0\n\t" /* 16 lb_start */ + " pushl %1\n\t" /* 12 buffer */ + " pushl %2\n\t" /* 8 lb_size */ + " pushl %3\n\t" /* 4 entry */ + " pushl %4\n\t" /* 0 elf_boot_notes */ + /* Compute the adjustment */ + " xorl %%eax, %%eax\n\t" + " subl 16(%%esp), %%eax\n\t" + " addl 12(%%esp), %%eax\n\t" + " addl 8(%%esp), %%eax\n\t" + " movl %%eax, 20(%%esp)\n\t" + /* Place a copy of coreboot in its new location */ + /* Move ``longs'' the coreboot size is 4 byte aligned */ + " movl 12(%%esp), %%edi\n\t" + " addl 8(%%esp), %%edi\n\t" + " movl 16(%%esp), %%esi\n\t" + " movl 8(%%esp), %%ecx\n\n" + " shrl $2, %%ecx\n\t" + " rep movsl\n\t" + + /* Adjust the stack pointer to point into the new coreboot image */ + " addl 20(%%esp), %%esp\n\t" + /* Adjust the instruction pointer to point into the new coreboot image */ + " movl $1f, %%eax\n\t" + " addl 20(%%esp), %%eax\n\t" + " jmp *%%eax\n\t" + "1: \n\t" + + /* Copy the coreboot bounce buffer over coreboot */ + /* Move ``longs'' the coreboot size is 4 byte aligned */ + " movl 16(%%esp), %%edi\n\t" + " movl 12(%%esp), %%esi\n\t" + " movl 8(%%esp), %%ecx\n\t" + " shrl $2, %%ecx\n\t" + " rep movsl\n\t" + + /* Now jump to the loaded image */ + " movl %5, %%eax\n\t" + " movl 0(%%esp), %%ebx\n\t" + " call *4(%%esp)\n\t" + + /* The loaded image returned? */ + " cli \n\t" + " cld \n\t" + + /* Copy the saved copy of coreboot where coreboot runs */ + /* Move ``longs'' the coreboot size is 4 byte aligned */ + " movl 16(%%esp), %%edi\n\t" + " movl 12(%%esp), %%esi\n\t" + " addl 8(%%esp), %%esi\n\t" + " movl 8(%%esp), %%ecx\n\t" + " shrl $2, %%ecx\n\t" + " rep movsl\n\t" + + /* Adjust the stack pointer to point into the old coreboot image */ + " subl 20(%%esp), %%esp\n\t" + + /* Adjust the instruction pointer to point into the old coreboot image */ + " movl $1f, %%eax\n\t" + " subl 20(%%esp), %%eax\n\t" + " jmp *%%eax\n\t" + "1: \n\t" + + /* Drop the parameters I was passed */ + " addl $24, %%esp\n\t" + + /* Restore the callee save registers */ + " popl %%ebx\n\t" + " popl %%edi\n\t" + " popl %%esi\n\t" + + :: + "ri" (lb_start), "ri" (buffer), "ri" (lb_size), + "ri" (entry), +#if CONFIG_MULTIBOOT + "ri"(mbi), "ri" (MB_MAGIC2) +#else + "ri"(adjusted_boot_notes), "ri" (0x0E1FB007) +#endif + ); +#endif +} diff --git a/src/arch/armv7/boot/Makefile.inc b/src/arch/armv7/boot/Makefile.inc deleted file mode 100644 index 8d24fae..0000000 --- a/src/arch/armv7/boot/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -ramstage-y += boot.c -#ramstage-$(CONFIG_MULTIBOOT) += multiboot.c -ramstage-y += tables.c -#ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c -#ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c -#ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S - -#FIXME(dhendrix): is there anything preventing multiboot from -#working on ARM? - -$(obj)/arch/armv7/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) -#$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/armv7/boot/boot.c b/src/arch/armv7/boot/boot.c deleted file mode 100644 index ab531be..0000000 --- a/src/arch/armv7/boot/boot.c +++ /dev/null @@ -1,189 +0,0 @@ -#include <console/console.h> -#include <ip_checksum.h> -#include <boot/elf.h> -#include <boot/elf_boot.h> -#include <string.h> -#include <cpu/x86/multiboot.h> -#include <arch/stages.h> - - -#ifndef CMD_LINE -#define CMD_LINE "" -#endif - - - -#define UPSZ(X) ((sizeof(X) + 3) &~3) - -static struct { - Elf_Bhdr hdr; - Elf_Nhdr ft_hdr; - unsigned char ft_desc[UPSZ(FIRMWARE_TYPE)]; - Elf_Nhdr bl_hdr; - unsigned char bl_desc[UPSZ(BOOTLOADER)]; - Elf_Nhdr blv_hdr; - unsigned char blv_desc[UPSZ(BOOTLOADER_VERSION)]; - Elf_Nhdr cmd_hdr; - unsigned char cmd_desc[UPSZ(CMD_LINE)]; -} elf_boot_notes = { - .hdr = { - .b_signature = 0x0E1FB007, - .b_size = sizeof(elf_boot_notes), - .b_checksum = 0, - .b_records = 4, - }, - .ft_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(FIRMWARE_TYPE), - .n_type = EBN_FIRMWARE_TYPE, - }, - .ft_desc = FIRMWARE_TYPE, - .bl_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(BOOTLOADER), - .n_type = EBN_BOOTLOADER_NAME, - }, - .bl_desc = BOOTLOADER, - .blv_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(BOOTLOADER_VERSION), - .n_type = EBN_BOOTLOADER_VERSION, - }, - .blv_desc = BOOTLOADER_VERSION, - .cmd_hdr = { - .n_namesz = 0, - .n_descsz = sizeof(CMD_LINE), - .n_type = EBN_COMMAND_LINE, - }, - .cmd_desc = CMD_LINE, -}; - - -int elf_check_arch(Elf_ehdr *ehdr) -{ - return ( - ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && - (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && - (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) - ); - -} - -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) -{ - extern unsigned char _ram_seg, _eram_seg; - unsigned long lb_start, lb_size; - unsigned long adjust, adjusted_boot_notes; - - elf_boot_notes.hdr.b_checksum = - compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); - - lb_start = (unsigned long)&_ram_seg; - lb_size = (unsigned long)(&_eram_seg - &_ram_seg); - adjust = buffer + size - lb_start; - - adjusted_boot_notes = (unsigned long)&elf_boot_notes; - adjusted_boot_notes += adjust; - - printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); - printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); - printk(BIOS_SPEW, "lb_size = 0x%08lx\n", lb_size); - printk(BIOS_SPEW, "adjust = 0x%08lx\n", adjust); - printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); - printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); - printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); - - stage_exit(entry); -#if 0 - /* FIXME: do we need any of this? */ - /* Jump to kernel */ - __asm__ __volatile__( - " cld \n\t" - /* Save the callee save registers... */ - " pushl %%esi\n\t" - " pushl %%edi\n\t" - " pushl %%ebx\n\t" - /* Save the parameters I was passed */ - " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ - " pushl %1\n\t" /* 12 buffer */ - " pushl %2\n\t" /* 8 lb_size */ - " pushl %3\n\t" /* 4 entry */ - " pushl %4\n\t" /* 0 elf_boot_notes */ - /* Compute the adjustment */ - " xorl %%eax, %%eax\n\t" - " subl 16(%%esp), %%eax\n\t" - " addl 12(%%esp), %%eax\n\t" - " addl 8(%%esp), %%eax\n\t" - " movl %%eax, 20(%%esp)\n\t" - /* Place a copy of coreboot in its new location */ - /* Move ``longs'' the coreboot size is 4 byte aligned */ - " movl 12(%%esp), %%edi\n\t" - " addl 8(%%esp), %%edi\n\t" - " movl 16(%%esp), %%esi\n\t" - " movl 8(%%esp), %%ecx\n\n" - " shrl $2, %%ecx\n\t" - " rep movsl\n\t" - - /* Adjust the stack pointer to point into the new coreboot image */ - " addl 20(%%esp), %%esp\n\t" - /* Adjust the instruction pointer to point into the new coreboot image */ - " movl $1f, %%eax\n\t" - " addl 20(%%esp), %%eax\n\t" - " jmp *%%eax\n\t" - "1: \n\t" - - /* Copy the coreboot bounce buffer over coreboot */ - /* Move ``longs'' the coreboot size is 4 byte aligned */ - " movl 16(%%esp), %%edi\n\t" - " movl 12(%%esp), %%esi\n\t" - " movl 8(%%esp), %%ecx\n\t" - " shrl $2, %%ecx\n\t" - " rep movsl\n\t" - - /* Now jump to the loaded image */ - " movl %5, %%eax\n\t" - " movl 0(%%esp), %%ebx\n\t" - " call *4(%%esp)\n\t" - - /* The loaded image returned? */ - " cli \n\t" - " cld \n\t" - - /* Copy the saved copy of coreboot where coreboot runs */ - /* Move ``longs'' the coreboot size is 4 byte aligned */ - " movl 16(%%esp), %%edi\n\t" - " movl 12(%%esp), %%esi\n\t" - " addl 8(%%esp), %%esi\n\t" - " movl 8(%%esp), %%ecx\n\t" - " shrl $2, %%ecx\n\t" - " rep movsl\n\t" - - /* Adjust the stack pointer to point into the old coreboot image */ - " subl 20(%%esp), %%esp\n\t" - - /* Adjust the instruction pointer to point into the old coreboot image */ - " movl $1f, %%eax\n\t" - " subl 20(%%esp), %%eax\n\t" - " jmp *%%eax\n\t" - "1: \n\t" - - /* Drop the parameters I was passed */ - " addl $24, %%esp\n\t" - - /* Restore the callee save registers */ - " popl %%ebx\n\t" - " popl %%edi\n\t" - " popl %%esi\n\t" - - :: - "ri" (lb_start), "ri" (buffer), "ri" (lb_size), - "ri" (entry), -#if CONFIG_MULTIBOOT - "ri"(mbi), "ri" (MB_MAGIC2) -#else - "ri"(adjusted_boot_notes), "ri" (0x0E1FB007) -#endif - ); -#endif -} diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c deleted file mode 100644 index 0fc7399..0000000 --- a/src/arch/armv7/boot/tables.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <cpu/cpu.h> -#include <boot/tables.h> -#include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> - -#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) - -/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; - -void cbmem_arch_init(void) -{ -} - -struct lb_memory *write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return NULL; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); - - return get_lb_mem(); -} diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c new file mode 100644 index 0000000..04eaa88 --- /dev/null +++ b/src/arch/armv7/cache.c @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R + * + * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition + */ + +#include <stdint.h> + +#include <arch/cache.h> + +#define bitmask(high, low) ((1UL << (high)) + \ + ((1UL << (high)) - 1) - ((1UL << (low)) - 1)) + +/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */ +/* FIXME: src/include/lib.h is difficult to work with due to romcc */ +static unsigned long log2(unsigned long u) +{ + int i = 0; + + while (u >>= 1) + i++; + + return i; +} + +void tlb_invalidate_all(void) +{ + /* + * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7, however this does + * not seem to be the case as of Cortex-A15. + */ + tlbiall(); + dtlbiall(); + itlbiall(); + isb(); + dsb(); +} + +void icache_invalidate_all(void) +{ + /* + * icache can be entirely invalidated with one operation. + * Note: If branch predictors are architecturally-visible, ICIALLU + * also performs a BPIALL operation (B2-1283 in arch manual) + */ + iciallu(); + isb(); +} + +enum dcache_op { + OP_DCCISW, + OP_DCISW, + OP_DCCIMVAC, + OP_DCCMVAC, +}; + +/* + * Do a dcache operation on entire cache by set/way. This is done for + * portability because mapping of memory address to cache location is + * implementation defined (See note on "Requirements for operations by + * set/way" in arch ref. manual). + */ +static void dcache_op_set_way(enum dcache_op op) +{ + uint32_t ccsidr; + unsigned int associativity, num_sets, linesize_bytes; + unsigned int set, way; + unsigned int level; + + level = (read_csselr() >> 1) & 0x7; + + /* + * dcache must be invalidated by set/way for portability since virtual + * memory mapping is system-defined. The number of sets and + * associativity is given by CCSIDR. We'll use DCISW to invalidate the + * dcache. + */ + ccsidr = read_ccsidr(); + + /* FIXME: rounding up required here? */ + num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1; + associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1; + /* FIXME: do we need to use CTR.DminLine here? */ + linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + + dsb(); + + /* + * Set/way operations require an interesting bit packing. See section + * B4-35 in the ARMv7 Architecture Reference Manual: + * + * A: Log2(associativity) + * B: L+S + * L: Log2(linesize) + * S: Log2(num_sets) + * + * The bits are packed as follows: + * 31 31-A B B-1 L L-1 4 3 1 0 + * |---|-------------|--------|-------|-----|-| + * |Way| zeros | Set | zeros |level|0| + * |---|-------------|--------|-------|-----|-| + */ + for (way = 0; way < associativity; way++) { + for (set = 0; set < num_sets; set++) { + uint32_t val = 0; + val |= way << (32 - log2(associativity)); + val |= set << log2(linesize_bytes); + val |= level << 1; + switch(op) { + case OP_DCCISW: + dccisw(val); + break; + case OP_DCISW: + dcisw(val); + break; + default: + break; + } + } + } + isb(); +} + +static void dcache_foreach(enum dcache_op op) +{ + uint32_t clidr; + int level; + + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x2: + case 0x3: + case 0x4: + csselr = level << 1; + write_csselr(csselr); + dcache_op_set_way(op); + break; + default: + /* no cache, icache only, or reserved */ + break; + } + } +} + +void dcache_clean_invalidate_all(void) +{ + dcache_foreach(OP_DCCISW); +} + +void dcache_invalidate_all(void) +{ + dcache_foreach(OP_DCISW); +} + +static unsigned int line_bytes(void) +{ + uint32_t ccsidr; + unsigned int size; + + ccsidr = read_ccsidr(); + /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ + size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + size *= sizeof(unsigned int); /* bytes per line */ + + return size; +} + +/* + * Do a dcache operation by modified virtual address. This is useful for + * maintaining coherency in drivers which do DMA transfers and only need to + * perform cache maintenance on a particular memory range rather than the + * entire cache. + */ +static void dcache_op_mva(unsigned long addr, + unsigned long len, enum dcache_op op) +{ + unsigned long line, linesize; + + linesize = line_bytes(); + line = addr & ~(linesize - 1); + + dsb(); + while (line < addr + len) { + switch(op) { + case OP_DCCIMVAC: + dccimvac(line); + break; + default: + break; + } + line += linesize; + } + isb(); +} + +void dcache_clean_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCCMVAC); +} + +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCCIMVAC); +} + +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + dcache_clean_invalidate_all(); + sctlr = read_sctlr(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); +} + +void armv7_invalidate_caches(void) +{ + uint32_t clidr; + int level; + + /* Invalidate branch predictor */ + bpiall(); + + /* Iterate thru each cache identified in CLIDR and invalidate */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + csselr = level << 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + case 0x3: + /* separate icache and dcache */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + + csselr = level << 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + tlb_invalidate_all(); +} diff --git a/src/arch/armv7/div0.c b/src/arch/armv7/div0.c new file mode 100644 index 0000000..ab06ad3 --- /dev/null +++ b/src/arch/armv7/div0.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <console/console.h> + +void __div0(void); // called from asm so no need for a prototype in a header + +/* Replacement (=dummy) for GNU/Linux division-by zero handler */ +/* recursion is ok here because we have no formats ... */ +void __div0 (void) +{ + printk(BIOS_EMERG, "DIVIDE BY ZERO! continuing ... \n"); +} diff --git a/src/arch/armv7/eabi_compat.c b/src/arch/armv7/eabi_compat.c new file mode 100644 index 0000000..c063c85 --- /dev/null +++ b/src/arch/armv7/eabi_compat.c @@ -0,0 +1,31 @@ +/* + * Utility functions needed for (some) EABI conformant tool chains. + * + * (C) Copyright 2009 Wolfgang Denk <wd(a)denx.de> + * + * This program is Free Software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + */ + +#include <console/console.h> + +/* FIXME(dhendrix): prototypes added for assembler */ +int raise (int signum); +int raise (int signum) +{ + printk(BIOS_CRIT, "raise: Signal # %d caught\n", signum); + return 0; +} + +/* Dummy function to avoid linker complaints */ +void __aeabi_unwind_cpp_pr0(void); +void __aeabi_unwind_cpp_pr0(void) +{ +}; + +void __aeabi_unwind_cpp_pr1(void); +void __aeabi_unwind_cpp_pr1(void) +{ +}; diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/id.inc b/src/arch/armv7/id.inc new file mode 100644 index 0000000..ffe547d --- /dev/null +++ b/src/arch/armv7/id.inc @@ -0,0 +1,18 @@ + .section ".id", "a", %progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end - ver /* Reverse offset to the vendor id */ +.long __id_end - vendor /* Reverse offset to the vendor id */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/armv7/interrupts.c b/src/arch/armv7/interrupts.c new file mode 100644 index 0000000..7508c69 --- /dev/null +++ b/src/arch/armv7/interrupts.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USE_IRQ +int interrupt_init (void) +{ + /* + * setup up stacks if necessary + */ + IRQ_STACK_START = gd->irq_sp - 4; + IRQ_STACK_START_IN = gd->irq_sp + 8; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; + + return arch_interrupt_init(); +} + +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +int interrupt_init (void) +{ + /* + * setup up stacks if necessary + */ + IRQ_STACK_START_IN = gd->irq_sp + 8; + + return 0; +} + +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + soft_reset(); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +#ifndef CONFIG_USE_IRQ +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} +#endif diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc deleted file mode 100644 index b10c1ab..0000000 --- a/src/arch/armv7/lib/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -#FIXME: cache_v7 and cache-cp15 will go away eventually - -bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c -bootblock-y += cache.c - -romstage-y += cache.c -romstage-y += div0.c -romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c - -ramstage-y += div0.c -#ramstage-y += interrupts.c -#ramstage-y += memcpy.S -#ramstage-y += memset.S -ramstage-y += cache.c -ramstage-y += mmu.c - -#FIXME(dhendrix): should this be a config option? -romstage-y += eabi_compat.c -ramstage-y += eabi_compat.c -bootblock-y += eabi_compat.c diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c deleted file mode 100644 index 04eaa88..0000000 --- a/src/arch/armv7/lib/cache.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R - * - * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition - */ - -#include <stdint.h> - -#include <arch/cache.h> - -#define bitmask(high, low) ((1UL << (high)) + \ - ((1UL << (high)) - 1) - ((1UL << (low)) - 1)) - -/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */ -/* FIXME: src/include/lib.h is difficult to work with due to romcc */ -static unsigned long log2(unsigned long u) -{ - int i = 0; - - while (u >>= 1) - i++; - - return i; -} - -void tlb_invalidate_all(void) -{ - /* - * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction - * instruction vs. data TLBs is deprecated in ARMv7, however this does - * not seem to be the case as of Cortex-A15. - */ - tlbiall(); - dtlbiall(); - itlbiall(); - isb(); - dsb(); -} - -void icache_invalidate_all(void) -{ - /* - * icache can be entirely invalidated with one operation. - * Note: If branch predictors are architecturally-visible, ICIALLU - * also performs a BPIALL operation (B2-1283 in arch manual) - */ - iciallu(); - isb(); -} - -enum dcache_op { - OP_DCCISW, - OP_DCISW, - OP_DCCIMVAC, - OP_DCCMVAC, -}; - -/* - * Do a dcache operation on entire cache by set/way. This is done for - * portability because mapping of memory address to cache location is - * implementation defined (See note on "Requirements for operations by - * set/way" in arch ref. manual). - */ -static void dcache_op_set_way(enum dcache_op op) -{ - uint32_t ccsidr; - unsigned int associativity, num_sets, linesize_bytes; - unsigned int set, way; - unsigned int level; - - level = (read_csselr() >> 1) & 0x7; - - /* - * dcache must be invalidated by set/way for portability since virtual - * memory mapping is system-defined. The number of sets and - * associativity is given by CCSIDR. We'll use DCISW to invalidate the - * dcache. - */ - ccsidr = read_ccsidr(); - - /* FIXME: rounding up required here? */ - num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1; - associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1; - /* FIXME: do we need to use CTR.DminLine here? */ - linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; - - dsb(); - - /* - * Set/way operations require an interesting bit packing. See section - * B4-35 in the ARMv7 Architecture Reference Manual: - * - * A: Log2(associativity) - * B: L+S - * L: Log2(linesize) - * S: Log2(num_sets) - * - * The bits are packed as follows: - * 31 31-A B B-1 L L-1 4 3 1 0 - * |---|-------------|--------|-------|-----|-| - * |Way| zeros | Set | zeros |level|0| - * |---|-------------|--------|-------|-----|-| - */ - for (way = 0; way < associativity; way++) { - for (set = 0; set < num_sets; set++) { - uint32_t val = 0; - val |= way << (32 - log2(associativity)); - val |= set << log2(linesize_bytes); - val |= level << 1; - switch(op) { - case OP_DCCISW: - dccisw(val); - break; - case OP_DCISW: - dcisw(val); - break; - default: - break; - } - } - } - isb(); -} - -static void dcache_foreach(enum dcache_op op) -{ - uint32_t clidr; - int level; - - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x2: - case 0x3: - case 0x4: - csselr = level << 1; - write_csselr(csselr); - dcache_op_set_way(op); - break; - default: - /* no cache, icache only, or reserved */ - break; - } - } -} - -void dcache_clean_invalidate_all(void) -{ - dcache_foreach(OP_DCCISW); -} - -void dcache_invalidate_all(void) -{ - dcache_foreach(OP_DCISW); -} - -static unsigned int line_bytes(void) -{ - uint32_t ccsidr; - unsigned int size; - - ccsidr = read_ccsidr(); - /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ - size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ - size *= sizeof(unsigned int); /* bytes per line */ - - return size; -} - -/* - * Do a dcache operation by modified virtual address. This is useful for - * maintaining coherency in drivers which do DMA transfers and only need to - * perform cache maintenance on a particular memory range rather than the - * entire cache. - */ -static void dcache_op_mva(unsigned long addr, - unsigned long len, enum dcache_op op) -{ - unsigned long line, linesize; - - linesize = line_bytes(); - line = addr & ~(linesize - 1); - - dsb(); - while (line < addr + len) { - switch(op) { - case OP_DCCIMVAC: - dccimvac(line); - break; - default: - break; - } - line += linesize; - } - isb(); -} - -void dcache_clean_by_mva(unsigned long addr, unsigned long len) -{ - dcache_op_mva(addr, len, OP_DCCMVAC); -} - -void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) -{ - dcache_op_mva(addr, len, OP_DCCIMVAC); -} - -void dcache_mmu_disable(void) -{ - uint32_t sctlr; - - dcache_clean_invalidate_all(); - sctlr = read_sctlr(); - sctlr &= ~(SCTLR_C | SCTLR_M); - write_sctlr(sctlr); -} - - -void dcache_mmu_enable(void) -{ - uint32_t sctlr; - - sctlr = read_sctlr(); - dcache_clean_invalidate_all(); - sctlr |= SCTLR_C | SCTLR_M; - write_sctlr(sctlr); -} - -void armv7_invalidate_caches(void) -{ - uint32_t clidr; - int level; - - /* Invalidate branch predictor */ - bpiall(); - - /* Iterate thru each cache identified in CLIDR and invalidate */ - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x0: - /* no cache */ - break; - case 0x1: - /* icache only */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - break; - case 0x2: - case 0x4: - /* dcache only or unified cache */ - csselr = level << 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - case 0x3: - /* separate icache and dcache */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - - csselr = level << 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - default: - /* reserved */ - break; - } - } - - /* Invalidate TLB */ - tlb_invalidate_all(); -} diff --git a/src/arch/armv7/lib/div0.c b/src/arch/armv7/lib/div0.c deleted file mode 100644 index ab06ad3..0000000 --- a/src/arch/armv7/lib/div0.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <console/console.h> - -void __div0(void); // called from asm so no need for a prototype in a header - -/* Replacement (=dummy) for GNU/Linux division-by zero handler */ -/* recursion is ok here because we have no formats ... */ -void __div0 (void) -{ - printk(BIOS_EMERG, "DIVIDE BY ZERO! continuing ... \n"); -} diff --git a/src/arch/armv7/lib/eabi_compat.c b/src/arch/armv7/lib/eabi_compat.c deleted file mode 100644 index c063c85..0000000 --- a/src/arch/armv7/lib/eabi_compat.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Utility functions needed for (some) EABI conformant tool chains. - * - * (C) Copyright 2009 Wolfgang Denk <wd(a)denx.de> - * - * This program is Free Software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - */ - -#include <console/console.h> - -/* FIXME(dhendrix): prototypes added for assembler */ -int raise (int signum); -int raise (int signum) -{ - printk(BIOS_CRIT, "raise: Signal # %d caught\n", signum); - return 0; -} - -/* Dummy function to avoid linker complaints */ -void __aeabi_unwind_cpp_pr0(void); -void __aeabi_unwind_cpp_pr0(void) -{ -}; - -void __aeabi_unwind_cpp_pr1(void); -void __aeabi_unwind_cpp_pr1(void) -{ -}; diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c deleted file mode 100644 index 68e81c6..0000000 --- a/src/arch/armv7/lib/early_console.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } -#endif -#if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); -#endif -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); -#endif -#if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_flush(CONFIG_TTYS0_BASE); -#endif -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/arch/armv7/lib/id.inc b/src/arch/armv7/lib/id.inc deleted file mode 100644 index ffe547d..0000000 --- a/src/arch/armv7/lib/id.inc +++ /dev/null @@ -1,18 +0,0 @@ - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/armv7/lib/interrupts.c b/src/arch/armv7/lib/interrupts.c deleted file mode 100644 index 7508c69..0000000 --- a/src/arch/armv7/lib/interrupts.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu(a)sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <reset.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_USE_IRQ -int interrupt_init (void) -{ - /* - * setup up stacks if necessary - */ - IRQ_STACK_START = gd->irq_sp - 4; - IRQ_STACK_START_IN = gd->irq_sp + 8; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; - - return arch_interrupt_init(); -} - -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else -int interrupt_init (void) -{ - /* - * setup up stacks if necessary - */ - IRQ_STACK_START_IN = gd->irq_sp + 8; - - return 0; -} - -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - soft_reset(); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -#ifndef CONFIG_USE_IRQ -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} -#endif diff --git a/src/arch/armv7/lib/memcpy.S b/src/arch/armv7/lib/memcpy.S deleted file mode 100644 index f04113f..0000000 --- a/src/arch/armv7/lib/memcpy.S +++ /dev/null @@ -1,243 +0,0 @@ -/* - * linux/arch/arm/lib/memcpy.S - * - * Author: Nicolas Pitre - * Created: Sep 28, 2005 - * Copyright: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <assembler.h> - -#define W(instr) instr - -#define LDR1W_SHIFT 0 -#define STR1W_SHIFT 0 - - .macro ldr1w ptr reg abort - W(ldr) \reg, [\ptr], #4 - .endm - - .macro ldr4w ptr reg1 reg2 reg3 reg4 abort - ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} - .endm - - .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort - ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} - .endm - - .macro ldr1b ptr reg cond=al abort - ldr\cond\()b \reg, [\ptr], #1 - .endm - - .macro str1w ptr reg abort - W(str) \reg, [\ptr], #4 - .endm - - .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort - stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} - .endm - - .macro str1b ptr reg cond=al abort - str\cond\()b \reg, [\ptr], #1 - .endm - - .macro enter reg1 reg2 - stmdb sp!, {r0, \reg1, \reg2} - .endm - - .macro exit reg1 reg2 - ldmfd sp!, {r0, \reg1, \reg2} - .endm - - .text - -/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ - -.globl memcpy -memcpy: - - cmp r0, r1 - moveq pc, lr - - enter r4, lr - - subs r2, r2, #4 - blt 8f - ands ip, r0, #3 - PLD( pld [r1, #0] ) - bne 9f - ands ip, r1, #3 - bne 10f - -1: subs r2, r2, #(28) - stmfd sp!, {r5 - r8} - blt 5f - - CALGN( ands ip, r0, #31 ) - CALGN( rsb r3, ip, #32 ) - CALGN( sbcnes r4, r3, r2 ) @ C is always set here - CALGN( bcs 2f ) - CALGN( adr r4, 6f ) - CALGN( subs r2, r2, r3 ) @ C gets set - CALGN( add pc, r4, ip ) - - PLD( pld [r1, #0] ) -2: PLD( subs r2, r2, #96 ) - PLD( pld [r1, #28] ) - PLD( blt 4f ) - PLD( pld [r1, #60] ) - PLD( pld [r1, #92] ) - -3: PLD( pld [r1, #124] ) -4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f - subs r2, r2, #32 - str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f - bge 3b - PLD( cmn r2, #96 ) - PLD( bge 4b ) - -5: ands ip, r2, #28 - rsb ip, ip, #32 -#if LDR1W_SHIFT > 0 - lsl ip, ip, #LDR1W_SHIFT -#endif - addne pc, pc, ip @ C is always clear here - b 7f -6: - .rept (1 << LDR1W_SHIFT) - W(nop) - .endr - ldr1w r1, r3, abort=20f - ldr1w r1, r4, abort=20f - ldr1w r1, r5, abort=20f - ldr1w r1, r6, abort=20f - ldr1w r1, r7, abort=20f - ldr1w r1, r8, abort=20f - ldr1w r1, lr, abort=20f - -#if LDR1W_SHIFT < STR1W_SHIFT - lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT -#elif LDR1W_SHIFT > STR1W_SHIFT - lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT -#endif - add pc, pc, ip - nop - .rept (1 << STR1W_SHIFT) - W(nop) - .endr - str1w r0, r3, abort=20f - str1w r0, r4, abort=20f - str1w r0, r5, abort=20f - str1w r0, r6, abort=20f - str1w r0, r7, abort=20f - str1w r0, r8, abort=20f - str1w r0, lr, abort=20f - - CALGN( bcs 2b ) - -7: ldmfd sp!, {r5 - r8} - -8: movs r2, r2, lsl #31 - ldr1b r1, r3, ne, abort=21f - ldr1b r1, r4, cs, abort=21f - ldr1b r1, ip, cs, abort=21f - str1b r0, r3, ne, abort=21f - str1b r0, r4, cs, abort=21f - str1b r0, ip, cs, abort=21f - - exit r4, pc - -9: rsb ip, ip, #4 - cmp ip, #2 - ldr1b r1, r3, gt, abort=21f - ldr1b r1, r4, ge, abort=21f - ldr1b r1, lr, abort=21f - str1b r0, r3, gt, abort=21f - str1b r0, r4, ge, abort=21f - subs r2, r2, ip - str1b r0, lr, abort=21f - blt 8b - ands ip, r1, #3 - beq 1b - -10: bic r1, r1, #3 - cmp ip, #2 - ldr1w r1, lr, abort=21f - beq 17f - bgt 18f - - - .macro forward_copy_shift pull push - - subs r2, r2, #28 - blt 14f - - CALGN( ands ip, r0, #31 ) - CALGN( rsb ip, ip, #32 ) - CALGN( sbcnes r4, ip, r2 ) @ C is always set here - CALGN( subcc r2, r2, ip ) - CALGN( bcc 15f ) - -11: stmfd sp!, {r5 - r9} - - PLD( pld [r1, #0] ) - PLD( subs r2, r2, #96 ) - PLD( pld [r1, #28] ) - PLD( blt 13f ) - PLD( pld [r1, #60] ) - PLD( pld [r1, #92] ) - -12: PLD( pld [r1, #124] ) -13: ldr4w r1, r4, r5, r6, r7, abort=19f - mov r3, lr, pull #\pull - subs r2, r2, #32 - ldr4w r1, r8, r9, ip, lr, abort=19f - orr r3, r3, r4, push #\push - mov r4, r4, pull #\pull - orr r4, r4, r5, push #\push - mov r5, r5, pull #\pull - orr r5, r5, r6, push #\push - mov r6, r6, pull #\pull - orr r6, r6, r7, push #\push - mov r7, r7, pull #\pull - orr r7, r7, r8, push #\push - mov r8, r8, pull #\pull - orr r8, r8, r9, push #\push - mov r9, r9, pull #\pull - orr r9, r9, ip, push #\push - mov ip, ip, pull #\pull - orr ip, ip, lr, push #\push - str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f - bge 12b - PLD( cmn r2, #96 ) - PLD( bge 13b ) - - ldmfd sp!, {r5 - r9} - -14: ands ip, r2, #28 - beq 16f - -15: mov r3, lr, pull #\pull - ldr1w r1, lr, abort=21f - subs ip, ip, #4 - orr r3, r3, lr, push #\push - str1w r0, r3, abort=21f - bgt 15b - CALGN( cmp r2, #0 ) - CALGN( bge 11b ) - -16: sub r1, r1, #(\push / 8) - b 8b - - .endm - - - forward_copy_shift pull=8 push=24 - -17: forward_copy_shift pull=16 push=16 - -18: forward_copy_shift pull=24 push=8 diff --git a/src/arch/armv7/lib/memset.S b/src/arch/armv7/lib/memset.S deleted file mode 100644 index 3ea2721..0000000 --- a/src/arch/armv7/lib/memset.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * linux/arch/arm/lib/memset.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ASM optimised string functions - */ -#include <assembler.h> - - .text - .align 5 - .word 0 - -1: subs r2, r2, #4 @ 1 do we have enough - blt 5f @ 1 bytes to align with? - cmp r3, #2 @ 1 - strltb r1, [r0], #1 @ 1 - strleb r1, [r0], #1 @ 1 - strb r1, [r0], #1 @ 1 - add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) -/* - * The pointer is now aligned and the length is adjusted. Try doing the - * memset again. - */ - -.globl memset -memset: - ands r3, r0, #3 @ 1 unaligned? - bne 1b @ 1 -/* - * we know that the pointer in r0 is aligned to a word boundary. - */ - orr r1, r1, r1, lsl #8 - orr r1, r1, r1, lsl #16 - mov r3, r1 - cmp r2, #16 - blt 4f - -#if ! CALGN(1)+0 - -/* - * We need an extra register for this loop - save the return address and - * use the LR - */ - str lr, [sp, #-4]! - mov ip, r1 - mov lr, r1 - -2: subs r2, r2, #64 - stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time. - stmgeia r0!, {r1, r3, ip, lr} - stmgeia r0!, {r1, r3, ip, lr} - stmgeia r0!, {r1, r3, ip, lr} - bgt 2b - ldmeqfd sp!, {pc} @ Now <64 bytes to go. -/* - * No need to correct the count; we're only testing bits from now on - */ - tst r2, #32 - stmneia r0!, {r1, r3, ip, lr} - stmneia r0!, {r1, r3, ip, lr} - tst r2, #16 - stmneia r0!, {r1, r3, ip, lr} - ldr lr, [sp], #4 - -#else - -/* - * This version aligns the destination pointer in order to write - * whole cache lines at once. - */ - - stmfd sp!, {r4-r7, lr} - mov r4, r1 - mov r5, r1 - mov r6, r1 - mov r7, r1 - mov ip, r1 - mov lr, r1 - - cmp r2, #96 - tstgt r0, #31 - ble 3f - - and ip, r0, #31 - rsb ip, ip, #32 - sub r2, r2, ip - movs ip, ip, lsl #(32 - 4) - stmcsia r0!, {r4, r5, r6, r7} - stmmiia r0!, {r4, r5} - tst ip, #(1 << 30) - mov ip, r1 - strne r1, [r0], #4 - -3: subs r2, r2, #64 - stmgeia r0!, {r1, r3-r7, ip, lr} - stmgeia r0!, {r1, r3-r7, ip, lr} - bgt 3b - ldmeqfd sp!, {r4-r7, pc} - - tst r2, #32 - stmneia r0!, {r1, r3-r7, ip, lr} - tst r2, #16 - stmneia r0!, {r4-r7} - ldmfd sp!, {r4-r7, lr} - -#endif - -4: tst r2, #8 - stmneia r0!, {r1, r3} - tst r2, #4 - strne r1, [r0], #4 -/* - * When we get here, we've got less than 4 bytes to zero. We - * may have an unaligned pointer as well. - */ -5: tst r2, #2 - strneb r1, [r0], #1 - strneb r1, [r0], #1 - tst r2, #1 - strneb r1, [r0], #1 - mov pc, lr diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c deleted file mode 100644 index 7d6d46a..0000000 --- a/src/arch/armv7/lib/mmu.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <stdlib.h> -#include <stdint.h> - -#include <cbmem.h> -#include <console/console.h> - -#include <arch/cache.h> -#include <arch/io.h> - -#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */ - -static uintptr_t ttb_addr; - -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) -{ - unsigned int i; - uint32_t *ttb_entry = (uint32_t *)ttb_addr; - printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", - start_mb*MiB, start_mb*MiB + size_mb*MiB - 1); - - for (i = start_mb; i < start_mb + size_mb; i++) - writel(0, &ttb_entry[i]); - - for (i = start_mb; i < start_mb + size_mb; i++) { - dccmvac((uintptr_t)&ttb_entry[i]); - tlbimvaa(i*MiB); - } -} - -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy) -{ - unsigned int i; - uint32_t attr; - uint32_t *ttb_entry = (uint32_t *)ttb_addr; - const char *str = NULL; - - /* - * Section entry bits: - * 31:20 - section base address - * 18 - 0 to indicate normal section (versus supersection) - * 17 - nG, 0 to indicate page is global - * 16 - S, 0 for non-shareable (?) - * 15 - APX, 0 for full access - * 14:12 - TEX, 0b000 for outer and inner write-back - * 11:10 - AP, 0b11 for full access - * 9 - P, ? (FIXME: not described or possibly obsolete?) - * 8: 5 - Domain - * 4 - XN, 1 to set execute-never (and also avoid prefetches) - * 3 - C, 1 for cacheable - * 2 - B, 1 for bufferable - * 1: 0 - 0b10 to indicate section entry - */ - - switch(policy) { - case DCACHE_OFF: - /* XN set to avoid prefetches to uncached/unbuffered regions */ - attr = (0x3 << 10) | (1 << 4) | 0x2; - str = "off"; - break; - case DCACHE_WRITEBACK: - attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; - str = "writeback"; - break; - case DCACHE_WRITETHROUGH: - attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; - str = "writethrough"; - break; - default: - printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy); - return; - } - - printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", - start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); - - /* Write out page table entries. */ - for (i = start_mb; i < start_mb + size_mb; i++) - writel((i << 20) | attr, &ttb_entry[i]); - - /* Flush the page table entries, and old translations from the TLB. */ - for (i = start_mb; i < start_mb + size_mb; i++) { - dccmvac((uintptr_t)&ttb_entry[i]); - tlbimvaa(i*MiB); - } -} - -void mmu_init(void) -{ - unsigned int ttb_size; - uint32_t ttbcr; - - /* - * For coreboot's purposes, we will create a simple L1 page table - * in RAM with 1MB section translation entries over the 4GB address - * space. - * (ref: section 10.2 and example 15-4 in Cortex-A series - * programmer's guide) - * - * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to - * 512 bytes. So allocate some extra space in cbmem and fix-up the - * pointer. - */ - ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t); - ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB); - ttb_addr = ALIGN(ttb_addr, 16*KiB); - printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr); - - /* - * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 - * table size is 16KB and has indices VA[31:20]. - * - * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, - */ - ttbcr = read_ttbcr(); - ttbcr &= ~(0x3); - write_ttbcr(ttbcr); - - /* - * Translation table base 0 address is in bits 31:14-N, where N is given - * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this - * register should be zero for coreboot. - */ - write_ttbr0(ttb_addr); - - /* disable domain-level checking of permissions */ - write_dacr(~0); -} diff --git a/src/arch/armv7/memcpy.S b/src/arch/armv7/memcpy.S new file mode 100644 index 0000000..f04113f --- /dev/null +++ b/src/arch/armv7/memcpy.S @@ -0,0 +1,243 @@ +/* + * linux/arch/arm/lib/memcpy.S + * + * Author: Nicolas Pitre + * Created: Sep 28, 2005 + * Copyright: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <assembler.h> + +#define W(instr) instr + +#define LDR1W_SHIFT 0 +#define STR1W_SHIFT 0 + + .macro ldr1w ptr reg abort + W(ldr) \reg, [\ptr], #4 + .endm + + .macro ldr4w ptr reg1 reg2 reg3 reg4 abort + ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} + .endm + + .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} + .endm + + .macro ldr1b ptr reg cond=al abort + ldr\cond\()b \reg, [\ptr], #1 + .endm + + .macro str1w ptr reg abort + W(str) \reg, [\ptr], #4 + .endm + + .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} + .endm + + .macro str1b ptr reg cond=al abort + str\cond\()b \reg, [\ptr], #1 + .endm + + .macro enter reg1 reg2 + stmdb sp!, {r0, \reg1, \reg2} + .endm + + .macro exit reg1 reg2 + ldmfd sp!, {r0, \reg1, \reg2} + .endm + + .text + +/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ + +.globl memcpy +memcpy: + + cmp r0, r1 + moveq pc, lr + + enter r4, lr + + subs r2, r2, #4 + blt 8f + ands ip, r0, #3 + PLD( pld [r1, #0] ) + bne 9f + ands ip, r1, #3 + bne 10f + +1: subs r2, r2, #(28) + stmfd sp!, {r5 - r8} + blt 5f + + CALGN( ands ip, r0, #31 ) + CALGN( rsb r3, ip, #32 ) + CALGN( sbcnes r4, r3, r2 ) @ C is always set here + CALGN( bcs 2f ) + CALGN( adr r4, 6f ) + CALGN( subs r2, r2, r3 ) @ C gets set + CALGN( add pc, r4, ip ) + + PLD( pld [r1, #0] ) +2: PLD( subs r2, r2, #96 ) + PLD( pld [r1, #28] ) + PLD( blt 4f ) + PLD( pld [r1, #60] ) + PLD( pld [r1, #92] ) + +3: PLD( pld [r1, #124] ) +4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f + subs r2, r2, #32 + str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f + bge 3b + PLD( cmn r2, #96 ) + PLD( bge 4b ) + +5: ands ip, r2, #28 + rsb ip, ip, #32 +#if LDR1W_SHIFT > 0 + lsl ip, ip, #LDR1W_SHIFT +#endif + addne pc, pc, ip @ C is always clear here + b 7f +6: + .rept (1 << LDR1W_SHIFT) + W(nop) + .endr + ldr1w r1, r3, abort=20f + ldr1w r1, r4, abort=20f + ldr1w r1, r5, abort=20f + ldr1w r1, r6, abort=20f + ldr1w r1, r7, abort=20f + ldr1w r1, r8, abort=20f + ldr1w r1, lr, abort=20f + +#if LDR1W_SHIFT < STR1W_SHIFT + lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT +#elif LDR1W_SHIFT > STR1W_SHIFT + lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT +#endif + add pc, pc, ip + nop + .rept (1 << STR1W_SHIFT) + W(nop) + .endr + str1w r0, r3, abort=20f + str1w r0, r4, abort=20f + str1w r0, r5, abort=20f + str1w r0, r6, abort=20f + str1w r0, r7, abort=20f + str1w r0, r8, abort=20f + str1w r0, lr, abort=20f + + CALGN( bcs 2b ) + +7: ldmfd sp!, {r5 - r8} + +8: movs r2, r2, lsl #31 + ldr1b r1, r3, ne, abort=21f + ldr1b r1, r4, cs, abort=21f + ldr1b r1, ip, cs, abort=21f + str1b r0, r3, ne, abort=21f + str1b r0, r4, cs, abort=21f + str1b r0, ip, cs, abort=21f + + exit r4, pc + +9: rsb ip, ip, #4 + cmp ip, #2 + ldr1b r1, r3, gt, abort=21f + ldr1b r1, r4, ge, abort=21f + ldr1b r1, lr, abort=21f + str1b r0, r3, gt, abort=21f + str1b r0, r4, ge, abort=21f + subs r2, r2, ip + str1b r0, lr, abort=21f + blt 8b + ands ip, r1, #3 + beq 1b + +10: bic r1, r1, #3 + cmp ip, #2 + ldr1w r1, lr, abort=21f + beq 17f + bgt 18f + + + .macro forward_copy_shift pull push + + subs r2, r2, #28 + blt 14f + + CALGN( ands ip, r0, #31 ) + CALGN( rsb ip, ip, #32 ) + CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( subcc r2, r2, ip ) + CALGN( bcc 15f ) + +11: stmfd sp!, {r5 - r9} + + PLD( pld [r1, #0] ) + PLD( subs r2, r2, #96 ) + PLD( pld [r1, #28] ) + PLD( blt 13f ) + PLD( pld [r1, #60] ) + PLD( pld [r1, #92] ) + +12: PLD( pld [r1, #124] ) +13: ldr4w r1, r4, r5, r6, r7, abort=19f + mov r3, lr, pull #\pull + subs r2, r2, #32 + ldr4w r1, r8, r9, ip, lr, abort=19f + orr r3, r3, r4, push #\push + mov r4, r4, pull #\pull + orr r4, r4, r5, push #\push + mov r5, r5, pull #\pull + orr r5, r5, r6, push #\push + mov r6, r6, pull #\pull + orr r6, r6, r7, push #\push + mov r7, r7, pull #\pull + orr r7, r7, r8, push #\push + mov r8, r8, pull #\pull + orr r8, r8, r9, push #\push + mov r9, r9, pull #\pull + orr r9, r9, ip, push #\push + mov ip, ip, pull #\pull + orr ip, ip, lr, push #\push + str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f + bge 12b + PLD( cmn r2, #96 ) + PLD( bge 13b ) + + ldmfd sp!, {r5 - r9} + +14: ands ip, r2, #28 + beq 16f + +15: mov r3, lr, pull #\pull + ldr1w r1, lr, abort=21f + subs ip, ip, #4 + orr r3, r3, lr, push #\push + str1w r0, r3, abort=21f + bgt 15b + CALGN( cmp r2, #0 ) + CALGN( bge 11b ) + +16: sub r1, r1, #(\push / 8) + b 8b + + .endm + + + forward_copy_shift pull=8 push=24 + +17: forward_copy_shift pull=16 push=16 + +18: forward_copy_shift pull=24 push=8 diff --git a/src/arch/armv7/memset.S b/src/arch/armv7/memset.S new file mode 100644 index 0000000..3ea2721 --- /dev/null +++ b/src/arch/armv7/memset.S @@ -0,0 +1,126 @@ +/* + * linux/arch/arm/lib/memset.S + * + * Copyright (C) 1995-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASM optimised string functions + */ +#include <assembler.h> + + .text + .align 5 + .word 0 + +1: subs r2, r2, #4 @ 1 do we have enough + blt 5f @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r1, [r0], #1 @ 1 + strleb r1, [r0], #1 @ 1 + strb r1, [r0], #1 @ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) +/* + * The pointer is now aligned and the length is adjusted. Try doing the + * memset again. + */ + +.globl memset +memset: + ands r3, r0, #3 @ 1 unaligned? + bne 1b @ 1 +/* + * we know that the pointer in r0 is aligned to a word boundary. + */ + orr r1, r1, r1, lsl #8 + orr r1, r1, r1, lsl #16 + mov r3, r1 + cmp r2, #16 + blt 4f + +#if ! CALGN(1)+0 + +/* + * We need an extra register for this loop - save the return address and + * use the LR + */ + str lr, [sp, #-4]! + mov ip, r1 + mov lr, r1 + +2: subs r2, r2, #64 + stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time. + stmgeia r0!, {r1, r3, ip, lr} + stmgeia r0!, {r1, r3, ip, lr} + stmgeia r0!, {r1, r3, ip, lr} + bgt 2b + ldmeqfd sp!, {pc} @ Now <64 bytes to go. +/* + * No need to correct the count; we're only testing bits from now on + */ + tst r2, #32 + stmneia r0!, {r1, r3, ip, lr} + stmneia r0!, {r1, r3, ip, lr} + tst r2, #16 + stmneia r0!, {r1, r3, ip, lr} + ldr lr, [sp], #4 + +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + mov ip, r1 + mov lr, r1 + + cmp r2, #96 + tstgt r0, #31 + ble 3f + + and ip, r0, #31 + rsb ip, ip, #32 + sub r2, r2, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + tst ip, #(1 << 30) + mov ip, r1 + strne r1, [r0], #4 + +3: subs r2, r2, #64 + stmgeia r0!, {r1, r3-r7, ip, lr} + stmgeia r0!, {r1, r3-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r2, #32 + stmneia r0!, {r1, r3-r7, ip, lr} + tst r2, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + +4: tst r2, #8 + stmneia r0!, {r1, r3} + tst r2, #4 + strne r1, [r0], #4 +/* + * When we get here, we've got less than 4 bytes to zero. We + * may have an unaligned pointer as well. + */ +5: tst r2, #2 + strneb r1, [r0], #1 + strneb r1, [r0], #1 + tst r2, #1 + strneb r1, [r0], #1 + mov pc, lr diff --git a/src/arch/armv7/mmu.c b/src/arch/armv7/mmu.c new file mode 100644 index 0000000..7d6d46a --- /dev/null +++ b/src/arch/armv7/mmu.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stdlib.h> +#include <stdint.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/cache.h> +#include <arch/io.h> + +#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */ + +static uintptr_t ttb_addr; + +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) +{ + unsigned int i; + uint32_t *ttb_entry = (uint32_t *)ttb_addr; + printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", + start_mb*MiB, start_mb*MiB + size_mb*MiB - 1); + + for (i = start_mb; i < start_mb + size_mb; i++) + writel(0, &ttb_entry[i]); + + for (i = start_mb; i < start_mb + size_mb; i++) { + dccmvac((uintptr_t)&ttb_entry[i]); + tlbimvaa(i*MiB); + } +} + +void mmu_config_range(unsigned long start_mb, unsigned long size_mb, + enum dcache_policy policy) +{ + unsigned int i; + uint32_t attr; + uint32_t *ttb_entry = (uint32_t *)ttb_addr; + const char *str = NULL; + + /* + * Section entry bits: + * 31:20 - section base address + * 18 - 0 to indicate normal section (versus supersection) + * 17 - nG, 0 to indicate page is global + * 16 - S, 0 for non-shareable (?) + * 15 - APX, 0 for full access + * 14:12 - TEX, 0b000 for outer and inner write-back + * 11:10 - AP, 0b11 for full access + * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 8: 5 - Domain + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable + * 1: 0 - 0b10 to indicate section entry + */ + + switch(policy) { + case DCACHE_OFF: + /* XN set to avoid prefetches to uncached/unbuffered regions */ + attr = (0x3 << 10) | (1 << 4) | 0x2; + str = "off"; + break; + case DCACHE_WRITEBACK: + attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + str = "writeback"; + break; + case DCACHE_WRITETHROUGH: + attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + str = "writethrough"; + break; + default: + printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy); + return; + } + + printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", + start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); + + /* Write out page table entries. */ + for (i = start_mb; i < start_mb + size_mb; i++) + writel((i << 20) | attr, &ttb_entry[i]); + + /* Flush the page table entries, and old translations from the TLB. */ + for (i = start_mb; i < start_mb + size_mb; i++) { + dccmvac((uintptr_t)&ttb_entry[i]); + tlbimvaa(i*MiB); + } +} + +void mmu_init(void) +{ + unsigned int ttb_size; + uint32_t ttbcr; + + /* + * For coreboot's purposes, we will create a simple L1 page table + * in RAM with 1MB section translation entries over the 4GB address + * space. + * (ref: section 10.2 and example 15-4 in Cortex-A series + * programmer's guide) + * + * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to + * 512 bytes. So allocate some extra space in cbmem and fix-up the + * pointer. + */ + ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB); + ttb_addr = ALIGN(ttb_addr, 16*KiB); + printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr); + + /* + * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 + * table size is 16KB and has indices VA[31:20]. + * + * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, + */ + ttbcr = read_ttbcr(); + ttbcr &= ~(0x3); + write_ttbcr(ttbcr); + + /* + * Translation table base 0 address is in bits 31:14-N, where N is given + * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this + * register should be zero for coreboot. + */ + write_ttbr0(ttb_addr); + + /* disable domain-level checking of permissions */ + write_dacr(~0); +} diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c new file mode 100644 index 0000000..0fc7399 --- /dev/null +++ b/src/arch/armv7/tables.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2005 Steve Magnani + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <boot/coreboot_tables.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> + +#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) + +/* + * TODO: "High" tables are a convention used on x86. Maybe we can + * clean up that naming at some point. + */ +uint64_t high_tables_base = 0; +uint64_t high_tables_size; + +void cbmem_arch_init(void) +{ +} + +struct lb_memory *write_tables(void) +{ + unsigned long table_pointer, new_table_pointer; + + if (!high_tables_base) { + printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); + } + + printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); + + post_code(0x9d); + + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (!table_pointer) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return NULL; + } + + new_table_pointer = write_coreboot_table(0UL, 0UL, + table_pointer, table_pointer); + + if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { + printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", + new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); + } + + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + + post_code(0x9e); + + /* Print CBMEM sections */ + cbmem_list(); + + return get_lb_mem(); +}

1 0

New patch to review for coreboot: 2519eda exynos5420: Replace the 5250 clock logic with 5420.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3658 -gerrit commit 2519eda13434d42fca4b564bd33e6370dfe77a30 Author: Gabe Black <gabeblack(a)google.com> Date: Fri May 17 11:29:22 2013 -0700 exynos5420: Replace the 5250 clock logic with 5420. The new code is stolen from U-Boot with little or no understanding of how it works. Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 1213 ++++++++++++++++++++++--------- src/cpu/samsung/exynos5420/clock.c | 198 ++--- src/cpu/samsung/exynos5420/clock_init.c | 491 ++++--------- src/cpu/samsung/exynos5420/setup.h | 393 +++++----- src/mainboard/google/pit/romstage.c | 5 +- 5 files changed, 1211 insertions(+), 1089 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index 631b637..b98a673 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -31,11 +31,13 @@ enum periph_id; #define HPLL 3 #define VPLL 4 #define BPLL 5 +#define RPLL 6 +#define SPLL 7 enum pll_src_bit { - SRC_MPLL = 6, - SRC_EPLL, - SRC_VPLL, + EXYNOS_SRC_MPLL = 6, + EXYNOS_SRC_EPLL, + EXYNOS_SRC_VPLL, }; /* * @@ -106,360 +108,854 @@ void clock_select_i2s_clk_source(void); int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); struct exynos5_clock { - unsigned int apll_lock; /* base + 0 */ - unsigned char res1[0xfc]; - unsigned int apll_con0; - unsigned int apll_con1; - unsigned char res2[0xf8]; - unsigned int src_cpu; - unsigned char res3[0x1fc]; - unsigned int mux_stat_cpu; - unsigned char res4[0xfc]; - unsigned int div_cpu0; - unsigned int div_cpu1; - unsigned char res5[0xf8]; - unsigned int div_stat_cpu0; - unsigned int div_stat_cpu1; - unsigned char res6[0x1f8]; - unsigned int gate_sclk_cpu; - unsigned char res7[0x1fc]; - unsigned int clkout_cmu_cpu; - unsigned int clkout_cmu_cpu_div_stat; - unsigned char res8[0x5f8]; - - unsigned int armclk_stopctrl; /* base + 0x1000 */ - unsigned int atclk_stopctrl; - unsigned char res9[0x8]; - unsigned int parityfail_status; - unsigned int parityfail_clear; - unsigned char res10[0x8]; - unsigned int pwr_ctrl; - unsigned int pwr_ctr2; - unsigned char res11[0xd8]; - unsigned int apll_con0_l8; - unsigned int apll_con0_l7; - unsigned int apll_con0_l6; - unsigned int apll_con0_l5; - unsigned int apll_con0_l4; - unsigned int apll_con0_l3; - unsigned int apll_con0_l2; - unsigned int apll_con0_l1; - unsigned int iem_control; - unsigned char res12[0xdc]; - unsigned int apll_con1_l8; - unsigned int apll_con1_l7; - unsigned int apll_con1_l6; - unsigned int apll_con1_l5; - unsigned int apll_con1_l4; - unsigned int apll_con1_l3; - unsigned int apll_con1_l2; - unsigned int apll_con1_l1; - unsigned char res13[0xe0]; - unsigned int div_iem_l8; - unsigned int div_iem_l7; - unsigned int div_iem_l6; - unsigned int div_iem_l5; - unsigned int div_iem_l4; - unsigned int div_iem_l3; - unsigned int div_iem_l2; - unsigned int div_iem_l1; - unsigned char res14[0x2ce0]; - - unsigned int mpll_lock; /* base + 0x4000 */ - unsigned char res15[0xfc]; - unsigned int mpll_con0; - unsigned int mpll_con1; - unsigned char res16[0xf8]; - unsigned int src_core0; - unsigned int src_core1; - unsigned char res17[0xf8]; - unsigned int src_mask_core; - unsigned char res18[0x100]; - unsigned int mux_stat_core1; - unsigned char res19[0xf8]; - unsigned int div_core0; - unsigned int div_core1; - unsigned int div_sysrgt; - unsigned char res20[0xf4]; - unsigned int div_stat_core0; - unsigned int div_stat_core1; - unsigned int div_stat_sysrgt; - unsigned char res21[0x2f4]; - unsigned int gate_ip_core; - unsigned int gate_ip_sysrgt; - unsigned char res22[0xf8]; - unsigned int clkout_cmu_core; - unsigned int clkout_cmu_core_div_stat; - unsigned char res23[0x5f8]; - - unsigned int dcgidx_map0; /* base + 0x5000 */ - unsigned int dcgidx_map1; - unsigned int dcgidx_map2; - unsigned char res24[0x14]; - unsigned int dcgperf_map0; - unsigned int dcgperf_map1; - unsigned char res25[0x18]; - unsigned int dvcidx_map; - unsigned char res26[0x1c]; - unsigned int freq_cpu; - unsigned int freq_dpm; - unsigned char res27[0x18]; - unsigned int dvsemclk_en; - unsigned int maxperf; - unsigned char res28[0x3478]; - - unsigned int div_acp; /* base + 0x8500 */ - unsigned char res29[0xfc]; - unsigned int div_stat_acp; - unsigned char res30[0x1fc]; - unsigned int gate_ip_acp; - unsigned char res31a[0xfc]; - unsigned int div_syslft; - unsigned char res31b[0xc]; - unsigned int div_stat_syslft; - unsigned char res31c[0xc]; - unsigned int gate_bus_syslft; - unsigned char res31d[0xdc]; - unsigned int clkout_cmu_acp; - unsigned int clkout_cmu_acp_div_stat; - unsigned char res32[0x38f8]; - - unsigned int div_isp0; /* base + 0xc300 */ - unsigned int div_isp1; - unsigned int div_isp2; - unsigned char res33[0xf4]; - - unsigned int div_stat_isp0; /* base + 0xc400 */ - unsigned int div_stat_isp1; - unsigned int div_stat_isp2; - unsigned char res34[0x3f4]; - - unsigned int gate_ip_isp0; /* base + 0xc800 */ - unsigned int gate_ip_isp1; - unsigned char res35[0xf8]; - unsigned int gate_sclk_isp; - unsigned char res36[0xc]; - unsigned int mcuisp_pwr_ctrl; - unsigned char res37[0xec]; - unsigned int clkout_cmu_isp; - unsigned int clkout_cmu_isp_div_stat; - unsigned char res38[0x3618]; - - unsigned int cpll_lock; /* base + 0x10020 */ - unsigned char res39[0xc]; - unsigned int epll_lock; - unsigned char res40[0xc]; - unsigned int vpll_lock; - unsigned char res41a[0xc]; - unsigned int gpll_lock; - unsigned char res41b[0xcc]; - unsigned int cpll_con0; - unsigned int cpll_con1; - unsigned char res42[0x8]; - unsigned int epll_con0; - unsigned int epll_con1; - unsigned int epll_con2; - unsigned char res43[0x4]; - unsigned int vpll_con0; - unsigned int vpll_con1; - unsigned int vpll_con2; - unsigned char res44a[0x4]; - unsigned int gpll_con0; - unsigned int gpll_con1; - unsigned char res44b[0xb8]; - unsigned int src_top0; - unsigned int src_top1; - unsigned int src_top2; - unsigned int src_top3; - unsigned int src_gscl; - unsigned int src_disp0_0; - unsigned int src_disp0_1; - unsigned int src_disp1_0; - unsigned int src_disp1_1; - unsigned char res46[0xc]; - unsigned int src_mau; - unsigned int src_fsys; - unsigned char res47[0x8]; - unsigned int src_peric0; - unsigned int src_peric1; - unsigned char res48[0x18]; - unsigned int sclk_src_isp; - unsigned char res49[0x9c]; - unsigned int src_mask_top; - unsigned char res50[0xc]; - unsigned int src_mask_gscl; - unsigned int src_mask_disp0_0; - unsigned int src_mask_disp0_1; - unsigned int src_mask_disp1_0; - unsigned int src_mask_disp1_1; - unsigned int src_mask_maudio; - unsigned char res52[0x8]; - unsigned int src_mask_fsys; - unsigned char res53[0xc]; - unsigned int src_mask_peric0; - unsigned int src_mask_peric1; - unsigned char res54[0x18]; - unsigned int src_mask_isp; - unsigned char res55[0x9c]; - unsigned int mux_stat_top0; - unsigned int mux_stat_top1; - unsigned int mux_stat_top2; - unsigned int mux_stat_top3; - unsigned char res56[0xf0]; - unsigned int div_top0; - unsigned int div_top1; - unsigned char res57[0x8]; - unsigned int div_gscl; - unsigned int div_disp0_0; - unsigned int div_disp0_1; - unsigned int div_disp1_0; - unsigned int div_disp1_1; - unsigned char res59[0x8]; - unsigned int div_gen; - unsigned char res60[0x4]; - unsigned int div_mau; - unsigned int div_fsys0; - unsigned int div_fsys1; - unsigned int div_fsys2; - unsigned int div_fsys3; - unsigned int div_peric0; - unsigned int div_peric1; - unsigned int div_peric2; - unsigned int div_peric3; - unsigned int div_peric4; - unsigned int div_peric5; - unsigned char res61[0x10]; - unsigned int sclk_div_isp; - unsigned char res62[0xc]; - unsigned int div2_ratio0; - unsigned int div2_ratio1; - unsigned char res63[0x8]; - unsigned int div4_ratio; - unsigned char res64[0x6c]; - unsigned int div_stat_top0; - unsigned int div_stat_top1; - unsigned char res65[0x8]; - unsigned int div_stat_gscl; - unsigned int div_stat_disp0_0; - unsigned int div_stat_disp0_1; - unsigned int div_stat_disp1_0; - unsigned int div_stat_disp1_1; - unsigned char res67[0x8]; - unsigned int div_stat_gen; - unsigned char res68[0x4]; - unsigned int div_stat_maudio; - unsigned int div_stat_fsys0; - unsigned int div_stat_fsys1; - unsigned int div_stat_fsys2; - unsigned int div_stat_fsys3; - unsigned int div_stat_peric0; - unsigned int div_stat_peric1; - unsigned int div_stat_peric2; - unsigned int div_stat_peric3; - unsigned int div_stat_peric4; - unsigned int div_stat_peric5; - unsigned char res69[0x10]; - unsigned int sclk_div_stat_isp; - unsigned char res70[0xc]; - unsigned int div2_stat0; - unsigned int div2_stat1; - unsigned char res71[0x8]; - unsigned int div4_stat; - unsigned char res72[0x180]; - unsigned int gate_top_sclk_disp0; - unsigned int gate_top_sclk_disp1; - unsigned int gate_top_sclk_gen; - unsigned char res74[0xc]; - unsigned int gate_top_sclk_mau; - unsigned int gate_top_sclk_fsys; - unsigned char res75[0xc]; - unsigned int gate_top_sclk_peric; - unsigned char res76[0x1c]; - unsigned int gate_top_sclk_isp; - unsigned char res77[0xac]; - unsigned int gate_ip_gscl; - unsigned int gate_ip_disp0; - unsigned int gate_ip_disp1; - unsigned int gate_ip_mfc; - unsigned int gate_ip_g3d; - unsigned int gate_ip_gen; - unsigned char res79[0xc]; - unsigned int gate_ip_fsys; - unsigned char res80[0x4]; - unsigned int gate_ip_gps; - unsigned int gate_ip_peric; - unsigned char res81[0xc]; - unsigned int gate_ip_peris; - unsigned char res82[0x1c]; - unsigned int gate_block; - unsigned char res83[0x7c]; - unsigned int clkout_cmu_top; - unsigned int clkout_cmu_top_div_stat; - unsigned char res84[0x37f8]; - - unsigned int src_lex; /* base + 0x14200 */ - unsigned char res85[0x1fc]; - unsigned int mux_stat_lex; - unsigned char res85b[0xfc]; - unsigned int div_lex; - unsigned char res86[0xfc]; - unsigned int div_stat_lex; - unsigned char res87[0x1fc]; - unsigned int gate_ip_lex; - unsigned char res88[0x1fc]; - unsigned int clkout_cmu_lex; - unsigned int clkout_cmu_lex_div_stat; - unsigned char res89[0x3af8]; - - unsigned int div_r0x; /* base + 0x18500 */ - unsigned char res90[0xfc]; - unsigned int div_stat_r0x; - unsigned char res91[0x1fc]; - unsigned int gate_ip_r0x; - unsigned char res92[0x1fc]; - unsigned int clkout_cmu_r0x; - unsigned int clkout_cmu_r0x_div_stat; - unsigned char res94[0x3af8]; - - unsigned int div_r1x; /* base + 0x1c500 */ - unsigned char res95[0xfc]; - unsigned int div_stat_r1x; - unsigned char res96[0x1fc]; - unsigned int gate_ip_r1x; - unsigned char res97[0x1fc]; - unsigned int clkout_cmu_r1x; - unsigned int clkout_cmu_r1x_div_stat; - unsigned char res98[0x3608]; - - unsigned int bpll_lock; /* base + 0x2000c */ - unsigned char res99[0xfc]; - unsigned int bpll_con0; - unsigned int bpll_con1; - unsigned char res100[0xe8]; - unsigned int src_cdrex; - unsigned char res101[0x1fc]; - unsigned int mux_stat_cdrex; - unsigned char res102[0xfc]; - unsigned int div_cdrex; - unsigned int div_cdrex2; - unsigned char res103[0xf8]; - unsigned int div_stat_cdrex; - unsigned char res104[0x2fc]; - unsigned int gate_ip_cdrex; - unsigned char res105[0xc]; - unsigned int c2c_monitor; - unsigned int dmc_pwr_ctrl; - unsigned char res106[0x4]; - unsigned int drex2_pause; - unsigned char res107[0xe0]; - unsigned int clkout_cmu_cdrex; - unsigned int clkout_cmu_cdrex_div_stat; - unsigned char res108[0x8]; - unsigned int lpddr3phy_ctrl; - unsigned char res109a[0xc]; - unsigned int lpddr3phy_con3; - unsigned int pll_div2_sel; - unsigned char res109b[0xf5e4]; + uint32_t apll_lock; /* base + 0 */ + uint8_t res1[0xfc]; + uint32_t apll_con0; + uint32_t apll_con1; + uint8_t res2[0xf8]; + uint32_t src_cpu; + uint8_t res3[0x1fc]; + uint32_t mux_stat_cpu; + uint8_t res4[0xfc]; + uint32_t div_cpu0; + uint32_t div_cpu1; + uint8_t res5[0xf8]; + uint32_t div_stat_cpu0; + uint32_t div_stat_cpu1; + uint8_t res6[0x1f8]; + uint32_t gate_sclk_cpu; + uint8_t res7[0x1fc]; + uint32_t clkout_cmu_cpu; + uint32_t clkout_cmu_cpu_div_stat; + uint8_t res8[0x5f8]; + + uint32_t armclk_stopctrl; /* base + 0x1000 */ + uint32_t atclk_stopctrl; + uint8_t res9[0x8]; + uint32_t parityfail_status; + uint32_t parityfail_clear; + uint8_t res10[0x8]; + uint32_t pwr_ctrl; + uint32_t pwr_ctr2; + uint8_t res11[0xd8]; + uint32_t apll_con0_l8; + uint32_t apll_con0_l7; + uint32_t apll_con0_l6; + uint32_t apll_con0_l5; + uint32_t apll_con0_l4; + uint32_t apll_con0_l3; + uint32_t apll_con0_l2; + uint32_t apll_con0_l1; + uint32_t iem_control; + uint8_t res12[0xdc]; + uint32_t apll_con1_l8; + uint32_t apll_con1_l7; + uint32_t apll_con1_l6; + uint32_t apll_con1_l5; + uint32_t apll_con1_l4; + uint32_t apll_con1_l3; + uint32_t apll_con1_l2; + uint32_t apll_con1_l1; + uint8_t res13[0xe0]; + uint32_t div_iem_l8; + uint32_t div_iem_l7; + uint32_t div_iem_l6; + uint32_t div_iem_l5; + uint32_t div_iem_l4; + uint32_t div_iem_l3; + uint32_t div_iem_l2; + uint32_t div_iem_l1; + uint8_t res14[0x2ce0]; + + uint32_t mpll_lock; /* base + 0x4000 */ + uint8_t res15[0xfc]; + uint32_t mpll_con0; + uint32_t mpll_con1; + uint8_t res16[0xf8]; + uint32_t src_core0; + uint32_t src_core1; + uint8_t res17[0xf8]; + uint32_t src_mask_core; + uint8_t res18[0x100]; + uint32_t mux_stat_core1; + uint8_t res19[0xf8]; + uint32_t div_core0; + uint32_t div_core1; + uint32_t div_sysrgt; + uint8_t res20[0xf4]; + uint32_t div_stat_core0; + uint32_t div_stat_core1; + uint32_t div_stat_sysrgt; + uint8_t res21[0x2f4]; + uint32_t gate_ip_core; + uint32_t gate_ip_sysrgt; + uint8_t res22[0xf8]; + uint32_t clkout_cmu_core; + uint32_t clkout_cmu_core_div_stat; + uint8_t res23[0x5f8]; + + uint32_t dcgidx_map0; /* base + 0x5000 */ + uint32_t dcgidx_map1; + uint32_t dcgidx_map2; + uint8_t res24[0x14]; + uint32_t dcgperf_map0; + uint32_t dcgperf_map1; + uint8_t res25[0x18]; + uint32_t dvcidx_map; + uint8_t res26[0x1c]; + uint32_t freq_cpu; + uint32_t freq_dpm; + uint8_t res27[0x18]; + uint32_t dvsemclk_en; + uint32_t maxperf; + uint8_t res28[0x3478]; + + uint32_t div_acp; /* base + 0x8500 */ + uint8_t res29[0xfc]; + uint32_t div_stat_acp; + uint8_t res30[0x1fc]; + uint32_t gate_ip_acp; + uint8_t res31a[0xfc]; + uint32_t div_syslft; + uint8_t res31b[0xc]; + uint32_t div_stat_syslft; + uint8_t res31c[0xc]; + uint32_t gate_bus_syslft; + uint8_t res31d[0xdc]; + uint32_t clkout_cmu_acp; + uint32_t clkout_cmu_acp_div_stat; + uint8_t res32[0x38f8]; + + uint32_t div_isp0; /* base + 0xc300 */ + uint32_t div_isp1; + uint32_t div_isp2; + uint8_t res33[0xf4]; + + uint32_t div_stat_isp0; /* base + 0xc400 */ + uint32_t div_stat_isp1; + uint32_t div_stat_isp2; + uint8_t res34[0x3f4]; + + uint32_t gate_ip_isp0; /* base + 0xc800 */ + uint32_t gate_ip_isp1; + uint8_t res35[0xf8]; + uint32_t gate_sclk_isp; + uint8_t res36[0xc]; + uint32_t mcuisp_pwr_ctrl; + uint8_t res37[0xec]; + uint32_t clkout_cmu_isp; + uint32_t clkout_cmu_isp_div_stat; + uint8_t res38[0x3618]; + + uint32_t cpll_lock; /* base + 0x10020 */ + uint8_t res39[0xc]; + uint32_t epll_lock; + uint8_t res40[0xc]; + uint32_t vpll_lock; + uint8_t res41a[0xc]; + uint32_t gpll_lock; + uint8_t res41b[0xcc]; + uint32_t cpll_con0; + uint32_t cpll_con1; + uint8_t res42[0x8]; + uint32_t epll_con0; + uint32_t epll_con1; + uint32_t epll_con2; + uint8_t res43[0x4]; + uint32_t vpll_con0; + uint32_t vpll_con1; + uint32_t vpll_con2; + uint8_t res44a[0x4]; + uint32_t gpll_con0; + uint32_t gpll_con1; + uint8_t res44b[0xb8]; + uint32_t src_top0; + uint32_t src_top1; + uint32_t src_top2; + uint32_t src_top3; + uint32_t src_gscl; + uint32_t src_disp0_0; + uint32_t src_disp0_1; + uint32_t src_disp1_0; + uint32_t src_disp1_1; + uint8_t res46[0xc]; + uint32_t src_mau; + uint32_t src_fsys; + uint8_t res47[0x8]; + uint32_t src_peric0; + uint32_t src_peric1; + uint8_t res48[0x18]; + uint32_t sclk_src_isp; + uint8_t res49[0x9c]; + uint32_t src_mask_top; + uint8_t res50[0xc]; + uint32_t src_mask_gscl; + uint32_t src_mask_disp0_0; + uint32_t src_mask_disp0_1; + uint32_t src_mask_disp1_0; + uint32_t src_mask_disp1_1; + uint32_t src_mask_maudio; + uint8_t res52[0x8]; + uint32_t src_mask_fsys; + uint8_t res53[0xc]; + uint32_t src_mask_peric0; + uint32_t src_mask_peric1; + uint8_t res54[0x18]; + uint32_t src_mask_isp; + uint8_t res55[0x9c]; + uint32_t mux_stat_top0; + uint32_t mux_stat_top1; + uint32_t mux_stat_top2; + uint32_t mux_stat_top3; + uint8_t res56[0xf0]; + uint32_t div_top0; + uint32_t div_top1; + uint8_t res57[0x8]; + uint32_t div_gscl; + uint32_t div_disp0_0; + uint32_t div_disp0_1; + uint32_t div_disp1_0; + uint32_t div_disp1_1; + uint8_t res59[0x8]; + uint32_t div_gen; + uint8_t res60[0x4]; + uint32_t div_mau; + uint32_t div_fsys0; + uint32_t div_fsys1; + uint32_t div_fsys2; + uint32_t div_fsys3; + uint32_t div_peric0; + uint32_t div_peric1; + uint32_t div_peric2; + uint32_t div_peric3; + uint32_t div_peric4; + uint32_t div_peric5; + uint8_t res61[0x10]; + uint32_t sclk_div_isp; + uint8_t res62[0xc]; + uint32_t div2_ratio0; + uint32_t div2_ratio1; + uint8_t res63[0x8]; + uint32_t div4_ratio; + uint8_t res64[0x6c]; + uint32_t div_stat_top0; + uint32_t div_stat_top1; + uint8_t res65[0x8]; + uint32_t div_stat_gscl; + uint32_t div_stat_disp0_0; + uint32_t div_stat_disp0_1; + uint32_t div_stat_disp1_0; + uint32_t div_stat_disp1_1; + uint8_t res67[0x8]; + uint32_t div_stat_gen; + uint8_t res68[0x4]; + uint32_t div_stat_maudio; + uint32_t div_stat_fsys0; + uint32_t div_stat_fsys1; + uint32_t div_stat_fsys2; + uint32_t div_stat_fsys3; + uint32_t div_stat_peric0; + uint32_t div_stat_peric1; + uint32_t div_stat_peric2; + uint32_t div_stat_peric3; + uint32_t div_stat_peric4; + uint32_t div_stat_peric5; + uint8_t res69[0x10]; + uint32_t sclk_div_stat_isp; + uint8_t res70[0xc]; + uint32_t div2_stat0; + uint32_t div2_stat1; + uint8_t res71[0x8]; + uint32_t div4_stat; + uint8_t res72[0x180]; + uint32_t gate_top_sclk_disp0; + uint32_t gate_top_sclk_disp1; + uint32_t gate_top_sclk_gen; + uint8_t res74[0xc]; + uint32_t gate_top_sclk_mau; + uint32_t gate_top_sclk_fsys; + uint8_t res75[0xc]; + uint32_t gate_top_sclk_peric; + uint8_t res76[0x1c]; + uint32_t gate_top_sclk_isp; + uint8_t res77[0xac]; + uint32_t gate_ip_gscl; + uint32_t gate_ip_disp0; + uint32_t gate_ip_disp1; + uint32_t gate_ip_mfc; + uint32_t gate_ip_g3d; + uint32_t gate_ip_gen; + uint8_t res79[0xc]; + uint32_t gate_ip_fsys; + uint8_t res80[0x4]; + uint32_t gate_ip_gps; + uint32_t gate_ip_peric; + uint8_t res81[0xc]; + uint32_t gate_ip_peris; + uint8_t res82[0x1c]; + uint32_t gate_block; + uint8_t res83[0x7c]; + uint32_t clkout_cmu_top; + uint32_t clkout_cmu_top_div_stat; + uint8_t res84[0x37f8]; + + uint32_t src_lex; /* base + 0x14200 */ + uint8_t res85[0x1fc]; + uint32_t mux_stat_lex; + uint8_t res85b[0xfc]; + uint32_t div_lex; + uint8_t res86[0xfc]; + uint32_t div_stat_lex; + uint8_t res87[0x1fc]; + uint32_t gate_ip_lex; + uint8_t res88[0x1fc]; + uint32_t clkout_cmu_lex; + uint32_t clkout_cmu_lex_div_stat; + uint8_t res89[0x3af8]; + + uint32_t div_r0x; /* base + 0x18500 */ + uint8_t res90[0xfc]; + uint32_t div_stat_r0x; + uint8_t res91[0x1fc]; + uint32_t gate_ip_r0x; + uint8_t res92[0x1fc]; + uint32_t clkout_cmu_r0x; + uint32_t clkout_cmu_r0x_div_stat; + uint8_t res94[0x3af8]; + + uint32_t div_r1x; /* base + 0x1c500 */ + uint8_t res95[0xfc]; + uint32_t div_stat_r1x; + uint8_t res96[0x1fc]; + uint32_t gate_ip_r1x; + uint8_t res97[0x1fc]; + uint32_t clkout_cmu_r1x; + uint32_t clkout_cmu_r1x_div_stat; + uint8_t res98[0x3608]; + + uint32_t bpll_lock; /* base + 0x2000c */ + uint8_t res99[0xfc]; + uint32_t bpll_con0; + uint32_t bpll_con1; + uint8_t res100[0xe8]; + uint32_t src_cdrex; + uint8_t res101[0x1fc]; + uint32_t mux_stat_cdrex; + uint8_t res102[0xfc]; + uint32_t div_cdrex; + uint32_t div_cdrex2; + uint8_t res103[0xf8]; + uint32_t div_stat_cdrex; + uint8_t res104[0x2fc]; + uint32_t gate_ip_cdrex; + uint8_t res105[0xc]; + uint32_t c2c_monitor; + uint32_t dmc_pwr_ctrl; + uint8_t res106[0x4]; + uint32_t drex2_pause; + uint8_t res107[0xe0]; + uint32_t clkout_cmu_cdrex; + uint32_t clkout_cmu_cdrex_div_stat; + uint8_t res108[0x8]; + uint32_t lpddr3phy_ctrl; + uint8_t res109a[0xc]; + uint32_t lpddr3phy_con3; + uint32_t pll_div2_sel; + uint8_t res109b[0xf5e4]; +}; + +struct exynos5420_clock { + uint32_t apll_lock; /* 0x10010000 */ + uint8_t res1[0xfc]; + uint32_t apll_con0; + uint32_t apll_con1; + uint8_t res2[0xf8]; + uint32_t clk_src_cpu; + uint8_t res3[0x1fc]; + uint32_t clk_mux_stat_cpu; + uint8_t res4[0xfc]; + uint32_t clk_div_cpu0; /* 0x10010500 */ + uint32_t clk_div_cpu1; + uint8_t res5[0xf8]; + uint32_t clk_div_stat_cpu0; + uint32_t clk_div_stat_cpu1; + uint8_t res6[0xf8]; + uint32_t clk_gate_bus_cpu; + uint8_t res7[0xfc]; + uint32_t clk_gate_sclk_cpu; + uint8_t res8[0x1fc]; + uint32_t clkout_cmu_cpu; /* 0x10010a00 */ + uint32_t clkout_cmu_cpu_div_stat; + uint8_t res9[0x5f8]; + uint32_t armclk_stopctrl; + uint8_t res10[0x4]; + uint32_t arm_ema_ctrl; + uint32_t arm_ema_status; + uint8_t res11[0x10]; + uint32_t pwr_ctrl; + uint32_t pwr_ctrl2; + uint8_t res12[0xd8]; + uint32_t apll_con0_l8; /* 0x1001100 */ + uint32_t apll_con0_l7; + uint32_t apll_con0_l6; + uint32_t apll_con0_l5; + uint32_t apll_con0_l4; + uint32_t apll_con0_l3; + uint32_t apll_con0_l2; + uint32_t apll_con0_l1; + uint32_t iem_control; + uint8_t res13[0xdc]; + uint32_t apll_con1_l8; /* 0x10011200 */ + uint32_t apll_con1_l7; + uint32_t apll_con1_l6; + uint32_t apll_con1_l5; + uint32_t apll_con1_l4; + uint32_t apll_con1_l3; + uint32_t apll_con1_l2; + uint32_t apll_con1_l1; + uint8_t res14[0xe0]; + uint32_t clkdiv_iem_l8; + uint32_t clkdiv_iem_l7; /* 0x10011304 */ + uint32_t clkdiv_iem_l6; + uint32_t clkdiv_iem_l5; + uint32_t clkdiv_iem_l4; + uint32_t clkdiv_iem_l3; + uint32_t clkdiv_iem_l2; + uint32_t clkdiv_iem_l1; + uint8_t res15[0xe0]; + uint32_t l2_status; + uint8_t res16[0x0c]; + uint32_t cpu_status; /* 0x10011410 */ + uint8_t res17[0x0c]; + uint32_t ptm_status; + uint8_t res18[0xbdc]; + uint32_t cmu_cpu_spare0; + uint32_t cmu_cpu_spare1; + uint32_t cmu_cpu_spare2; + uint32_t cmu_cpu_spare3; + uint32_t cmu_cpu_spare4; + uint8_t res19[0x1fdc]; + uint32_t cmu_cpu_version; + uint8_t res20[0x20c]; + uint32_t clk_src_cperi0; /* 0x10014200 */ + uint32_t clk_src_cperi1; + uint8_t res21[0xf8]; + uint32_t clk_src_mask_cperi; + uint8_t res22[0x100]; + uint32_t clk_mux_stat_cperi1; + uint8_t res23[0xfc]; + uint32_t clk_div_cperi1; + uint8_t res24[0xfc]; + uint32_t clk_div_stat_cperi1; + uint8_t res25[0xf8]; + uint32_t clk_gate_bus_cperi0; /* 0x10014700 */ + uint32_t clk_gate_bus_cperi1; + uint8_t res26[0xf8]; + uint32_t clk_gate_sclk_cperi; + uint8_t res27[0xfc]; + uint32_t clk_gate_ip_cperi; + uint8_t res28[0xfc]; + uint32_t clkout_cmu_cperi; + uint32_t clkout_cmu_cperi_div_stat; + uint8_t res29[0x5f8]; + uint32_t dcgidx_map0; /* 0x10015000 */ + uint32_t dcgidx_map1; + uint32_t dcgidx_map2; + uint8_t res30[0x14]; + uint32_t dcgperf_map0; + uint32_t dcgperf_map1; + uint8_t res31[0x18]; + uint32_t dvcidx_map; + uint8_t res32[0x1c]; + uint32_t freq_cpu; + uint32_t freq_dpm; + uint8_t res33[0x18]; + uint32_t dvsemclk_en; /* 0x10015080 */ + uint32_t maxperf; + uint8_t res34[0x2e78]; + uint32_t cmu_cperi_spare0; + uint32_t cmu_cperi_spare1; + uint32_t cmu_cperi_spare2; + uint32_t cmu_cperi_spare3; + uint32_t cmu_cperi_spare4; + uint32_t cmu_cperi_spare5; + uint32_t cmu_cperi_spare6; + uint32_t cmu_cperi_spare7; + uint32_t cmu_cperi_spare8; + uint8_t res35[0xcc]; + uint32_t cmu_cperi_version; /* 0x10017ff0 */ + uint8_t res36[0x50c]; + uint32_t clk_div_g2d; + uint8_t res37[0xfc]; + uint32_t clk_div_stat_g2d; + uint8_t res38[0xfc]; + uint32_t clk_gate_bus_g2d; + uint8_t res39[0xfc]; + uint32_t clk_gate_ip_g2d; + uint8_t res40[0x1fc]; + uint32_t clkout_cmu_g2d; + uint32_t clkout_cmu_g2d_div_stat;/* 0x10018a04 */ + uint8_t res41[0xf8]; + uint32_t cmu_g2d_spare0; + uint32_t cmu_g2d_spare1; + uint32_t cmu_g2d_spare2; + uint32_t cmu_g2d_spare3; + uint32_t cmu_g2d_spare4; + uint8_t res42[0x34dc]; + uint32_t cmu_g2d_version; + uint8_t res43[0x30c]; + uint32_t clk_div_cmu_isp0; + uint32_t clk_div_cmu_isp1; + uint32_t clk_div_isp2; /* 0x1001c308 */ + uint8_t res44[0xf4]; + uint32_t clk_div_stat_cmu_isp0; + uint32_t clk_div_stat_cmu_isp1; + uint32_t clk_div_stat_isp2; + uint8_t res45[0x2f4]; + uint32_t clk_gate_bus_isp0; + uint32_t clk_gate_bus_isp1; + uint32_t clk_gate_bus_isp2; + uint32_t clk_gate_bus_isp3; + uint8_t res46[0xf0]; + uint32_t clk_gate_ip_isp0; + uint32_t clk_gate_ip_isp1; + uint8_t res47[0xf8]; + uint32_t clk_gate_sclk_isp; + uint8_t res48[0x0c]; + uint32_t mcuisp_pwr_ctrl; /* 0x1001c910 */ + uint8_t res49[0x0ec]; + uint32_t clkout_cmu_isp; + uint32_t clkout_cmu_isp_div_stat; + uint8_t res50[0xf8]; + uint32_t cmu_isp_spare0; + uint32_t cmu_isp_spare1; + uint32_t cmu_isp_spare2; + uint32_t cmu_isp_spare3; + uint8_t res51[0x34e0]; + uint32_t cmu_isp_version; + uint8_t res52[0x2c]; + uint32_t cpll_lock; /* 10020020 */ + uint8_t res53[0xc]; + uint32_t dpll_lock; + uint8_t res54[0xc]; + uint32_t epll_lock; + uint8_t res55[0xc]; + uint32_t rpll_lock; + uint8_t res56[0xc]; + uint32_t ipll_lock; + uint8_t res57[0xc]; + uint32_t spll_lock; + uint8_t res58[0xc]; + uint32_t vpll_lock; + uint8_t res59[0xc]; + uint32_t mpll_lock; + uint8_t res60[0x8c]; + uint32_t cpll_con0; /* 10020120 */ + uint32_t cpll_con1; + uint32_t dpll_con0; + uint32_t dpll_con1; + uint32_t epll_con0; + uint32_t epll_con1; + uint32_t epll_con2; + uint8_t res601[0x4]; + uint32_t rpll_con0; + uint32_t rpll_con1; + uint32_t rpll_con2; + uint8_t res602[0x4]; + uint32_t ipll_con0; + uint32_t ipll_con1; + uint8_t res61[0x8]; + uint32_t spll_con0; + uint32_t spll_con1; + uint8_t res62[0x8]; + uint32_t vpll_con0; + uint32_t vpll_con1; + uint8_t res63[0x8]; + uint32_t mpll_con0; + uint32_t mpll_con1; + uint8_t res64[0x78]; + uint32_t clk_src_top0; /* 0x10020200 */ + uint32_t clk_src_top1; + uint32_t clk_src_top2; + uint32_t clk_src_top3; + uint32_t clk_src_top4; + uint32_t clk_src_top5; + uint32_t clk_src_top6; + uint32_t clk_src_top7; + uint8_t res65[0xc]; + uint32_t clk_src_disp10; /* 0x1002022c */ + uint8_t res66[0x10]; + uint32_t clk_src_mau; + uint32_t clk_src_fsys; + uint8_t res67[0x8]; + uint32_t clk_src_peric0; + uint32_t clk_src_peric1; + uint8_t res68[0x18]; + uint32_t clk_src_isp; + uint8_t res69[0x0c]; + uint32_t clk_src_top10; + uint32_t clk_src_top11; + uint32_t clk_src_top12; + uint8_t res70[0x74]; + uint32_t clk_src_mask_top0; + uint32_t clk_src_mask_top1; + uint32_t clk_src_mask_top2; + uint8_t res71[0x10]; + uint32_t clk_src_mask_top7; + uint8_t res72[0xc]; + uint32_t clk_src_mask_disp10; /* 0x1002032c */ + uint8_t res73[0x4]; + uint32_t clk_src_mask_mau; + uint8_t res74[0x8]; + uint32_t clk_src_mask_fsys; + uint8_t res75[0xc]; + uint32_t clk_src_mask_peric0; + uint32_t clk_src_mask_peric1; + uint8_t res76[0x18]; + uint32_t clk_src_mask_isp; + uint8_t res77[0x8c]; + uint32_t clk_mux_stat_top0; /* 0x10020400 */ + uint32_t clk_mux_stat_top1; + uint32_t clk_mux_stat_top2; + uint32_t clk_mux_stat_top3; + uint32_t clk_mux_stat_top4; + uint32_t clk_mux_stat_top5; + uint32_t clk_mux_stat_top6; + uint32_t clk_mux_stat_top7; + uint8_t res78[0x60]; + uint32_t clk_mux_stat_top10; + uint32_t clk_mux_stat_top11; + uint32_t clk_mux_stat_top12; + uint8_t res79[0x74]; + uint32_t clk_div_top0; /* 0x10020500 */ + uint32_t clk_div_top1; + uint32_t clk_div_top2; + uint8_t res80[0x20]; + uint32_t clk_div_disp10; + uint8_t res81[0x14]; + uint32_t clk_div_mau; + uint32_t clk_div_fsys0; + uint32_t clk_div_fsys1; + uint32_t clk_div_fsys2; + uint8_t res82[0x4]; + uint32_t clk_div_peric0; + uint32_t clk_div_peric1; + uint32_t clk_div_peric2; + uint32_t clk_div_peric3; + uint32_t clk_div_peric4; /* 0x10020568 */ + uint8_t res83[0x14]; + uint32_t clk_div_isp0; + uint32_t clk_div_isp1; + uint8_t res84[0x8]; + uint32_t clkdiv2_ratio; + uint8_t res850[0xc]; + uint32_t clkdiv4_ratio; + uint8_t res85[0x5c]; + uint32_t clk_div_stat_top0; + uint32_t clk_div_stat_top1; + uint32_t clk_div_stat_top2; + uint8_t res86[0x20]; + uint32_t clk_div_stat_disp10; + uint8_t res87[0x14]; + uint32_t clk_div_stat_mau; /* 0x10020644 */ + uint32_t clk_div_stat_fsys0; + uint32_t clk_div_stat_fsys1; + uint32_t clk_div_stat_fsys2; + uint8_t res88[0x4]; + uint32_t clk_div_stat_peric0; + uint32_t clk_div_stat_peric1; + uint32_t clk_div_stat_peric2; + uint32_t clk_div_stat_peric3; + uint32_t clk_div_stat_peric4; + uint8_t res89[0x14]; + uint32_t clk_div_stat_isp0; + uint32_t clk_div_stat_isp1; + uint8_t res90[0x8]; + uint32_t clkdiv2_stat0; + uint8_t res91[0xc]; + uint32_t clkdiv4_stat; + uint8_t res92[0x5c]; + uint32_t clk_gate_bus_top; /* 0x10020700 */ + uint8_t res93[0xc]; + uint32_t clk_gate_bus_gscl0; + uint8_t res94[0xc]; + uint32_t clk_gate_bus_gscl1; + uint8_t res95[0x4]; + uint32_t clk_gate_bus_disp1; + uint8_t res96[0x4]; + uint32_t clk_gate_bus_wcore; + uint32_t clk_gate_bus_mfc; + uint32_t clk_gate_bus_g3d; + uint32_t clk_gate_bus_gen; + uint32_t clk_gate_bus_fsys0; + uint32_t clk_gate_bus_fsys1; + uint32_t clk_gate_bus_fsys2; + uint32_t clk_gate_bus_mscl; + uint32_t clk_gate_bus_peric; + uint32_t clk_gate_bus_peric1; + uint8_t res97[0x8]; + uint32_t clk_gate_bus_peris0; + uint32_t clk_gate_bus_peris1; /* 0x10020764 */ + uint8_t res98[0x8]; + uint32_t clk_gate_bus_noc; + uint8_t res99[0xac]; + uint32_t clk_gate_top_sclk_gscl; + uint8_t res1000[0x4]; + uint32_t clk_gate_top_sclk_disp1; + uint8_t res100[0x10]; + uint32_t clk_gate_top_sclk_mau; + uint32_t clk_gate_top_sclk_fsys; + uint8_t res101[0xc]; + uint32_t clk_gate_top_sclk_peric; + uint8_t res102[0xc]; + uint32_t clk_gate_top_sclk_cperi; + uint8_t res103[0xc]; + uint32_t clk_gate_top_sclk_isp; + uint8_t res104[0x9c]; + uint32_t clk_gate_ip_gscl0; + uint8_t res105[0xc]; + uint32_t clk_gate_ip_gscl1; + uint8_t res106[0x4]; + uint32_t clk_gate_ip_disp1; + uint32_t clk_gate_ip_mfc; + uint32_t clk_gate_ip_g3d; + uint32_t clk_gate_ip_gen; /* 0x10020934 */ + uint8_t res107[0xc]; + uint32_t clk_gate_ip_fsys; + uint8_t res108[0x8]; + uint32_t clk_gate_ip_peric; + uint8_t res109[0xc]; + uint32_t clk_gate_ip_peris; + uint8_t res110[0xc]; + uint32_t clk_gate_ip_mscl; + uint8_t res111[0xc]; + uint32_t clk_gate_ip_block; + uint8_t res112[0xc]; + uint32_t bypass; + uint8_t res113[0x6c]; + uint32_t clkout_cmu_top; + uint32_t clkout_cmu_top_div_stat; + uint8_t res114[0xf8]; + uint32_t clkout_top_spare0; + uint32_t clkout_top_spare1; + uint32_t clkout_top_spare2; + uint32_t clkout_top_spare3; + uint8_t res115[0x34e0]; + uint32_t clkout_top_version; + uint8_t res116[0xc01c]; + uint32_t bpll_lock; /* 0x10030010 */ + uint8_t res117[0xfc]; + uint32_t bpll_con0; + uint32_t bpll_con1; + uint8_t res118[0xe8]; + uint32_t clk_src_cdrex; + uint8_t res119[0x1fc]; + uint32_t clk_mux_stat_cdrex; + uint8_t res120[0xfc]; + uint32_t clk_div_cdrex0; + uint32_t clk_div_cdrex1; + uint8_t res121[0xf8]; + uint32_t clk_div_stat_cdrex; + uint8_t res1211[0xfc]; + uint32_t clk_gate_bus_cdrex; + uint32_t clk_gate_bus_cdrex1; + uint8_t res122[0x1f8]; + uint32_t clk_gate_ip_cdrex; + uint8_t res123[0x10]; + uint32_t dmc_freq_ctrl; /* 0x10030914 */ + uint8_t res124[0x4]; + uint32_t pause; + uint32_t ddrphy_lock_ctrl; + uint8_t res125[0xdc]; + uint32_t clkout_cmu_cdrex; + uint32_t clkout_cmu_cdrex_div_stat; + uint8_t res126[0x8]; + uint32_t lpddr3phy_ctrl; + uint32_t lpddr3phy_con0; + uint32_t lpddr3phy_con1; + uint32_t lpddr3phy_con2; + uint32_t lpddr3phy_con3; + uint32_t lpddr3phy_con4; + uint32_t lpddr3phy_con5; /* 0x10030a28 */ + uint32_t pll_div2_sel; + uint8_t res127[0xd0]; + uint32_t cmu_cdrex_spare0; + uint32_t cmu_cdrex_spare1; + uint32_t cmu_cdrex_spare2; + uint32_t cmu_cdrex_spare3; + uint32_t cmu_cdrex_spare4; + uint8_t res128[0x34dc]; + uint32_t cmu_cdrex_version; /* 0x10033ff0 */ + uint8_t res129[0x400c]; + uint32_t kpll_lock; + uint8_t res130[0xfc]; + uint32_t kpll_con0; + uint32_t kpll_con1; + uint8_t res131[0xf8]; + uint32_t clk_src_kfc; + uint8_t res132[0x1fc]; + uint32_t clk_mux_stat_kfc; /* 0x10038400 */ + uint8_t res133[0xfc]; + uint32_t clk_div_kfc0; + uint8_t res134[0xfc]; + uint32_t clk_div_stat_kfc0; + uint8_t res135[0xfc]; + uint32_t clk_gate_bus_cpu_kfc; + uint8_t res136[0xfc]; + uint32_t clk_gate_sclk_cpu_kfc; + uint8_t res137[0x1fc]; + uint32_t clkout_cmu_kfc; + uint32_t clkout_cmu_kfc_div_stat;/* 0x10038a04 */ + uint8_t res138[0x5f8]; + uint32_t armclk_stopctrl_kfc; + uint8_t res139[0x4]; + uint32_t armclk_ema_ctrl_kfc; + uint32_t armclk_ema_status_kfc; + uint8_t res140[0x10]; + uint32_t pwr_ctrl_kfc; + uint32_t pwr_ctrl2_kfc; + uint8_t res141[0xd8]; + uint32_t kpll_con0_l8; + uint32_t kpll_con0_l7; + uint32_t kpll_con0_l6; + uint32_t kpll_con0_l5; + uint32_t kpll_con0_l4; + uint32_t kpll_con0_l3; + uint32_t kpll_con0_l2; + uint32_t kpll_con0_l1; + uint32_t iem_control_kfc; /* 0x10039120 */ + uint8_t res142[0xdc]; + uint32_t kpll_con1_l8; + uint32_t kpll_con1_l7; + uint32_t kpll_con1_l6; + uint32_t kpll_con1_l5; + uint32_t kpll_con1_l4; + uint32_t kpll_con1_l3; + uint32_t kpll_con1_l2; + uint32_t kpll_con1_l1; + uint8_t res143[0xe0]; + uint32_t clkdiv_iem_l8_kfc; /* 0x10039300 */ + uint32_t clkdiv_iem_l7_kfc; + uint32_t clkdiv_iem_l6_kfc; + uint32_t clkdiv_iem_l5_kfc; + uint32_t clkdiv_iem_l4_kfc; + uint32_t clkdiv_iem_l3_kfc; + uint32_t clkdiv_iem_l2_kfc; + uint32_t clkdiv_iem_l1_kfc; + uint8_t res144[0xe0]; + uint32_t l2_status_kfc; + uint8_t res145[0xc]; + uint32_t cpu_status_kfc; /* 0x10039410 */ + uint8_t res146[0xc]; + uint32_t ptm_status_kfc; + uint8_t res147[0xbdc]; + uint32_t cmu_kfc_spare0; + uint32_t cmu_kfc_spare1; + uint32_t cmu_kfc_spare2; + uint32_t cmu_kfc_spare3; + uint32_t cmu_kfc_spare4; + uint8_t res148[0x1fdc]; + uint32_t cmu_kfc_version; /* 0x1003bff0 */ }; struct exynos5_mct_regs { @@ -618,7 +1114,6 @@ struct arm_clk_ratios *get_arm_clk_ratios(void); * Initialize clock for the device */ struct mem_timings; -void system_clock_init(struct mem_timings *mem, - struct arm_clk_ratios *arm_clk_ratio); +void system_clock_init(void); #endif diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index e199e6b..fd15486 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -28,100 +28,6 @@ /* input clock of PLL: SMDK5420 has 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 -static struct arm_clk_ratios arm_clk_ratios[] = { - { - .arm_freq_mhz = 600, - - .apll_mdiv = 0xc8, - .apll_pdiv = 0x4, - .apll_sdiv = 0x1, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x2, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x1, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 800, - - .apll_mdiv = 0x64, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x3, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1000, - - .apll_mdiv = 0x7d, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x4, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1200, - - .apll_mdiv = 0x96, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x5, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1400, - - .apll_mdiv = 0xaf, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1700, - - .apll_mdiv = 0x1a9, - .apll_pdiv = 0x6, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - } -}; - /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { {0, 4, 0, -1}, @@ -173,8 +79,8 @@ static struct st_epll_con_val epll_div[] = { /* exynos5: return pll clock frequency */ unsigned long get_pll_clk(int pllreg) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; unsigned int freq; @@ -182,9 +88,6 @@ unsigned long get_pll_clk(int pllreg) case APLL: r = readl(&clk->apll_con0); break; - case BPLL: - r = readl(&clk->bpll_con0); - break; case MPLL: r = readl(&clk->mpll_con0); break; @@ -196,6 +99,16 @@ unsigned long get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + case SPLL: + r = readl(&clk->spll_con0); + break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); return 0; @@ -207,7 +120,8 @@ unsigned long get_pll_clk(int pllreg) * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] */ - if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL || + pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -221,7 +135,7 @@ unsigned long get_pll_clk(int pllreg) freq = CONFIG_SYS_CLK_FREQ; - if (pllreg == EPLL) { + if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 65536) * (freq / (p * (1 << s))); @@ -239,11 +153,10 @@ unsigned long get_pll_clk(int pllreg) unsigned long clock_get_periph_rate(enum periph_id peripheral) { - struct exynos5_clock *clk = - samsung_get_base_clock(); struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; unsigned long sclk, sub_clk; unsigned int src, div, sub_div; + struct exynos5_clock *clk = samsung_get_base_clock(); switch (peripheral) { case PERIPH_ID_UART0: @@ -275,10 +188,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) src = readl(&clk->sclk_src_isp); div = readl(&clk->sclk_div_isp); break; - case PERIPH_ID_SATA: - src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys0); - break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: @@ -303,26 +212,27 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) return -1; }; - src = (src >> bit_info->src_bit) & ((1 << bit_info->n_src_bits) - 1); - if (peripheral == PERIPH_ID_SATA) { - if (src) - sclk = get_pll_clk(BPLL); - else - sclk = get_pll_clk(MPLL); - } else { - if (src == SRC_MPLL) - sclk = get_pll_clk(MPLL); - else if (src == SRC_EPLL) - sclk = get_pll_clk(EPLL); - else if (src == SRC_VPLL) - sclk = get_pll_clk(VPLL); - else - return 0; + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS_SRC_MPLL: + sclk = get_pll_clk(MPLL); + break; + case EXYNOS_SRC_EPLL: + sclk = get_pll_clk(EPLL); + break; + case EXYNOS_SRC_VPLL: + sclk = get_pll_clk(VPLL); + break; + default: + return 0; } + /* Ratio clock division for this peripheral */ sub_div = (div >> bit_info->div_bit) & 0xf; sub_clk = sclk / (sub_div + 1); + /* Pre-ratio clock division for SDMMC0 and 2 */ if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { div = (div >> bit_info->prediv_bit) & 0xff; return sub_clk / (div + 1); @@ -334,8 +244,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) /* exynos5: return ARM clock frequency */ unsigned long get_arm_clk(void) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5_clock *clk = samsung_get_base_clock(); unsigned long div; unsigned long armclk; unsigned int arm_ratio; @@ -353,45 +262,20 @@ unsigned long get_arm_clk(void) return armclk; } -struct arm_clk_ratios *get_arm_clk_ratios(void) -{ - struct arm_clk_ratios *arm_ratio; - unsigned long arm_freq = 1700; /* FIXME: use get_arm_clk() */ - int i; - - for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); - i++, arm_ratio++) { - if (arm_ratio->arm_freq_mhz == arm_freq) - return arm_ratio; - } - - return NULL; -} - /* exynos5: set the mmc clock */ void set_mmc_clk(int dev_index, unsigned int div) { - struct exynos5_clock *clk = - samsung_get_base_clock(); - unsigned int *addr; - unsigned int val; + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + void *addr; + unsigned int val, shift; - /* - * CLK_DIV_FSYS1 - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] - * CLK_DIV_FSYS2 - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] - */ - if (dev_index < 2) { - addr = &clk->div_fsys1; - } else { - addr = &clk->div_fsys2; - dev_index -= 2; - } + addr = &clk->clk_div_fsys1; + shift = dev_index * 10; val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); + val &= ~(0x3ff << shift); + val |= (div & 0x3ff) << shift; writel(val, addr); } diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 2986cab..0a13c9e 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -26,420 +26,175 @@ #include "dp.h" #include "setup.h" -void system_clock_init(struct mem_timings *mem, - struct arm_clk_ratios *arm_clk_ratio) +void system_clock_init(void) { - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + struct exynos5420_clock *clk = + (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; - u32 val, tmp; + u32 val; /* Turn on the MCT as early as possible. */ mct_regs->g_tcon |= (1 << 8); - clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | MUX_APLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_core1); - } while ((val | MUX_MPLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); - tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK - | MUX_GPLL_SEL_MASK; - do { - val = readl(&clk->mux_stat_top2); - } while ((val | tmp) != val); - - clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cdrex); - } while ((val | MUX_BPLL_SEL_MASK) != val); - /* PLL locktime */ writel(APLL_LOCK_VAL, &clk->apll_lock); - writel(MPLL_LOCK_VAL, &clk->mpll_lock); - writel(BPLL_LOCK_VAL, &clk->bpll_lock); - writel(CPLL_LOCK_VAL, &clk->cpll_lock); - - writel(GPLL_LOCK_VAL, &clk->gpll_lock); - + writel(DPLL_LOCK_VAL, &clk->dpll_lock); writel(EPLL_LOCK_VAL, &clk->epll_lock); - writel(VPLL_LOCK_VAL, &clk->vpll_lock); + writel(IPLL_LOCK_VAL, &clk->ipll_lock); + writel(SPLL_LOCK_VAL, &clk->spll_lock); + writel(KPLL_LOCK_VAL, &clk->kpll_lock); + + setbits_le32(&clk->clk_src_cpu, MUX_HPM_SEL_MASK); - writel(CLK_REG_DISABLE, &clk->pll_div2_sel); - - writel(MUX_HPM_SEL_MASK, &clk->src_cpu); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | HPM_SEL_SCLK_MPLL) != val); - - val = arm_clk_ratio->arm2_ratio << 28 - | arm_clk_ratio->apll_ratio << 24 - | arm_clk_ratio->pclk_dbg_ratio << 20 - | arm_clk_ratio->atb_ratio << 16 - | arm_clk_ratio->periph_ratio << 12 - | arm_clk_ratio->acp_ratio << 8 - | arm_clk_ratio->cpud_ratio << 4 - | arm_clk_ratio->arm_ratio; - writel(val, &clk->div_cpu0); - do { - val = readl(&clk->div_stat_cpu0); - } while (0 != val); - - writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); - do { - val = readl(&clk->div_stat_cpu1); - } while (0 != val); + writel(0, &clk->clk_src_top6); + + writel(0, &clk->clk_src_cdrex); + writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc); + writel(HPM_RATIO, &clk->clk_div_cpu1); + writel(CLK_DIV_CPU0_VAL, &clk->clk_div_cpu0); /* Set APLL */ writel(APLL_CON1_VAL, &clk->apll_con1); - val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, - arm_clk_ratio->apll_sdiv); + val = set_pll(0xc8, 0x3, 0x1); writel(val, &clk->apll_con0); - while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) + while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) + ; + + writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc); + writel(CLK_DIV_KFC_VAL, &clk->clk_div_kfc0); + + /* Set KPLL*/ + writel(KPLL_CON1_VAL, &clk->kpll_con1); + val = set_pll(0xc8, 0x2, 0x2); + writel(val, &clk->kpll_con0); + while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) ; /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); - val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); + val = set_pll(0xc8, 0x3, 0x1); writel(val, &clk->mpll_con0); - while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) - ; - - /* - * Configure MUX_MPLL_FOUT to choose the direct clock source - * path and avoid the fixed DIV/2 block to save power - */ - setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL); - - /* Set BPLL */ - if (mem->use_bpll) { - writel(BPLL_CON1_VAL, &clk->bpll_con1); - val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); - writel(val, &clk->bpll_con0); - while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) - ; - - setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL); - } - - /* Set CPLL */ - writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); - writel(val, &clk->cpll_con0); - while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) + while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) ; - /* Set GPLL */ - writel(GPLL_CON1_VAL, &clk->gpll_con1); - val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); - writel(val, &clk->gpll_con0); - while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) + /* Set DPLL */ + writel(DPLL_CON1_VAL, &clk->dpll_con1); + val = set_pll(0xc8, 0x2, 0x2); + writel(val, &clk->dpll_con0); + while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0) ; /* Set EPLL */ writel(EPLL_CON2_VAL, &clk->epll_con2); writel(EPLL_CON1_VAL, &clk->epll_con1); - val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); + val = set_pll(0x64, 0x2, 0x1); writel(val, &clk->epll_con0); - while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) - ; - - /* Set VPLL */ - writel(VPLL_CON2_VAL, &clk->vpll_con2); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); - writel(val, &clk->vpll_con0); - while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) - ; - - writel(CLK_SRC_CORE0_VAL, &clk->src_core0); - writel(CLK_DIV_CORE0_VAL, &clk->div_core0); - while (readl(&clk->div_stat_core0) != 0) - ; - - writel(CLK_DIV_CORE1_VAL, &clk->div_core1); - while (readl(&clk->div_stat_core1) != 0) - ; - - writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); - while (readl(&clk->div_stat_sysrgt) != 0) + while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0) ; - writel(CLK_DIV_ACP_VAL, &clk->div_acp); - while (readl(&clk->div_stat_acp) != 0) - ; - - writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); - while (readl(&clk->div_stat_syslft) != 0) - ; - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - writel(TOP2_VAL, &clk->src_top2); - writel(CLK_SRC_TOP3_VAL, &clk->src_top3); - - writel(CLK_DIV_TOP0_VAL, &clk->div_top0); - while (readl(&clk->div_stat_top0)) - ; - - writel(CLK_DIV_TOP1_VAL, &clk->div_top1); - while (readl(&clk->div_stat_top1)) - ; - - writel(CLK_SRC_LEX_VAL, &clk->src_lex); - while (1) { - val = readl(&clk->mux_stat_lex); - if (val == (val | 1)) - break; - } - - writel(CLK_DIV_LEX_VAL, &clk->div_lex); - while (readl(&clk->div_stat_lex)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R1X_VAL, &clk->div_r1x); - while (readl(&clk->div_stat_r1x)) + /* Set CPLL */ + writel(CPLL_CON1_VAL, &clk->cpll_con1); + val = set_pll(0x6f, 0x2, 0x1); + writel(val, &clk->cpll_con0); + while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) ; - if (mem->use_bpll) { - writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | - MUX_MCLK_DPHY_SEL, &clk->src_cdrex); - } else { - writel(CLK_REG_DISABLE, &clk->src_cdrex); - } - - writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); - while (readl(&clk->div_stat_cdrex)) + /* Set IPLL */ + writel(IPLL_CON1_VAL, &clk->ipll_con1); + val = set_pll(0xB9, 0x3, 0x2); + writel(val, &clk->ipll_con0); + while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0) ; - val = readl(&clk->src_cpu); - val |= CLK_SRC_CPU_VAL; - writel(val, &clk->src_cpu); - - val = readl(&clk->src_top2); - val |= CLK_SRC_TOP2_VAL; - writel(val, &clk->src_top2); - - val = readl(&clk->src_core1); - val |= CLK_SRC_CORE1_VAL; - writel(val, &clk->src_core1); - - writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); - writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); - while (readl(&clk->div_stat_fsys0)) + /* Set VPLL */ + writel(VPLL_CON1_VAL, &clk->vpll_con1); + val = set_pll(0xd7, 0x3, 0x2); + writel(val, &clk->vpll_con0); + while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0) ; - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); - - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); - writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); - - writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); - writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); - writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); - writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); - writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); - writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); - writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); - writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); - - /* FIMD1 SRC CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); - - val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET - | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET - | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET - | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; - writel(val, &clk->div_fsys2); + /* Set BPLL */ + writel(BPLL_CON1_VAL, &clk->bpll_con1); + val = set_pll(0xc8, 0x3, 0x1); + writel(val, &clk->bpll_con0); + while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set SPLL */ + writel(SPLL_CON1_VAL, &clk->spll_con1); + val = set_pll(0xc8, 0x2, 0x3); + writel(val, &clk->spll_con0); + while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) + ; + + writel(CLK_DIV_CDREX0_VAL, &clk->clk_div_cdrex0); + writel(CLK_DIV_CDREX1_VAL, &clk->clk_div_cdrex1); + + writel(CLK_SRC_TOP0_VAL, &clk->clk_src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->clk_src_top1); + writel(CLK_SRC_TOP2_VAL, &clk->clk_src_top2); + writel(CLK_SRC_TOP7_VAL, &clk->clk_src_top7); + + writel(CLK_DIV_TOP0_VAL, &clk->clk_div_top0); + writel(CLK_DIV_TOP1_VAL, &clk->clk_div_top1); + writel(CLK_DIV_TOP2_VAL, &clk->clk_div_top2); + + writel(0, &clk->clk_src_top10); + writel(0, &clk->clk_src_top11); + writel(0, &clk->clk_src_top12); + + writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top3); + writel(CLK_SRC_TOP4_VAL, &clk->clk_src_top4); + writel(CLK_SRC_TOP5_VAL, &clk->clk_src_top5); + + /* DISP1 BLK CLK SELECTION */ + writel(CLK_SRC_DISP1_0_VAL, &clk->clk_src_disp10); + writel(CLK_DIV_DISP1_0_VAL, &clk->clk_div_disp10); + + /* AUDIO BLK */ + writel(AUDIO0_SEL_EPLL, &clk->clk_src_mau); + writel(DIV_MAU_VAL, &clk->clk_div_mau); + + /* FSYS */ + writel(CLK_SRC_FSYS0_VAL, &clk->clk_src_fsys); + writel(CLK_DIV_FSYS0_VAL, &clk->clk_div_fsys0); + writel(CLK_DIV_FSYS1_VAL, &clk->clk_div_fsys1); + writel(CLK_DIV_FSYS2_VAL, &clk->clk_div_fsys2); + + writel(CLK_SRC_ISP_VAL, &clk->clk_src_isp); + writel(CLK_DIV_ISP0_VAL, &clk->clk_div_isp0); + writel(CLK_DIV_ISP1_VAL, &clk->clk_div_isp1); + + writel(CLK_SRC_PERIC0_VAL, &clk->clk_src_peric0); + writel(CLK_SRC_PERIC1_VAL, &clk->clk_src_peric1); + + writel(CLK_DIV_PERIC0_VAL, &clk->clk_div_peric0); + writel(CLK_DIV_PERIC1_VAL, &clk->clk_div_peric1); + writel(CLK_DIV_PERIC2_VAL, &clk->clk_div_peric2); + writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3); + writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4); + + writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio); + writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio); + writel(CLK_DIV_G2D, &clk->clk_div_g2d); + + writel(CLK_SRC_CPU_VAL, &clk->clk_src_cpu); + writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top6); + writel(CLK_SRC_CDREX_VAL, &clk->clk_src_cdrex); + writel(CLK_SRC_KFC_VAL, &clk->clk_src_kfc); } void clock_gate(void) { - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - - /* CLK_GATE_IP_SYSRGT */ - clrbits_le32(&clk->gate_ip_sysrgt, CLK_C2C_MASK); - - /* CLK_GATE_IP_ACP */ - clrbits_le32(&clk->gate_ip_acp, CLK_SMMUG2D_MASK | - CLK_SMMUSSS_MASK | - CLK_SMMUMDMA_MASK | - CLK_ID_REMAPPER_MASK | - CLK_G2D_MASK | - CLK_SSS_MASK | - CLK_MDMA_MASK | - CLK_SECJTAG_MASK); - - /* CLK_GATE_BUS_SYSLFT */ - clrbits_le32(&clk->gate_bus_syslft, CLK_EFCLK_MASK); - - /* CLK_GATE_IP_ISP0 */ - clrbits_le32(&clk->gate_ip_isp0, CLK_UART_ISP_MASK | - CLK_WDT_ISP_MASK | - CLK_PWM_ISP_MASK | - CLK_MTCADC_ISP_MASK | - CLK_I2C1_ISP_MASK | - CLK_I2C0_ISP_MASK | - CLK_MPWM_ISP_MASK | - CLK_MCUCTL_ISP_MASK | - CLK_INT_COMB_ISP_MASK | - CLK_SMMU_MCUISP_MASK | - CLK_SMMU_SCALERP_MASK | - CLK_SMMU_SCALERC_MASK | - CLK_SMMU_FD_MASK | - CLK_SMMU_DRC_MASK | - CLK_SMMU_ISP_MASK | - CLK_GICISP_MASK | - CLK_ARM9S_MASK | - CLK_MCUISP_MASK | - CLK_SCALERP_MASK | - CLK_SCALERC_MASK | - CLK_FD_MASK | - CLK_DRC_MASK | - CLK_ISP_MASK); - - /* CLK_GATE_IP_ISP1 */ - clrbits_le32(&clk->gate_ip_isp1, CLK_SPI1_ISP_MASK | - CLK_SPI0_ISP_MASK | - CLK_SMMU3DNR_MASK | - CLK_SMMUDIS1_MASK | - CLK_SMMUDIS0_MASK | - CLK_SMMUODC_MASK | - CLK_3DNR_MASK | - CLK_DIS_MASK | - CLK_ODC_MASK); - - /* CLK_GATE_SCLK_ISP */ - clrbits_le32(&clk->gate_sclk_isp, SCLK_MPWM_ISP_MASK); - - /* CLK_GATE_IP_GSCL */ - clrbits_le32(&clk->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | - CLK_SMMUFIMC_LITE1_MASK | - CLK_SMMUFIMC_LITE0_MASK | - CLK_SMMUGSCL3_MASK | - CLK_SMMUGSCL2_MASK | - CLK_SMMUGSCL1_MASK | - CLK_SMMUGSCL0_MASK | - CLK_GSCL_WRAP_B_MASK | - CLK_GSCL_WRAP_A_MASK | - CLK_CAMIF_TOP_MASK | - CLK_GSCL3_MASK | - CLK_GSCL2_MASK | - CLK_GSCL1_MASK | - CLK_GSCL0_MASK); - - /* CLK_GATE_IP_DISP1 */ - clrbits_le32(&clk->gate_ip_disp1, CLK_SMMUTVX_MASK | - CLK_ASYNCTVX_MASK | - CLK_HDMI_MASK | - CLK_MIXER_MASK | - CLK_DSIM1_MASK); - - /* CLK_GATE_IP_MFC */ - clrbits_le32(&clk->gate_ip_mfc, CLK_SMMUMFCR_MASK | - CLK_SMMUMFCL_MASK | - CLK_MFC_MASK); - - /* CLK_GATE_IP_GEN */ - clrbits_le32(&clk->gate_ip_gen, CLK_SMMUMDMA1_MASK | - CLK_SMMUJPEG_MASK | - CLK_SMMUROTATOR_MASK | - CLK_MDMA1_MASK | - CLK_JPEG_MASK | - CLK_ROTATOR_MASK); - - /* CLK_GATE_IP_FSYS */ - clrbits_le32(&clk->gate_ip_fsys, CLK_WDT_IOP_MASK | - CLK_SMMUMCU_IOP_MASK | - CLK_SATA_PHY_I2C_MASK | - CLK_SATA_PHY_CTRL_MASK | - CLK_MCUCTL_MASK | - CLK_NFCON_MASK | - CLK_SMMURTIC_MASK | - CLK_RTIC_MASK | - CLK_MIPI_HSI_MASK | - CLK_USBOTG_MASK | - CLK_SATA_MASK | - CLK_PDMA1_MASK | - CLK_PDMA0_MASK | - CLK_MCU_IOP_MASK); - - /* CLK_GATE_IP_PERIC */ - clrbits_le32(&clk->gate_ip_peric, CLK_HS_I2C3_MASK | - CLK_HS_I2C2_MASK | - CLK_HS_I2C1_MASK | - CLK_HS_I2C0_MASK | - CLK_AC97_MASK | - CLK_SPDIF_MASK | - CLK_PCM2_MASK | - CLK_PCM1_MASK | - CLK_I2S2_MASK | - CLK_SPI2_MASK | - CLK_SPI0_MASK); - - /* - * CLK_GATE_IP_PERIS - * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID - * register (PRO_ID) works correctly when the OS kernel determines - * which chip it is running on. - */ - clrbits_le32(&clk->gate_ip_peris, CLK_RTC_MASK | - CLK_TZPC9_MASK | - CLK_TZPC8_MASK | - CLK_TZPC7_MASK | - CLK_TZPC6_MASK | - CLK_TZPC5_MASK | - CLK_TZPC4_MASK | - CLK_TZPC3_MASK | - CLK_TZPC2_MASK | - CLK_TZPC1_MASK | - CLK_TZPC0_MASK); - - /* CLK_GATE_BLOCK */ - clrbits_le32(&clk->gate_block, CLK_ACP_MASK); - - /* CLK_GATE_IP_CDREX */ - clrbits_le32(&clk->gate_ip_cdrex, CLK_DPHY0_MASK | - CLK_DPHY1_MASK | - CLK_TZASC_DRBXR_MASK); - + /* Not implemented for now. */ } void clock_init_dp_clock(void) { - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - - /* DP clock enable */ - setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); - - /* We run DP at 267 Mhz */ - setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); + /* Not implemented for now. */ } - diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 7a779ba..34056f3 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -26,6 +26,8 @@ struct exynos5_dmc; enum ddr_mode; struct exynos5_phy_control; +#define NOT_AVAILABLE 0 + /* TZPC : Register Offsets */ #define TZPC0_BASE 0x10100000 #define TZPC1_BASE 0x10110000 @@ -39,34 +41,50 @@ struct exynos5_phy_control; #define TZPC9_BASE 0x10190000 /* APLL_CON1 */ -#define APLL_CON1_VAL (0x00203800) +#define APLL_CON1_VAL (0x0020f300) /* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) +#define MPLL_CON1_VAL (0x0020f300) /* CPLL_CON1 */ -#define CPLL_CON1_VAL (0x00203800) +#define CPLL_CON1_VAL (0x0020f300) + +/* DPLL_CON1 */ +#define DPLL_CON1_VAL (0x0020f300) /* GPLL_CON1 */ -#define GPLL_CON1_VAL (0x00203800) +#define GPLL_CON1_VAL (NOT_AVAILABLE) /* EPLL_CON1, CON2 */ #define EPLL_CON1_VAL 0x00000000 #define EPLL_CON2_VAL 0x00000080 /* VPLL_CON1, CON2 */ -#define VPLL_CON1_VAL 0x00000000 -#define VPLL_CON2_VAL 0x00000080 +#define VPLL_CON1_VAL 0x0020f300 +#define VPLL_CON2_VAL NOT_AVAILABLE + +/* RPLL_CON1, CON2 */ +#define RPLL_CON1_VAL 0x00000000 +#define RPLL_CON2_VAL 0x00000080 /* BPLL_CON1 */ -#define BPLL_CON1_VAL 0x00203800 +#define BPLL_CON1_VAL 0x0020f300 + +/* SPLL_CON1 */ +#define SPLL_CON1_VAL 0x0020f300 + +/* IPLL_CON1 */ +#define IPLL_CON1_VAL 0x00000080 + +/* KPLL_CON1 */ +#define KPLL_CON1_VAL 0x200000 /* Set PLL */ #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) /* CLK_SRC_CPU */ /* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 +#define MUX_HPM_SEL 1 #define MUX_CPU_SEL 0 #define MUX_APLL_SEL 1 @@ -146,20 +164,11 @@ struct exynos5_phy_control; #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) -/* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (ACP_RATIO << 8) \ - | (CPUD_RATIO << 4) \ - | (ARM_RATIO)) - - /* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define CLK_SRC_FSYS0_VAL 0x33033300 +#define CLK_DIV_FSYS0_VAL 0x0 +#define CLK_DIV_FSYS1_VAL 0x04f13c4f +#define CLK_DIV_FSYS2_VAL 0x041d0000 /* CLK_DIV_CPU1 */ #define HPM_RATIO 0x2 @@ -191,141 +200,57 @@ struct exynos5_phy_control; #define CLK_DIV_SYSLFT_VAL 0x00000311 /* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x1 +#define CLK_SRC_CDREX_VAL 0x00000001 /* CLK_DIV_CDREX */ -#define MCLK_CDREX2_RATIO 0x0 -#define ACLK_EFCON_RATIO 0x1 -#define MCLK_DPHY_RATIO 0x1 -#define MCLK_CDREX_RATIO 0x1 -#define ACLK_C2C_200_RATIO 0x1 -#define C2C_CLK_400_RATIO 0x1 -#define PCLK_CDREX_RATIO 0x1 -#define ACLK_CDREX_RATIO 0x1 - -#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ - | (C2C_CLK_400_RATIO << 6) \ - | (PCLK_CDREX_RATIO << 4) \ - | (ACLK_CDREX_RATIO)) - -/* CLK_SRC_TOP0 */ -#define MUX_ACLK_300_GSCL_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID_SEL 0x0 -#define MUX_ACLK_400_G3D_MID_SEL 0x0 -#define MUX_ACLK_333_SEL 0x0 -#define MUX_ACLK_300_DISP1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID_SEL 0x0 -#define MUX_ACLK_200_SEL 0x0 -#define MUX_ACLK_166_SEL 0x0 -#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ - | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ - | (MUX_ACLK_400_G3D_MID_SEL << 20) \ - | (MUX_ACLK_333_SEL << 16) \ - | (MUX_ACLK_300_DISP1_SEL << 15) \ - | (MUX_ACLK_300_DISP1_MID_SEL << 14) \ - | (MUX_ACLK_200_SEL << 12) \ - | (MUX_ACLK_166_SEL << 8)) - -/* CLK_SRC_TOP1 */ -#define MUX_ACLK_400_G3D_SEL 0x1 -#define MUX_ACLK_400_ISP_SEL 0x0 -#define MUX_ACLK_400_IOP_SEL 0x0 -#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 -#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ - |(MUX_ACLK_400_ISP_SEL << 24) \ - |(MUX_ACLK_400_IOP_SEL << 20) \ - |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ - |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ - |(MUX_ACLK_300_DISP1_MID1_SEL << 8)) - -/* CLK_SRC_TOP2 */ -#define MUX_GPLL_SEL 0x1 -#define MUX_BPLL_USER_SEL 0x0 -#define MUX_MPLL_USER_SEL 0x0 -#define MUX_VPLL_SEL 0x1 -#define MUX_EPLL_SEL 0x1 -#define MUX_CPLL_SEL 0x1 -#define VPLLSRC_SEL 0x0 -#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ - | (MUX_BPLL_USER_SEL << 24) \ - | (MUX_MPLL_USER_SEL << 20) \ - | (MUX_VPLL_SEL << 16) \ - | (MUX_EPLL_SEL << 12) \ - | (MUX_CPLL_SEL << 8) \ - | (VPLLSRC_SEL)) -/* CLK_SRC_TOP3 */ -#define MUX_ACLK_333_SUB_SEL 0x1 -#define MUX_ACLK_400_SUB_SEL 0x1 -#define MUX_ACLK_266_ISP_SUB_SEL 0x1 -#define MUX_ACLK_266_GPS_SUB_SEL 0x0 -#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 -#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 -#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ - | (MUX_ACLK_400_SUB_SEL << 20) \ - | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ - | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ - | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ - | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ - | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ - | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) - -/* CLK_DIV_TOP0 */ -#define ACLK_300_DISP1_RATIO 0x2 -#define ACLK_400_G3D_RATIO 0x0 -#define ACLK_333_RATIO 0x0 -#define ACLK_266_RATIO 0x2 -#define ACLK_200_RATIO 0x3 -#define ACLK_166_RATIO 0x1 -#define ACLK_133_RATIO 0x1 -#define ACLK_66_RATIO 0x5 - -#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \ - | (ACLK_400_G3D_RATIO << 24) \ - | (ACLK_333_RATIO << 20) \ - | (ACLK_266_RATIO << 16) \ - | (ACLK_200_RATIO << 12) \ - | (ACLK_166_RATIO << 8) \ - | (ACLK_133_RATIO << 4) \ - | (ACLK_66_RATIO)) - -/* CLK_DIV_TOP1 */ -#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 -#define ACLK_66_PRE_RATIO 0x1 -#define ACLK_400_ISP_RATIO 0x1 -#define ACLK_400_IOP_RATIO 0x1 -#define ACLK_300_GSCL_RATIO 0x2 - -#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ - | (ACLK_66_PRE_RATIO << 24) \ - | (ACLK_400_ISP_RATIO << 20) \ - | (ACLK_400_IOP_RATIO << 16) \ - | (ACLK_300_GSCL_RATIO << 12)) - -/* APLL_LOCK */ -#define APLL_LOCK_VAL (0x546) -/* MPLL_LOCK */ -#define MPLL_LOCK_VAL (0x546) -/* CPLL_LOCK */ -#define CPLL_LOCK_VAL (0x546) -/* GPLL_LOCK */ -#define GPLL_LOCK_VAL (0x546) -/* EPLL_LOCK */ -#define EPLL_LOCK_VAL (0x3A98) -/* VPLL_LOCK */ -#define VPLL_LOCK_VAL (0x3A98) -/* BPLL_LOCK */ -#define BPLL_LOCK_VAL (0x546) - -#define MUX_MCLK_CDREX_SEL (1 << 4) -#define MUX_MCLK_DPHY_SEL (1 << 8) +#define CLK_DIV_CDREX0_VAL 0x30010100 +#define CLK_DIV_CDREX1_VAL 0x300 + +#define CLK_DIV_CDREX_VAL 0x17010100 + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL 0x01440020 + +/* CLK_SRC_TOP */ +#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP1_VAL 0x00100200 +#define CLK_SRC_TOP2_VAL 0x11101000 +#define CLK_SRC_TOP3_VAL 0x11111111 +#define CLK_SRC_TOP4_VAL 0x11110111 +#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP7_VAL 0x00022200 + +/* CLK_DIV_TOP */ +#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP1_VAL 0x13100B00 +#define CLK_DIV_TOP2_VAL 0x11101100 + +/* APLL_LOCK */ +#define APLL_LOCK_VAL (0x320) +/* MPLL_LOCK */ +#define MPLL_LOCK_VAL (0x258) +/* BPLL_LOCK */ +#define BPLL_LOCK_VAL (0x258) +/* CPLL_LOCK */ +#define CPLL_LOCK_VAL (0x190) +/* DPLL_LOCK */ +#define DPLL_LOCK_VAL (0x190) +/* GPLL_LOCK */ +#define GPLL_LOCK_VAL NOT_AVAILABLE +/* IPLL_LOCK */ +#define IPLL_LOCK_VAL (0x320) +/* KPLL_LOCK */ +#define KPLL_LOCK_VAL (0x258) +/* SPLL_LOCK */ +#define SPLL_LOCK_VAL (0x320) +/* RPLL_LOCK */ +#define RPLL_LOCK_VAL (0x2328) +/* EPLL_LOCK */ +#define EPLL_LOCK_VAL (0x2328) +/* VPLL_LOCK */ +#define VPLL_LOCK_VAL (0x258) #define MUX_APLL_SEL_MASK (1 << 0) -#define MUX_MPLL_FOUT_SEL (1 << 4) -#define MUX_BPLL_FOUT_SEL (1 << 0) #define MUX_MPLL_SEL_MASK (1 << 8) #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) #define MUX_CPLL_SEL_MASK (1 << 8) @@ -335,6 +260,7 @@ struct exynos5_phy_control; #define MUX_BPLL_SEL_MASK (1 << 0) #define MUX_HPM_SEL_MASK (1 << 20) #define HPM_SEL_SCLK_MPLL (1 << 21) +#define PLL_LOCKED (1 << 29) #define APLL_CON0_LOCKED (1 << 29) #define MPLL_CON0_LOCKED (1 << 29) #define BPLL_CON0_LOCKED (1 << 29) @@ -345,33 +271,75 @@ struct exynos5_phy_control; #define CLK_REG_DISABLE 0x0 #define TOP2_VAL 0x0110000 +/* CLK_SRC_LEX */ +#define CLK_SRC_LEX_VAL 0x0 + +/* CLK_DIV_LEX */ +#define CLK_DIV_LEX_VAL 0x10 + +/* CLK_DIV_R0X */ +#define CLK_DIV_R0X_VAL 0x10 + +/* CLK_DIV_L0X */ +#define CLK_DIV_R1X_VAL 0x10 + +/* CLK_DIV_ISP2 */ +#define CLK_DIV_ISP2_VAL 0x1 + +/* CLK_SRC_KFC */ +#define SRC_KFC_HPM_SEL (1 << 15) + +/* CLK_SRC_KFC */ +#define CLK_SRC_KFC_VAL 0x00008001 + +/* CLK_DIV_KFC */ +#define CLK_DIV_KFC_VAL 0x03300110 + +/* CLK_DIV2_RATIO */ +#define CLK_DIV2_RATIO 0x10111150 + +/* CLK_DIV4_RATIO */ +#define CLK_DIV4_RATIO 0x00000003 + +/* CLK_DIV_G2D */ +#define CLK_DIV_G2D 0x00000010 + /* CLK_SRC_PERIC0 */ -#define PWM_SEL 6 -#define UART3_SEL 6 -#define UART2_SEL 6 -#define UART1_SEL 6 -#define UART0_SEL 6 -/* SRC_CLOCK = SCLK_MPLL */ -#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ - | (UART0_SEL)) +#define SPDIF_SEL 1 +#define PWM_SEL 3 +#define UART4_SEL 3 +#define UART3_SEL 3 +#define UART2_SEL 3 +#define UART1_SEL 3 +#define UART0_SEL 3 +/* SRC_CLOCK = SCLK_RPLL */ +#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \ + | (PWM_SEL << 24) \ + | (UART4_SEL << 20) \ + | (UART3_SEL << 16) \ + | (UART2_SEL << 12) \ + | (UART1_SEL << 8) \ + | (UART0_SEL << 4)) /* CLK_SRC_PERIC1 */ -/* SRC_CLOCK = SCLK_MPLL */ +/* SRC_CLOCK = SCLK_EPLL */ #define SPI0_SEL 6 #define SPI1_SEL 6 #define SPI2_SEL 6 -#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \ - | (SPI1_SEL << 20) \ - | (SPI0_SEL << 16)) - -/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ -#define SPI0_ISP_SEL 6 -#define SPI1_ISP_SEL 6 -#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ - | (SPI0_ISP_SEL << 0) +#define AUDIO0_SEL 6 +#define AUDIO1_SEL 6 +#define AUDIO2_SEL 6 +#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \ + | (SPI1_SEL << 24) \ + | (SPI0_SEL << 20) \ + | (AUDIO2_SEL << 16) \ + | (AUDIO2_SEL << 12) \ + | (AUDIO2_SEL << 8)) + +/* CLK_SRC_ISP */ +#define CLK_SRC_ISP_VAL 0x33366000 +#define CLK_DIV_ISP0_VAL 0x13131300 +#define CLK_DIV_ISP1_VAL 0xbb110202 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ #define SPI0_ISP_RATIO 0xf @@ -380,32 +348,50 @@ struct exynos5_phy_control; | (SPI0_ISP_RATIO << 0) /* CLK_DIV_PERIL0 */ -#define UART5_RATIO 7 -#define UART4_RATIO 7 -#define UART3_RATIO 7 -#define UART2_RATIO 7 -#define UART1_RATIO 7 -#define UART0_RATIO 7 - -#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ - | (UART2_RATIO << 8) \ - | (UART1_RATIO << 4) \ - | (UART0_RATIO)) +#define PWM_RATIO 8 +#define UART4_RATIO 9 +#define UART3_RATIO 9 +#define UART2_RATIO 9 +#define UART1_RATIO 9 +#define UART0_RATIO 9 + +#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ + | (UART4_RATIO << 24) \ + | (UART3_RATIO << 20) \ + | (UART2_RATIO << 16) \ + | (UART1_RATIO << 12) \ + | (UART0_RATIO << 8)) + /* CLK_DIV_PERIC1 */ -#define SPI1_RATIO 0x7 -#define SPI0_RATIO 0xf -#define SPI1_SUB_RATIO 0x0 -#define SPI0_SUB_RATIO 0x0 -#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \ - | ((SPI1_RATIO << 16) \ - | (SPI0_SUB_RATIO << 8) \ - | (SPI0_RATIO << 0))) +#define SPI2_RATIO 0x1 +#define SPI1_RATIO 0x1 +#define SPI0_RATIO 0x1 +#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \ + | (SPI1_RATIO << 24) \ + | (SPI0_RATIO << 20)) /* CLK_DIV_PERIC2 */ -#define SPI2_RATIO 0xf -#define SPI2_SUB_RATIO 0x0 -#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \ - | (SPI2_RATIO << 0)) +#define PCM2_RATIO 0x3 +#define PCM1_RATIO 0x3 +#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \ + | (PCM1_RATIO << 16)) + +/* CLK_DIV_PERIC3 */ +#define AUDIO2_RATIO 0x5 +#define AUDIO1_RATIO 0x5 +#define AUDIO0_RATIO 0x5 +#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \ + | (AUDIO1_RATIO << 24) \ + | (AUDIO0_RATIO << 20)) + +/* CLK_DIV_PERIC4 */ +#define SPI2_PRE_RATIO 0x2 +#define SPI1_PRE_RATIO 0x2 +#define SPI0_PRE_RATIO 0x2 +#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ + | (SPI1_PRE_RATIO << 16) \ + | (SPI0_PRE_RATIO << 8)) + /* CLK_DIV_FSYS2 */ #define MMC2_RATIO_MASK 0xf #define MMC2_RATIO_VAL 0x3 @@ -435,17 +421,12 @@ struct exynos5_phy_control; /* CLK_DIV_L0X */ #define CLK_DIV_R1X_VAL 0x10 -/* CLK_DIV_ISP0 */ -#define CLK_DIV_ISP0_VAL 0x31 - -/* CLK_DIV_ISP1 */ -#define CLK_DIV_ISP1_VAL 0x0 - /* CLK_DIV_ISP2 */ #define CLK_DIV_ISP2_VAL 0x1 /* CLK_SRC_DISP1_0 */ -#define CLK_SRC_DISP1_0_VAL 0x6 +#define CLK_SRC_DISP1_0_VAL 0x10666600 +#define CLK_DIV_DISP1_0_VAL 0x01050210 /* * DIV_DISP1_0 @@ -538,6 +519,12 @@ struct exynos5_phy_control; #define CLK_MIXER_MASK (1 << 5) #define CLK_DSIM1_MASK (1 << 3) +/* AUDIO CLK SEL */ +#define AUDIO0_SEL_EPLL (0x6 << 28) +#define AUDIO0_RATIO 0x5 +#define PCM0_RATIO 0x3 +#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20) + /* CLK_GATE_IP_GEN */ #define CLK_SMMUMDMA1_MASK (1 << 9) #define CLK_SMMUJPEG_MASK (1 << 7) diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 4cc2e4b..7cf19c5 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -150,11 +150,12 @@ static void setup_memory(struct mem_timings *mem, int is_resume) static struct mem_timings *setup_clock(void) { struct mem_timings *mem = get_mem_timings(); - struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); if (!mem) { die("Unable to auto-detect memory timings\n"); } - system_clock_init(mem, arm_ratios); + + system_clock_init(); + return mem; }

1 0

New patch to review for coreboot: 1a0eedf exynos5420: Make the ps_hold_setup function public.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3657 -gerrit commit 1a0eedf3a550beb35af949e706b5105f9dc293b5 Author: Gabe Black <gabeblack(a)google.com> Date: Fri May 17 11:17:15 2013 -0700 exynos5420: Make the ps_hold_setup function public. This function had been declared in a public header file, but was marked static when actually defined. Change-Id: Ia551a5a12e7dbaf7bc00861e085695145ab7b91a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/power.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/power.c b/src/cpu/samsung/exynos5420/power.c index 029efc9..82791b6 100644 --- a/src/cpu/samsung/exynos5420/power.c +++ b/src/cpu/samsung/exynos5420/power.c @@ -24,9 +24,10 @@ #include <arch/hlt.h> #include "cpu.h" #include "power.h" +#include "setup.h" #include "sysreg.h" -static void ps_hold_setup(void) +void ps_hold_setup(void) { struct exynos5_power *power = samsung_get_base_power();

1 0

New patch to review for coreboot: 51a5f17 Exynos5420: Clean up console code
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3656 -gerrit commit 51a5f17ab5c936bcb402de73ed7e0491e7d37d62 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 12:29:37 2013 -0700 Exynos5420: Clean up console code - Don't initialize console twice in the bootblock - remove printk in memory init that would mess up the UART - unconditionally run console_init() in romstage, as it is also unconditionally run in the bootblock. Change-Id: I983d011c6ca602445f447d17799c1b2a33e8bd1d Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/bootblock.c | 3 --- src/mainboard/google/pit/memory.c | 1 - src/mainboard/google/pit/romstage.c | 5 +++-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index f523428..d3d737e 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include "clk.h" #include "wakeup.h" @@ -38,6 +37,4 @@ void bootblock_cpu_init(void) * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is * already handled by iROM so there's no need to setup again. */ - - console_init(); } diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c index e420fe0..68c2bd6 100644 --- a/src/mainboard/google/pit/memory.c +++ b/src/mainboard/google/pit/memory.c @@ -490,7 +490,6 @@ static int board_get_config(void) id1 = gpio_read_mvl3(BOARD_ID1_GPIO); if (id0 < 0 || id1 < 0) return -1; - printk(BIOS_DEBUG, "%s: id0: %u, id1: %u\n", __func__, id0, id1); for (i = 0; i < ARRAY_SIZE(id_map); i++) { if (id0 == id_map[i].id0 && id1 == id_map[i].id1) { diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 08f19f5..4cc2e4b 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -129,7 +129,7 @@ static void setup_gpio(void) static void setup_memory(struct mem_timings *mem, int is_resume) { - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", mem->mem_manuf, mem->mem_type, mem->mpll_mdiv, @@ -168,8 +168,9 @@ void main(void) * to re-initialize serial console drivers again. */ mem = setup_clock(); + console_init(); + if (!is_resume) { - console_init(); setup_power(); }

1 0

New patch to review for coreboot: 7430bb5 exynos5250: Clear the framebuffer before making it uncacheable.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3655 -gerrit commit 7430bb5c8ba9fa4647f10811f02e799d6bc02436 Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 23:06:47 2013 -0700 exynos5250: Clear the framebuffer before making it uncacheable. If we clear the framebuffer and then flush it back to memory using cache operations, the writes are going to be full cachelines at a time. If we make it uncacheable first, the writes will be serialized writes of whatever sized chunks memset uses, probably 4 bytes or less. Change-Id: I1b81731cfed00ae091ba6357451ab186d16f559e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index d2a6df7..3687ea8 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev) lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ + /* * We need to clean and invalidate the framebuffer region and disable * caching as well. We assume that our dcache <--> memory address @@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); - memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); }

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New patch to review for coreboot: 42fb287 exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3654 -gerrit commit 42fb28706ecbe28ae32bffbed2699e6d28c17852 Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 22:57:34 2013 -0700 exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer. At one time it seemed to be necessary to disable and then re-enable the MMU when setting the framebuffer to be uncache-able due to bugs in the MMU management code. Since those bugs have been fixed, this is no longer necessary. Change-Id: I5f7b9bd14dc9929efe1834ec9a258d388b8c94e9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 3ab57c9..d2a6df7 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -105,15 +105,11 @@ static void exynos_displayport_init(device_t dev) * Note: We may want to do something clever to ensure the framebuffer * region is aligned such that we don't change dcache policy for other * stuff inadvertantly. - * - * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); dcache_clean_invalidate_by_mva(lower, upper - lower); - dcache_mmu_disable(); mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); - dcache_mmu_enable(); mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG,

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New patch to review for coreboot: 80bf2c5 ARM: Fix up page table/cachability management.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3653 -gerrit commit 80bf2c53a23020cf05757a185cb6d8fa1e652e3c Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 22:45:54 2013 -0700 ARM: Fix up page table/cachability management. When modifying the page tables, use writel to ensure the writes happen, flush the page tables themselves to ensure they're visible to the MMU if it doesn't look at the caches, and invalidate the right TLB entries. The first two changes are probably safer but may not be strictly necessary. The third change is necessary because we were invalidating the TLB using i which was in megabytes but using an instruction that expects an address in bytes. One symptom of this problem was that the framebuffer, which was supposed to be marked uncacheable, was only being partially updated since some of the updates were still in the cache. With this change the graphics show up correctly. Change-Id: I5475df29690371459b0d37a304eebc62f81dd76b Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/lib/mmu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index 594bba5..7d6d46a 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -34,6 +34,7 @@ #include <console/console.h> #include <arch/cache.h> +#include <arch/io.h> #define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */ @@ -44,11 +45,14 @@ void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) unsigned int i; uint32_t *ttb_entry = (uint32_t *)ttb_addr; printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", - start_mb << 20, ((start_mb + size_mb) << 20) - 1); + start_mb*MiB, start_mb*MiB + size_mb*MiB - 1); + + for (i = start_mb; i < start_mb + size_mb; i++) + writel(0, &ttb_entry[i]); for (i = start_mb; i < start_mb + size_mb; i++) { - ttb_entry[i] = 0; - tlbimvaa(i); + dccmvac((uintptr_t)&ttb_entry[i]); + tlbimvaa(i*MiB); } } @@ -99,9 +103,14 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); + /* Write out page table entries. */ + for (i = start_mb; i < start_mb + size_mb; i++) + writel((i << 20) | attr, &ttb_entry[i]); + + /* Flush the page table entries, and old translations from the TLB. */ for (i = start_mb; i < start_mb + size_mb; i++) { - ttb_entry[i] = (i << 20) | attr; - tlbimvaa(start_mb); + dccmvac((uintptr_t)&ttb_entry[i]); + tlbimvaa(i*MiB); } }

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New patch to review for coreboot: 0c6f272 exynos5250: Simplify the graphics code by eliminating the unused color map.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3652 -gerrit commit 0c6f272901a5e58d739272339bdf26a82fe39d9e Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 15:58:46 2013 -0700 exynos5250: Simplify the graphics code by eliminating the unused color map. The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: Ia6a41cefdf8b29fe7d68f9596a156eced6eb5df8 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 21 +++++---------------- src/cpu/samsung/exynos5250/dp-core.h | 16 ++++------------ src/cpu/samsung/exynos5250/fb.c | 29 ++++++++--------------------- src/mainboard/google/snow/mainboard.c | 2 +- 4 files changed, 18 insertions(+), 50 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index b51a591..3ab57c9 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -68,12 +68,10 @@ static void exynos_displayport_init(device_t dev) /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. */ - vidinfo_t vi; struct exynos5_fimd_panel panel; unsigned long int fb_size; u32 lcdbase; - memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); panel.is_dp = 1; /* Display I/F is eDP */ @@ -94,18 +92,10 @@ static void exynos_displayport_init(device_t dev) panel.xres = conf->xres; panel.yres = conf->yres; - vi.vl_col = conf->xres; - vi.vl_row = conf->yres; - vi.vl_bpix = conf->bpp; - /* - * The size is a magic number from hardware. Allocate enough for the - * frame buffer and color map. - */ + /* The size is a magic number from hardware. */ fb_size = conf->xres * conf->yres * (conf->bpp / 8); - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); - printk(BIOS_SPEW, "LCD colormap base is %p\n", (void *)(lcdbase)); - mmio_resource(dev, 0, lcdbase/KiB, 64); - vi.cmap = (void *)lcdbase; + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); + printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); /* * We need to clean and invalidate the framebuffer region and disable @@ -119,18 +109,17 @@ static void exynos_displayport_init(device_t dev) * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); - uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); + uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); dcache_clean_invalidate_by_mva(lower, upper - lower); dcache_mmu_disable(); mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); dcache_mmu_enable(); - lcdbase += 64*KiB; mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ - ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); + ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5250/dp-core.h b/src/cpu/samsung/exynos5250/dp-core.h index 144524d..73f4638 100644 --- a/src/cpu/samsung/exynos5250/dp-core.h +++ b/src/cpu/samsung/exynos5250/dp-core.h @@ -117,14 +117,6 @@ struct s5p_dp_device { struct link_train link_train; }; -/* this struct is used by mainboards to pass mode info to the driver */ -typedef struct vidinfo { - u16 vl_col; - u16 vl_row; - u8 vl_bpix; - u16 *cmap; -} vidinfo_t; - /* s5p_dp_reg.c */ /* @@ -260,9 +252,9 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; -void fb_init(vidinfo_t *panel_info, void *lcdbase, - struct exynos5_fimd_panel *pd); +void fb_init(unsigned long int fb_size, void *lcdbase, + struct exynos5_fimd_panel *pd); int dp_controller_init(struct s5p_dp_device *dp_device); -int lcd_ctrl_init(vidinfo_t *panel_info, - struct exynos5_fimd_panel *panel_data, void *lcdbase); +int lcd_ctrl_init(unsigned long int fb_size, + struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* CPU_SAMSUNG_EXYNOS5250_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5250/fb.c b/src/cpu/samsung/exynos5250/fb.c index d4c3d44..760f5ee 100644 --- a/src/cpu/samsung/exynos5250/fb.c +++ b/src/cpu/samsung/exynos5250/fb.c @@ -116,32 +116,21 @@ static void fimd_bypass(void) sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } -/* Calculate the size of Framebuffer from the resolution */ -static u32 calc_fbsize(vidinfo_t *panel_info) -{ - /* They had PAGE_SIZE here instead of 4096. - * but that's a totally arbitrary number -- everything nowadays - * has lots of page sizes. - * So keep it obvious. - */ - return ALIGN((panel_info->vl_col * panel_info->vl_row * - ((1<<panel_info->vl_bpix) / 8)), 4096); -} - /* * Initialize display controller. * * @param lcdbase pointer to the base address of framebuffer. * @pd pointer to the main panel_data structure */ -void fb_init(vidinfo_t *panel_info, void *lcdbase, - struct exynos5_fimd_panel *pd) +void fb_init(unsigned long int fb_size, void *lcdbase, + struct exynos5_fimd_panel *pd) { unsigned int val; - u32 fbsize; struct exynos5_fimd *fimd = samsung_get_base_fimd(); struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl(); + fb_size = ALIGN(fb_size, 4096); + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); writel(val, &fimd->vidcon0); @@ -161,9 +150,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, writel(val, &disp_ctrl->vidtcon2); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); - - fbsize = calc_fbsize(panel_info); - writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + writel((unsigned int)lcdbase + fb_size, &fimd->vidw00add1b0); writel(pd->xres * 2, &fimd->vidw00add2); @@ -586,12 +573,12 @@ int dp_controller_init(struct s5p_dp_device *dp_device) * @param lcdbase Base address of LCD frame buffer * @return 0 if ok, -ve error code on error */ -int lcd_ctrl_init(vidinfo_t *panel_info, - struct exynos5_fimd_panel *panel_data, void *lcdbase) +int lcd_ctrl_init(unsigned long int fb_size, + struct exynos5_fimd_panel *panel_data, void *lcdbase) { int ret = 0; fimd_bypass(); - fb_init(panel_info, lcdbase, panel_data); + fb_init(fb_size, lcdbase, panel_data); return ret; } diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 2dd56fc..76605bb 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -226,7 +226,7 @@ static void mainboard_init(device_t dev) disable_usb30_pll(); fb_addr = cbmem_find(CBMEM_ID_CONSOLE); - set_vbe_mode_info_valid(&edid, (uintptr_t)(fb_addr) + 64*KiB); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); do {

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coreboot-gerrit July 2013