coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

1 participants
1030 discussions

New patch to review for coreboot: 1e92b47 exynos5420: use speed parameter in i2c_init() for HSI2C
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3701 -gerrit commit 1e92b473b8e024c3e171fceccaaf9a227293a531 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 22 19:40:43 2013 -0700 exynos5420: use speed parameter in i2c_init() for HSI2C This allows us to set different speeds for each HSI2C bus. Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/i2c.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index cbe7a79..b16d068 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -93,11 +93,6 @@ #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) -/* Controller operating frequency, timing values for operation - * are calculated against this frequency - */ -#define HSI2C_FS_TX_CLOCK 1000000 - /* S3C I2C Controller bits */ #define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ @@ -244,11 +239,11 @@ static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) write32(I2C_MODE_MT | I2C_TXRX_ENA, &bus->regs->iicstat); } -static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) +static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus, + unsigned int bus_freq_hz) { struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; unsigned long clkin = clock_get_periph_rate(i2c_bus->periph_id); - unsigned int op_clk = HSI2C_FS_TX_CLOCK; unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; @@ -259,7 +254,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) * uTemp2 = TSCLK_L + TSCLK_H */ t_ftl_cycle = (read32(&hsregs->usi_conf) >> 16) & 0x7; - utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + utemp0 = (clkin / bus_freq_hz) - 8 - 2 * t_ftl_cycle; /* CLK_DIV max is 256 */ for (i = 0; i < 256; i++) { @@ -274,7 +269,8 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) return -1; } -static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) +static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus, + unsigned int bus_freq_hz) { struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; unsigned int t_sr_release; @@ -288,7 +284,7 @@ static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) u32 i2c_timing_s3; u32 i2c_timing_sla; - hsi2c_get_clk_details(i2c_bus); + hsi2c_get_clk_details(i2c_bus, bus_freq_hz); n_clkdiv = i2c_bus->clk_div; t_scl_l = i2c_bus->clk_cycle / 2; @@ -341,7 +337,8 @@ static void i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) write32(i2c_ctl, &i2c->usi_ctl); /* Initialize the configure registers */ - hsi2c_ch_init(i2c_bus); + /* FIXME: This just assumes 100KHz as a default bus freq */ + hsi2c_ch_init(i2c_bus, 100000); } void i2c_init(unsigned bus_num, int speed, int slaveadd) @@ -352,12 +349,8 @@ void i2c_init(unsigned bus_num, int speed, int slaveadd) i2c_reset(i2c); - /* FIXME(dhendrix): hsi2c_ch_init doesn't take a speed or slaveadd - * parameter, so we should split it out and call it directly from - * romstage without the unneeded parameters. - */ if (i2c->is_highspeed) - hsi2c_ch_init(i2c); + hsi2c_ch_init(i2c, speed); else i2c_ch_init(i2c, speed, slaveadd); }

1 0

New patch to review for coreboot: b1cfdca exynos5420: Change some clock settings.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3700 -gerrit commit b1cfdcaf828e5f64a9dfa8a32a4f21ff4ad558d4 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jun 22 20:05:37 2013 -0700 exynos5420: Change some clock settings. This change adjusts some clock settings so that they match U-Boot. There are three different changes. 1. Change the source for psgen from the oscillator clock to the pclk. 2. Change the pll feeding the SPI busses from epll to mpll, as suggested in the manual. 3. Change the SPI prescaller. Change-Id: Ib54a255bc14fc286629dac86db9b8cf8e75a610b Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/setup.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 7d486f0..7d63772 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -227,7 +227,7 @@ struct exynos5_phy_control; #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111110 #define CLK_SRC_TOP7_VAL 0x00022200 /* CLK_DIV_TOP */ @@ -332,10 +332,11 @@ struct exynos5_phy_control; | (UART0_SEL << 4)) /* CLK_SRC_PERIC1 */ +/* SRC_CLOCK = SCLK_MPLL */ +#define SPI0_SEL 3 +#define SPI1_SEL 3 +#define SPI2_SEL 3 /* SRC_CLOCK = SCLK_EPLL */ -#define SPI0_SEL 6 -#define SPI1_SEL 6 -#define SPI2_SEL 6 #define AUDIO0_SEL 6 #define AUDIO1_SEL 6 #define AUDIO2_SEL 6 @@ -395,9 +396,9 @@ struct exynos5_phy_control; | (AUDIO0_RATIO << 20)) /* CLK_DIV_PERIC4 */ -#define SPI2_PRE_RATIO 0x2 -#define SPI1_PRE_RATIO 0x2 -#define SPI0_PRE_RATIO 0x2 +#define SPI2_PRE_RATIO 0x3 +#define SPI1_PRE_RATIO 0x3 +#define SPI0_PRE_RATIO 0x3 #define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ | (SPI1_PRE_RATIO << 16) \ | (SPI0_PRE_RATIO << 8))

1 0

New patch to review for coreboot: 8c897ed exynos5420: Fix the way the rate of the input clock for i2c buses is found.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3699 -gerrit commit 8c897ed6d42d6f603ec3e6f77eebb9ad49791d53 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jun 22 19:43:40 2013 -0700 exynos5420: Fix the way the rate of the input clock for i2c buses is found. The clock divider was being read from registers incorrectly which meant that the periph rate was wrong. Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index e5ab001..8c4baf8 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -196,9 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case PERIPH_ID_I2C9: case PERIPH_ID_I2C10: sclk = get_pll_clk(MPLL); - sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1; - div = (readl(&clk->clk_div_top0) & 0x7) + 1; - return (sclk / sub_div) / div; + div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1; + return sclk / div; default: printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral); return -1;

1 0

New patch to review for coreboot: d6a3c94 snow: Add flush to UART driver.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3698 -gerrit commit d6a3c94f930b3c4d21926a59b305ae28aae5c725 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 5 14:06:55 2013 -0700 snow: Add flush to UART driver. Wait for UART FIFO to be ready. (Credit to dhendrix for finding the bits to test with.) Change-Id: Ib6733e422cbc1c61b942bd90d85f88a3f412d6ff Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/uart.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 24812ae..41dc709 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -162,12 +162,19 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } +static void exynos5_uart_tx_flush(void) +{ + struct s5p_uart *uart = (struct s5p_uart *)base_port; + + while (readl(&uart->ufstat) & 0x1ff0000); +} + #if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, -// .tx_flush = exynos5_uart_tx_flush, + .tx_flush = exynos5_uart_tx_flush, .rx_byte = exynos5_uart_rx_byte, // .tst_byte = exynos5_uart_tst_byte, }; @@ -196,6 +203,7 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { + exynos5_uart_tx_flush(); } #endif

1 0

New patch to review for coreboot: 4a50058 Exynos5420: Initialize USB PHY
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3697 -gerrit commit 4a50058d85947f2a6250705babd13449ceb5238d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 20 16:13:19 2013 -0700 Exynos5420: Initialize USB PHY ... this is needed for libpayload to talk to USB devices. (forward ported from https://gerrit.chromium.org/gerrit/#/c/55554) Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/Makefile.inc | 1 + src/cpu/samsung/exynos5420/chip.h | 5 ++ src/cpu/samsung/exynos5420/cpu.c | 14 ++++- src/cpu/samsung/exynos5420/usb.c | 105 ++++++++++++++++++++++++++++++++ src/cpu/samsung/exynos5420/usb.h | 62 +++++++++++++++++++ src/mainboard/google/pit/devicetree.cb | 2 + 6 files changed, 186 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 6f9b91b..8540409 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c +ramstage-y += usb.c exynos5420_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5420 BL1\n" diff --git a/src/cpu/samsung/exynos5420/chip.h b/src/cpu/samsung/exynos5420/chip.h index 7f1aadc..f2c710d 100644 --- a/src/cpu/samsung/exynos5420/chip.h +++ b/src/cpu/samsung/exynos5420/chip.h @@ -20,6 +20,8 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_H #define CPU_SAMSUNG_EXYNOS5420_H +#include "gpio.h" + struct cpu_samsung_exynos5420_config { /* special magic numbers! */ int clkval_f; @@ -34,6 +36,9 @@ struct cpu_samsung_exynos5420_config { int yres; int bpp; + int usb_vbus_gpio; + int usb_hsic_gpio; + u32 lcdbase; }; diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 6e360bf..d204556 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -29,6 +29,7 @@ #include "dp-core.h" #include "cpu.h" #include "clk.h" +#include "usb.h" #include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) @@ -119,15 +120,22 @@ static void exynos_displayport_init(device_t dev) ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_init(device_t dev) +static void cpu_enable(device_t dev) { exynos_displayport_init(dev); + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); set_cpu_id(); +} + +static void cpu_init(device_t dev) +{ printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); + + usb_init(dev); } static void cpu_noop(device_t dev) @@ -137,8 +145,8 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, .set_resources = cpu_noop, - .enable_resources = cpu_init, - .init = cpu_noop, + .enable_resources = cpu_enable, + .init = cpu_init, .scan_bus = 0, }; diff --git a/src/cpu/samsung/exynos5420/usb.c b/src/cpu/samsung/exynos5420/usb.c new file mode 100644 index 0000000..4d07699 --- /dev/null +++ b/src/cpu/samsung/exynos5420/usb.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include "gpio.h" +#include "power.h" +#include "cpu.h" +#include "usb.h" +#include "chip.h" + +/* Enable VBUS */ +static int usb_vbus_init(int vbus_gpio) +{ + /* Enable VBUS power switch */ + gpio_direction_output(GPIO_X11, 1); + /* VBUS turn ON time */ + mdelay(3); + + return 0; +} + +/* Setup the EHCI host controller. */ + +static void setup_usb_phy(struct usb_phy *usb, int hsic_gpio) +{ + unsigned int hostphy_ctrl0; + + power_enable_usb_phy(); + + /* Setting up host and device simultaneously */ + hostphy_ctrl0 = readl(&usb->usbphyctrl0); + hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | + /* HOST Phy setting */ + HOST_CTRL0_PHYSWRST | + HOST_CTRL0_PHYSWRSTALL | + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESUSPEND | + HOST_CTRL0_FORCESLEEP); + hostphy_ctrl0 |= ( /* Setting up the ref freq */ + CLK_24MHZ << 16 | + /* HOST Phy setting */ + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); + writel(hostphy_ctrl0, &usb->usbphyctrl0); + udelay(10); + clrbits_le32(&usb->usbphyctrl0, + HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); + udelay(20); + + /* EHCI Ctrl setting */ + setbits_le32(&usb->ehcictrl, + EHCICTRL_ENAINCRXALIGN | + EHCICTRL_ENAINCR4 | + EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16); + + /* HSIC USB Hub initialization. */ + // FIXME board specific? + gpio_direction_output(hsic_gpio, 0); + udelay(100); + gpio_direction_output(hsic_gpio, 1); + udelay(5000); + + clrbits_le32(&usb->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST); + udelay(10); + clrbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST); + + /* PHY clock and power setup time */ + // FIXME If this happens more than 50ms before executing the payload, + // we might not need this delay. + mdelay(50); +} + +void usb_init(device_t dev) +{ + struct usb_phy *usb; + struct cpu_samsung_exynos5420_config *conf = dev->chip_info; + + usb_vbus_init(conf->usb_vbus_gpio); + usb = (struct usb_phy *) samsung_get_base_usb_phy(); + setup_usb_phy(usb, conf->usb_hsic_gpio); +} diff --git a/src/cpu/samsung/exynos5420/usb.h b/src/cpu/samsung/exynos5420/usb.h new file mode 100644 index 0000000..1b7d635 --- /dev/null +++ b/src/cpu/samsung/exynos5420/usb.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5420_USB_H +#define CPU_SAMSUNG_EXYNOS5420_USB_H + +#define CLK_24MHZ 5 + +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) + +#define HOST_CTRL0_FSEL_MASK (7 << 16) + +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) + +/* Register map for PHY control */ +struct usb_phy { + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; +}; + +void usb_init(device_t dev); + +#endif diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb index 3b6cdb9..0c687c4 100644 --- a/src/mainboard/google/pit/devicetree.cb +++ b/src/mainboard/google/pit/devicetree.cb @@ -30,4 +30,6 @@ chip cpu/samsung/exynos5420 register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" + register "usb_vbus_gpio" = "GPIO_X11" + register "usb_hsic_gpio" = "GPIO_E10" end

1 0

New patch to review for coreboot: e23f618 Exynos5250: Initialize USB PHY
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3696 -gerrit commit e23f618c3b1a0aac90a275feefff75286c56bc76 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 17 11:52:45 2013 -0700 Exynos5250: Initialize USB PHY ... this is needed for libpayload to talk to USB devices. Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 1 + src/cpu/samsung/exynos5250/chip.h | 5 ++ src/cpu/samsung/exynos5250/cpu.c | 14 ++++- src/cpu/samsung/exynos5250/usb.c | 105 ++++++++++++++++++++++++++++++++ src/cpu/samsung/exynos5250/usb.h | 62 +++++++++++++++++++ src/mainboard/google/snow/devicetree.cb | 2 + 6 files changed, 186 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e4e373c..73fd3c5 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c +ramstage-y += usb.c exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h index 798cd26..f244379 100644 --- a/src/cpu/samsung/exynos5250/chip.h +++ b/src/cpu/samsung/exynos5250/chip.h @@ -20,6 +20,8 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_H #define CPU_SAMSUNG_EXYNOS5250_H +#include "gpio.h" + struct cpu_samsung_exynos5250_config { /* special magic numbers! */ int clkval_f; @@ -34,6 +36,9 @@ struct cpu_samsung_exynos5250_config { int yres; int bpp; + int usb_vbus_gpio; + int usb_hsic_gpio; + u32 lcdbase; }; diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 3687ea8..96e7dc3 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -29,6 +29,7 @@ #include "dp-core.h" #include "cpu.h" #include "clk.h" +#include "usb.h" #include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) @@ -119,15 +120,22 @@ static void exynos_displayport_init(device_t dev) ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_init(device_t dev) +static void cpu_enable(device_t dev) { exynos_displayport_init(dev); + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); set_cpu_id(); +} + +static void cpu_init(device_t dev) +{ printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); + + usb_init(dev); } static void cpu_noop(device_t dev) @@ -137,8 +145,8 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, .set_resources = cpu_noop, - .enable_resources = cpu_init, - .init = cpu_noop, + .enable_resources = cpu_enable, + .init = cpu_init, .scan_bus = 0, }; diff --git a/src/cpu/samsung/exynos5250/usb.c b/src/cpu/samsung/exynos5250/usb.c new file mode 100644 index 0000000..d8e07da --- /dev/null +++ b/src/cpu/samsung/exynos5250/usb.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include "gpio.h" +#include "power.h" +#include "cpu.h" +#include "usb.h" +#include "chip.h" + +/* Enable VBUS */ +static int usb_vbus_init(int vbus_gpio) +{ + /* Enable VBUS power switch */ + gpio_direction_output(GPIO_X11, 1); + /* VBUS turn ON time */ + mdelay(3); + + return 0; +} + +/* Setup the EHCI host controller. */ + +static void setup_usb_phy(struct usb_phy *usb, int hsic_gpio) +{ + unsigned int hostphy_ctrl0; + + power_enable_usb_phy(); + + /* Setting up host and device simultaneously */ + hostphy_ctrl0 = readl(&usb->usbphyctrl0); + hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | + /* HOST Phy setting */ + HOST_CTRL0_PHYSWRST | + HOST_CTRL0_PHYSWRSTALL | + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESUSPEND | + HOST_CTRL0_FORCESLEEP); + hostphy_ctrl0 |= ( /* Setting up the ref freq */ + CLK_24MHZ << 16 | + /* HOST Phy setting */ + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); + writel(hostphy_ctrl0, &usb->usbphyctrl0); + udelay(10); + clrbits_le32(&usb->usbphyctrl0, + HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); + udelay(20); + + /* EHCI Ctrl setting */ + setbits_le32(&usb->ehcictrl, + EHCICTRL_ENAINCRXALIGN | + EHCICTRL_ENAINCR4 | + EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16); + + /* HSIC USB Hub initialization. */ + // FIXME board specific? + gpio_direction_output(hsic_gpio, 0); + udelay(100); + gpio_direction_output(hsic_gpio, 1); + udelay(5000); + + clrbits_le32(&usb->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST); + udelay(10); + clrbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST); + + /* PHY clock and power setup time */ + // FIXME If this happens more than 50ms before executing the payload, + // we might not need this delay. + mdelay(50); +} + +void usb_init(device_t dev) +{ + struct usb_phy *usb; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + + usb_vbus_init(conf->usb_vbus_gpio); + usb = (struct usb_phy *) samsung_get_base_usb_phy(); + setup_usb_phy(usb, conf->usb_hsic_gpio); +} diff --git a/src/cpu/samsung/exynos5250/usb.h b/src/cpu/samsung/exynos5250/usb.h new file mode 100644 index 0000000..45a7b53 --- /dev/null +++ b/src/cpu/samsung/exynos5250/usb.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_USB_H +#define CPU_SAMSUNG_EXYNOS5250_USB_H + +#define CLK_24MHZ 5 + +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) + +#define HOST_CTRL0_FSEL_MASK (7 << 16) + +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) + +/* Register map for PHY control */ +struct usb_phy { + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; +}; + +void usb_init(device_t dev); + +#endif diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index c14f374..34aa4e6 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -30,4 +30,6 @@ chip cpu/samsung/exynos5250 register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" + register "usb_vbus_gpio" = "GPIO_X11" + register "usb_hsic_gpio" = "GPIO_E10" end

1 0

New patch to review for coreboot: 08a9bab Exynos: Only compile UART in if serial console is selected
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3695 -gerrit commit 08a9bab0dd839139a39031a822d4f94fc26b5ed6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:51:04 2013 -0700 Exynos: Only compile UART in if serial console is selected Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 4 ++++ src/cpu/samsung/exynos5420/Makefile.inc | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 663f532..e4e373c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,9 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +endif bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c @@ -24,7 +26,9 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +endif romstage-y += wakeup.c romstage-y += pwm.c # needed by timer.c romstage-y += gpio.c diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 1dddd21..6f9b91b 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,9 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +endif bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c @@ -24,7 +26,9 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +endif romstage-y += wakeup.c romstage-y += pwm.c # needed by timer.c romstage-y += gpio.c

1 0

New patch to review for coreboot: ac8ea3d Don't try to use CBMEM console in bootblock
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3694 -gerrit commit ac8ea3d7656198bfe3dd0a88de4361aa444c27c9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:44:36 2013 -0700 Don't try to use CBMEM console in bootblock Otherwise we have to worry about hand off between bootblock and romstage. Too much complexity Change-Id: I89bf8a229dba7e1330accadf9a732d831ebc4827 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/early_console.c | 2 +- src/console/console.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 68e81c6..84f97ba 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -41,7 +41,7 @@ void console_tx_byte(unsigned char byte) #if CONFIG_USBDEBUG usbdebug_tx_byte(0, byte); #endif -#if CONFIG_CONSOLE_CBMEM +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) cbmemc_tx_byte(byte); #endif } diff --git a/src/console/console.c b/src/console/console.c index c53adc6..a0e8f6d 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -117,7 +117,7 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) cbmemc_init(); #endif #if CONFIG_SPKMODEM

1 0

New patch to review for coreboot: 45dfe23 Exynos5420: add code to make sure resume will work on DRAM.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3693 -gerrit commit 45dfe231642ca2b5069a9e2018106266d50621f3 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Wed Jun 19 15:46:25 2013 -0700 Exynos5420: add code to make sure resume will work on DRAM. Found during a perusal of u-boot changes. It looks important. For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commi… Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/bootblock.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index d3d737e..5cc9ef6 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -19,10 +19,28 @@ #include "clk.h" #include "wakeup.h" +#include "cpu.h" void bootblock_cpu_init(void); void bootblock_cpu_init(void) { + u32 ret; + /* + * During Suspend-Resume & S/W-Reset, as soon as PMU releases + * pad retention, CKE goes high. This causes memory contents + * not to be retained during DRAM initialization. Therfore, + * there is a new control register(0x100431e8[28]) which lets us + * release pad retention and retain the memory content until the + * initialization is complete. + */ + if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) { + write32(PAD_RETENTION_DRAM_COREBLK_VAL, + (void *)PAD_RETENTION_DRAM_COREBLK_OPTION); + do { + ret = read32((void *)PAD_RETENTION_DRAM_STATUS); + } while (ret != 0x1); + } + /* kick off the multi-core timer. * We want to do this as early as we can. */

1 0

New patch to review for coreboot: e077a69 ARMv7: Drop duplicate call to bootblock_cpu_init()
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3692 -gerrit commit e077a6947c503725ae5039853d1119800b70d2f3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 12 17:07:05 2013 -0700 ARMv7: Drop duplicate call to bootblock_cpu_init() This is already called in ARMv7 bootblock_simple.c so we don't want to do it twice Change-Id: I80cb41035b8a77787e04f2ea58a1cd372cea97d8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/include/bootblock_common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/armv7/include/bootblock_common.h index 39af453..2fa705f 100644 --- a/src/arch/armv7/include/bootblock_common.h +++ b/src/arch/armv7/include/bootblock_common.h @@ -7,8 +7,5 @@ #else static void bootblock_mainboard_init(void) { -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif } #endif

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2013