coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: d005e7e i2c: Change the type of the data parameter to uint8_t.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3721 -gerrit commit d005e7eddb81584d7949c7c779058b1b37f84a24 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 30 03:47:33 2013 -0700 i2c: Change the type of the data parameter to uint8_t. Data is intended to be a byte array, so it should be described by a type which has a fixed size equal to an 8 bit byte. Also, the data passed to write shouldn't be modified and can be const. Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/i2c.c | 6 +++--- src/cpu/samsung/exynos5420/i2c.c | 13 +++++++------ src/include/device/i2c.h | 6 ++++-- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/cpu/samsung/exynos5250/i2c.c b/src/cpu/samsung/exynos5250/i2c.c index 723cee6..e83ab57 100644 --- a/src/cpu/samsung/exynos5250/i2c.c +++ b/src/cpu/samsung/exynos5250/i2c.c @@ -347,7 +347,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, } int i2c_read(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -376,7 +376,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, } int i2c_write(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, const uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -397,7 +397,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, i2c = &i2c_buses[bus]; ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], - alen, buf, len); + alen, (void *)buf, len); return ret != 0; } diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index acb5bcf..2268628 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -408,7 +408,8 @@ static int hsi2c_wait_for_transfer(struct exynos5_hsi2c *i2c) return 0; } -static int hsi2c_senddata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) +static int hsi2c_senddata(struct exynos5_hsi2c *i2c, const uint8_t *data, + int len) { while (!hsi2c_check_transfer(i2c) && len) { if (!(read32(&i2c->usi_fifo_stat) & HSI2C_TX_FIFO_FULL)) { @@ -434,7 +435,7 @@ static int hsi2c_write(struct exynos5_hsi2c *i2c, unsigned char chip, unsigned char addr[], unsigned char alen, - unsigned char data[], + const uint8_t data[], unsigned short len) { uint32_t i2c_auto_conf; @@ -470,7 +471,7 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, unsigned char chip, unsigned char addr[], unsigned char alen, - unsigned char data[], + uint8_t data[], unsigned short len, int check) { @@ -632,7 +633,7 @@ bailout: } int i2c_read(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -667,7 +668,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, } int i2c_write(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, const uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -692,7 +693,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, alen, buf, len); else ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, - &xaddr[4 - alen], alen, buf, len); + &xaddr[4 - alen], alen, (void *)buf, len); if (ret != 0) { diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index d880a7b..997d201 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -20,10 +20,12 @@ #ifndef _DEVICE_I2C_H_ #define _DEVICE_I2C_H_ +#include <stdint.h> + /* note: chip is the 7-bit I2C address */ int i2c_read(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len); + unsigned alen, uint8_t *buf, unsigned len); int i2c_write(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len); + unsigned alen, const uint8_t *buf, unsigned len); #endif /* _DEVICE_I2C_H_ */

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New patch to review for coreboot: f04413a pit: Stop setting up the hardware dp hotplug detect in ROM stage too.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3720 -gerrit commit f04413a1c2d04c2a71fff6afd21479bbac65557a Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 30 03:37:24 2013 -0700 pit: Stop setting up the hardware dp hotplug detect in ROM stage too. This was removed from ramstage a little while ago and should have been removed from here as well. Change-Id: I6a40ed4a98bedac39e5492e4b1aed3427ab4e08b Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/romstage.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index f123253..a757615 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -135,11 +135,6 @@ static void setup_ec(void) exynos_pinmux_spi2(); } -static void setup_graphics(void) -{ - exynos_pinmux_dphpd(); -} - static void setup_gpio(void) { gpio_direction_input(GPIO_X30); // WP_GPIO @@ -280,7 +275,6 @@ void main(void) setup_storage(); setup_gpio(); - setup_graphics(); setup_ec(); simple_spi_test();

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New patch to review for coreboot: e2ffc46 PIT: add panel to the list of things to be powered up by the PMIC
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3719 -gerrit commit e2ffc46e28b3235a7bf5636e2ed5ac8a99d0e2fd Author: Ronald G. Minnich <rminnich(a)google.com> Date: Wed Jun 26 17:28:52 2013 -0700 PIT: add panel to the list of things to be powered up by the PMIC This appears to be needed, though we have no way to test yet. Change-Id: I39033581011e056258193f2cdff78814361a8d55 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 30c8aeb..f123253 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -71,7 +71,8 @@ struct pmic_write pmic_writes[] = MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | - MAX77802_BUCK_TYPE1_IGNORE_PWRREQ } + MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, + { 1, MAX77802_REG_PMIC_LDO35CTRL1, MAX77802_LDO35CTRL1_1_2V }, }; static void setup_power(int is_resume)

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New patch to review for coreboot: d9a33f0 armv7/exynos: Prevent unexpected reboots in resume.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3718 -gerrit commit d9a33f01ebfb31b0eeee50060e332bc5179c2eb7 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Jun 28 17:27:17 2013 +0800 armv7/exynos: Prevent unexpected reboots in resume. In resume path, if memory setup takes too long without setting PS_HOLD, EC watch dog may power off or reboot the system. To prevent that, we should enable PS_HOLD in same timing as cold boot - right before starting memory setup. Change-Id: I5c294fa7ae015f8cff57b1fd81e5b80902647b15 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/romstage.c | 11 ++++++----- src/mainboard/google/snow/romstage.c | 11 ++++++----- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 7ba66a4..30c8aeb 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -74,13 +74,17 @@ struct pmic_write pmic_writes[] = MAX77802_BUCK_TYPE1_IGNORE_PWRREQ } }; -static void setup_power(void) +static void setup_power(int is_resume) { int error = 0; int i; power_init(); + if (is_resume) { + return; + } + /* Initialize I2C bus to configure PMIC. */ exynos_pinmux_i2c4(); i2c_init(4, I2C_4_SPEED, 0x00); @@ -264,10 +268,7 @@ void main(void) console_init(); - if (!is_resume) { - setup_power(); - } - + setup_power(is_resume); setup_memory(&mem_timings, is_resume); primitive_mem_test(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 8c01536..7442f7a 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -43,12 +43,16 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -static void setup_power(void) +static void setup_power(int is_resume) { int error = 0; power_init(); + if (is_resume) { + return; + } + /* Initialize I2C bus to configure PMIC. */ exynos_pinmux_i2c0(); i2c_init(0, I2C_0_SPEED, 0x00); @@ -171,10 +175,7 @@ void main(void) console_init(); - if (!is_resume) { - setup_power(); - } - + setup_power(is_resume); setup_memory(mem, is_resume); if (is_resume) {

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New patch to review for coreboot: a69a341 pit: Replace the tps65090 functions and adjust the hotplug detect line.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3717 -gerrit commit a69a341d1c9905145921bb8e258270b2def57e7c Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jun 28 14:27:16 2013 -0700 pit: Replace the tps65090 functions and adjust the hotplug detect line. The functions which manipulated the tps65090 were removed a while ago because it isn't accessible directly from the AP, it's on an I2C bus that has to be accessed by the EC on our behalf. Now that that capability has been added, we can rewrite the small portion of the the tps65090 we actually used but using the EC passthrough commands. Also, we should not be configuring the hardware display port hotplug detect line since we're using it as a GPIO for other purposes. The GPIO we're using instead defaults to being an input, but to be safe we should probably explicitly configure it as one anyway. Change-Id: I7f8a8a767e3cccb813513940a5feceea482982f5 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/mainboard.c | 39 ++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 64783ad..67d3b5d 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -34,6 +34,7 @@ #include <cpu/samsung/exynos5420/power.h> #include <cpu/samsung/exynos5420/i2c.h> #include <cpu/samsung/exynos5420/dp-core.h> +#include <ec/google/chromeec/ec.h> #include "exynos5420.h" @@ -57,8 +58,6 @@ static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ static void exynos_dp_bridge_setup(void) { - exynos_pinmux_dphpd(); - gpio_set_value(dp_pd_l, 1); gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); @@ -68,6 +67,8 @@ static void exynos_dp_bridge_setup(void) gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); udelay(10); gpio_set_value(dp_rst_l, 1); + + gpio_cfg_pin(dp_hpd, GPIO_INPUT); } static void exynos_dp_bridge_init(void) @@ -170,6 +171,35 @@ static void gpio_init(void) exynos_pinmux_i2c10(); } +enum { + FET_CTRL_WAIT = 3 << 2, + FET_CTRL_ADENFET = 1 << 1, + FET_CTRL_ENFET = 1 << 0 +}; + +static void tps65090_thru_ec_fet_set(int index) +{ + uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET; + + if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { + printk(BIOS_ERR, + "Error sending i2c pass through command to EC.\n"); + return; + } +} + +static void lcd_vdd(void) +{ + /* Enable FET6, lcd panel */ + tps65090_thru_ec_fet_set(6); +} + +static void backlight_vdd(void) +{ + /* Enable FET1, backlight */ + tps65090_thru_ec_fet_set(1); +} + /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { @@ -193,7 +223,7 @@ static void mainboard_init(device_t dev) fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); - // XXX Turn on the LCD power here. + lcd_vdd(); // FIXME: should timeout do { @@ -204,6 +234,7 @@ static void mainboard_init(device_t dev) for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { + printk(BIOS_ERR, "Hotplug detect failed.\n"); exynos_dp_reset(); continue; } @@ -213,7 +244,7 @@ static void mainboard_init(device_t dev) udelay(LCD_T3_DELAY_MS * 1000); - // XXX Turn on the backlight power here. + backlight_vdd(); backlight_pwm(); backlight_en(); /* if we're here, we're successful */

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New patch to review for coreboot: adfb22c armv7/pit: Correct EC device in mainboard configuration.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3716 -gerrit commit adfb22c7e17ba4e1c056b3c0762b17579fa24b8a Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 19:48:43 2013 +0800 armv7/pit: Correct EC device in mainboard configuration. The ChromeOS EC for peach_pit is connected to SPI2 bus, not I2C. Change-Id: Ifeb8a626aa4fc3d3a181a7bc016e3f91be948ae5 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index 4148101..20e0084 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_SAMSUNG_EXYNOS5420 select HAVE_UART_MEMORY_MAPPED select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_I2C + select EC_GOOGLE_CHROMEEC_SPI select BOARD_ROMSIZE_KB_4096 select CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT @@ -44,8 +44,8 @@ config DRAM_SIZE_MB int default 2048 -config EC_GOOGLE_CHROMEEC_I2C_BUS +config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 4 + default 2 endif # BOARD_GOOGLE_PIT

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New patch to review for coreboot: edcb779 armv7/exynos5420: Remove the extra reopen when reading SPI.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3715 -gerrit commit edcb779f5c9fb2ab3dd42dcb04705fdca251b199 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 21:22:55 2013 +0800 armv7/exynos5420: Remove the extra reopen when reading SPI. The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be removed now. Change-Id: I6b1bf717c916903999a137998a578b0a866829bd Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 906f6a7..1c60378 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -364,9 +364,6 @@ static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest, int bytes; DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count); bytes = exynos_spi_read(spi->slave, dest, count, offset); - // Flush and re-open the device. - spi_release_bus(spi->slave); - spi_claim_bus(spi->slave); return bytes; }

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New patch to review for coreboot: 8664af0 armv7/exynos5420: Apply new implementation for SPI transmission.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3714 -gerrit commit 8664af0481076a7889eb7a2bd5423cb013255cdf Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:31:22 2013 +0800 armv7/exynos5420: Apply new implementation for SPI transmission. Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 115 +++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 59 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index dddbec5..906f6a7 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -153,10 +153,8 @@ static void exynos_spi_request_bytes(struct exynos_spi *regs, int count, } } -int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, - const uint8_t *txp, int tx_bytes); -int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, - const uint8_t *txp, int tx_bytes) +static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, + const uint8_t *txp, int tx_bytes) { struct exynos_spi_slave *espi = to_exynos_spi(slave); struct exynos_spi *regs = espi->regs; @@ -237,46 +235,6 @@ int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, return 0; } -static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, - void *dinp, void const *doutp, int i) -{ - int rx_lvl, tx_lvl; - unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); - unsigned int out_bytes, in_bytes; - - // TODO In currrent implementation, every read/write must be aligned to - // 4 bytes, otherwise you may get timeout or other unexpected results. - ASSERT(todo % 4 == 0); - - out_bytes = in_bytes = todo; - exynos_spi_soft_reset(regs); - writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); - - while (in_bytes) { - uint32_t spi_sts; - int temp; - - spi_sts = readl(&regs->spi_sts); - rx_lvl = ((spi_sts >> 15) & 0x7f); - tx_lvl = ((spi_sts >> 6) & 0x7f); - while (tx_lvl < 32 && out_bytes) { - // TODO The "writing" (tx) is not supported now; that's - // why we write garbage to keep driving FIFO clock. - temp = 0xffffffff; - writel(temp, &regs->tx_data); - out_bytes -= 4; - tx_lvl += 4; - } - while (rx_lvl >= 4 && in_bytes) { - temp = readl(&regs->rx_data); - if (rxp) - *rxp++ = temp; - in_bytes -= 4; - rx_lvl -= 4; - } - } -} - int spi_claim_bus(struct spi_slave *slave) { struct exynos_spi_slave *espi = to_exynos_spi(slave); @@ -304,32 +262,70 @@ int spi_claim_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { - // TODO(hungte) Invoke exynos_spi_rx_tx to transfer data. - return -1; + unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; + uint8_t *out_ptr = (uint8_t *)dout, *in_ptr = (uint8_t *)din; + int offset, todo, len; + int ret = 0; + + ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); + len = MAX(out_bytes, in_bytes); + + /* + * Exynos SPI limits each transfer to (2^16-1=65535) bytes. To keep + * things simple (especially for word-width transfer mode), allow a + * maximum of (2^16-4=65532) bytes. We could allow more in word mode, + * but the performance difference is small. + */ + spi_cs_activate(slave); + for (offset = 0; !ret && (offset < len); offset += todo) { + todo = min(len - offset, (1 << 16) - 4); + ret = spi_rx_tx(slave, in_ptr, MIN(in_bytes, todo), out_ptr, + MIN(out_bytes, todo)); + // Adjust remaining bytes and pointers. + if (in_bytes >= todo) { + in_bytes -= todo; + in_ptr += todo; + } else { + in_bytes = 0; + in_ptr = NULL; + } + if (out_bytes >= todo) { + out_bytes -= todo; + out_ptr += todo; + } else { + out_bytes = 0; + out_ptr = NULL; + } + } + spi_cs_deactivate(slave); + + return ret; } static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, uint32_t off) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - int upto, todo; - int i; - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + int rv; - /* Send read instruction (0x3h) followed by a 24 bit addr */ - writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data); + // TODO(hungte) Merge the "read address" command into spi_xfer calls + // (full-duplex mode). - /* waiting for TX done */ - while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)); + spi_cs_activate(slave); - for (upto = 0, i = 0; upto < len; upto += todo, i++) { - todo = MIN(len - upto, (1 << 15)); - exynos_spi_rx_tx(regs, todo, dest, (void *)(off), i); + // Specify read address (in word-width mode). + ASSERT(off < (1 << 24)); + exynos_spi_request_bytes(regs, sizeof(off), sizeof(off)); + writel(htonl((SF_READ_DATA_CMD << 24) | off), &regs->tx_data); + while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) { + /* Wait for TX done */ } - setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + // Now, safe to transfer. + rv = spi_xfer(slave, NULL, 0, dest, len * 8); + spi_cs_deactivate(slave); - return len; + return (rv == 0) ? len : -1; } void spi_release_bus(struct spi_slave *slave) @@ -378,7 +374,8 @@ static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset, size_t count) { struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_map\n"); - // See exynos_spi_rx_tx for I/O alignment limitation. + // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and + // requires buffer memory address to be aligned. if (count % 4) count += 4 - (count % 4); return cbfs_simple_buffer_map(&spi->buffer, media, offset, count);

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New patch to review for coreboot: 8ad601e armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3713 -gerrit commit 8ad601ea1794c51af71d57fd59b070892b9725c4 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:29:06 2013 +0800 armv7/exynos5420: Add output ability and half-duplex mode in SPI driver. The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and only full-duplex mode. To communicate with devices like ChromeOS EC, we need both output (tx) and half-duplex (searching frame header) features. This commit adds a spi_rx_tx that can handle all cases we need. Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 115 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 6637aad..dddbec5 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -27,6 +27,8 @@ #include "cpu.h" #include "spi.h" +#define EXYNOS_SPI_MAX_TRANSFER_BYTES (65535) + #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "EXYNOS_SPI: " x) #else @@ -122,6 +124,119 @@ static inline void exynos_spi_flush_fifo(struct exynos_spi *regs) setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); } +static void exynos_spi_request_bytes(struct exynos_spi *regs, int count, + int width) +{ + uint32_t mode_word = SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD, + swap_word = (SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | + SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | + SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); + + /* For word address we need to swap bytes */ + if (width == sizeof(uint32_t)) { + setbits_le32(&regs->mode_cfg, mode_word); + setbits_le32(&regs->swap_cfg, swap_word); + count /= width; + } else { + /* Select byte access and clear the swap configuration */ + clrbits_le32(&regs->mode_cfg, mode_word); + writel(0, &regs->swap_cfg); + } + + exynos_spi_soft_reset(regs); + + if (count) { + ASSERT(count < (1 << 16)); + writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt); + } else { + writel(0, &regs->pkt_cnt); + } +} + +int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, + const uint8_t *txp, int tx_bytes); +int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, + const uint8_t *txp, int tx_bytes) +{ + struct exynos_spi_slave *espi = to_exynos_spi(slave); + struct exynos_spi *regs = espi->regs; + + int step; + int todo = MAX(rx_bytes, tx_bytes); + int wait_for_frame_header = espi->half_duplex; + + ASSERT(todo < EXYNOS_SPI_MAX_TRANSFER_BYTES); + + /* Select transfer mode. */ + if (espi->half_duplex) { + step = 1; + } else if ((rx_bytes | tx_bytes | (uintptr_t)rxp |(uintptr_t)txp) & 3) { + printk(BIOS_CRIT, "%s: WARNING: tranfer mode decreased to 1B\n", + __func__); + step = 1; + } else { + step = sizeof(uint32_t); + } + + exynos_spi_request_bytes(regs, espi->half_duplex ? 0 : todo, step); + + /* Note: Some device, like ChromeOS EC, tries to work in half-duplex + * mode and sends a large amount of data (larger than FIFO size). + * Printing lots of debug messages or doing extra delay in the loop + * below may cause rx buffer to overflow and getting unexpected data + * error. + */ + while (rx_bytes || tx_bytes) { + int temp; + uint32_t spi_sts = readl(&regs->spi_sts); + int rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK, + tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; + int min_tx = ((tx_bytes || !espi->half_duplex) ? + (espi->fifo_size / 2) : 1); + + // TODO(hungte) Abort if timeout happens in half-duplex mode. + + /* + * Don't completely fill the txfifo, since we don't want our + * rxfifo to overflow, and it may already contain data. + */ + while (tx_lvl < min_tx) { + if (tx_bytes) { + if (step == sizeof(uint32_t)) { + temp = *((uint32_t *)txp); + txp += sizeof(uint32_t); + } else { + temp = *txp++; + } + tx_bytes -= step; + } else { + temp = -1; + } + writel(temp, &regs->tx_data); + tx_lvl += step; + } + + while ((rx_lvl >= step) && rx_bytes) { + temp = readl(&regs->rx_data); + rx_lvl -= step; + if (wait_for_frame_header) { + if ((temp & 0xff) == espi->frame_header) { + wait_for_frame_header = 0; + } + break; /* Restart the outer loop. */ + } + if (step == sizeof(uint32_t)) { + *((uint32_t *)rxp) = temp; + rxp += sizeof(uint32_t); + } else { + *rxp++ = temp; + } + rx_bytes -= step; + } + } + return 0; +} + static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) {

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New patch to review for coreboot: 6a2b17c armv7/exynos5420: Revise SPI open/close/reset procedure.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3712 -gerrit commit 6a2b17cd80ff4e0fe0cca23da17c1477fa349f7d Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:22:50 2013 +0800 armv7/exynos5420: Revise SPI open/close/reset procedure. The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 76 +++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 82c3765..6637aad 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -102,6 +102,26 @@ void spi_cs_deactivate(struct spi_slave *slave) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); } +static inline void exynos_spi_soft_reset(struct exynos_spi *regs) +{ + /* The soft reset clears only FIFO and status register. + * All special function registers are not changed. */ + setbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); +} + +static inline void exynos_spi_flush_fifo(struct exynos_spi *regs) +{ + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits_le32(&regs->ch_cfg, SPI_CH_HS_EN); + exynos_spi_soft_reset(regs); + setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); +} + static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) { @@ -114,8 +134,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, ASSERT(todo % 4 == 0); out_bytes = in_bytes = todo; - setbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + exynos_spi_soft_reset(regs); writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); while (in_bytes) { @@ -143,35 +162,27 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, } } -/* set up SPI channel */ int spi_claim_bus(struct spi_slave *slave) { struct exynos_spi_slave *espi = to_exynos_spi(slave); struct exynos_spi *regs = espi->regs; - /* set the spi1 GPIO */ + exynos_spi_flush_fifo(regs); - /* set pktcnt and enable it */ - writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt); - /* set FB_CLK_SEL */ - writel(SPI_FB_DELAY_180, &regs->fb_clk); - /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(&regs->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + // Select Active High Clock, Format A (SCP 30.2.1.8). + clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L | SPI_CH_CPHA_B); - /* clear rx and tx channel if set priveously */ - clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - - setbits_le32(&regs->swap_cfg, - SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); - - /* do a soft reset */ - setbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + // Set FeedBack Clock Selection. + writel(SPI_FB_DELAY_180, &regs->fb_clk); - /* now set rx and tx channel ON */ - setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + // HIGH speed is required for Tx/Rx to work in 50MHz (SCP 30.2.1.6). + if (espi->half_duplex) { + clrbits_le32(&regs->ch_cfg, SPI_CH_HS_EN); + printk(BIOS_DEBUG, "%s: LOW speed.\n", __func__); + } else { + setbits_le32(&regs->ch_cfg, SPI_CH_HS_EN); + printk(BIOS_DEBUG, "%s: HIGH speed.\n", __func__); + } return 0; } @@ -209,21 +220,12 @@ static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, void spi_release_bus(struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - /* - * Let put controller mode to BYTE as - * SPI driver does not support WORD mode yet - */ - clrbits_le32(&regs->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + /* Reset swap mode to make sure no one relying on default values (Ex, + * payload or kernel) will go wrong. */ + clrbits_le32(&regs->mode_cfg, (SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD)); writel(0, &regs->swap_cfg); - - /* - * Flush spi tx, rx fifos and reset the SPI controller - * and clear rx/tx channel - */ - clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); + exynos_spi_flush_fifo(regs); } // SPI as CBFS media.

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coreboot-gerrit July 2013