coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: f7973ad armv7/exynos5420: Provide configuration for SPI0~SPI2.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3711 -gerrit commit f7973ad25de023b68af5bad8c948a327712ea39b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:17:42 2013 +0800 armv7/exynos5420: Provide configuration for SPI0~SPI2. Fill the SPI device parameters for spi_setup_slave on Exynos 5420. Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index e3029b8..82c3765 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -41,6 +41,32 @@ struct exynos_spi_slave { uint8_t frame_header; /* header byte to detect in half-duplex mode. */ }; +/* TODO(hungte) Move the SPI param list to per-board configuration, probably + * Kconfig or mainboard.c */ +static struct exynos_spi_slave exynos_spi_slaves[3] = { + // SPI 0 + { + .slave = { .bus = 0, }, + .regs = samsung_get_base_spi0(), + }, + // SPI 1 + { + .slave = { .bus = 1, .rw = SPI_READ_FLAG, }, + .regs = samsung_get_base_spi1(), + .fifo_size = 64, + .half_duplex = 0, + }, + // SPI 2 + { + .slave = { .bus = 2, + .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, + .regs = samsung_get_base_spi2(), + .fifo_size = 64, + .half_duplex = 1, + .frame_header = 0xec, + }, +}; + static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) { return container_of(slave, struct exynos_spi_slave, slave); @@ -54,14 +80,13 @@ void spi_init(void) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { - // TODO(hungte) Provide Exynos SPI device setup. - return NULL; + ASSERT(bus >= 0 && bus < 3); + return &(exynos_spi_slaves[bus].slave); } int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - // TODO(hungte) Detect and check if BUS/CS is valid. - return 0; + return bus > 0 && bus < 3; } void spi_cs_activate(struct spi_slave *slave)

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New patch to review for coreboot: 7486e1a armv7/exynos5420: Change SPI module to standard <spi-generic> interface.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3710 -gerrit commit 7486e1a729c0cf3307a3959614eb740a37dea903 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:16:13 2013 +0800 armv7/exynos5420: Change SPI module to standard <spi-generic> interface. The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard (spi-generic.h) and will be a problem when we want to share SPI drivers. This commit replaces exynos_spi_* by spi_* functions. Note, exynos_spi_read is kept and changed to a static function because its usage is different from the standard API "spi_xfer". Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 89 ++++++++++++++++++++++++++++++++++------ src/cpu/samsung/exynos5420/spi.h | 5 --- 2 files changed, 76 insertions(+), 18 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 35fccb2..e3029b8 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -22,17 +22,61 @@ #include <arch/io.h> #include <stdlib.h> #include <assert.h> +#include <spi_flash.h> +#include "cpu.h" #include "spi.h" -#define EXYNOS_BASE_SPI1 ((void *)0x12d30000) - #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "EXYNOS_SPI: " x) #else # define DEBUG_SPI(x,...) #endif +struct exynos_spi_slave { + struct spi_slave slave; + struct exynos_spi *regs; + unsigned int fifo_size; + uint8_t half_duplex; + uint8_t frame_header; /* header byte to detect in half-duplex mode. */ +}; + +static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) +{ + return container_of(slave, struct exynos_spi_slave, slave); +} + +void spi_init(void) +{ + printk(BIOS_INFO, "Exynos SPI driver initiated.\n"); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + // TODO(hungte) Provide Exynos SPI device setup. + return NULL; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + // TODO(hungte) Detect and check if BUS/CS is valid. + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct exynos_spi *regs = to_exynos_spi(slave)->regs; + // TODO(hungte) Add some delay if too many transactions happen at once. + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct exynos_spi *regs = to_exynos_spi(slave)->regs; + setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); +} + static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) { @@ -75,8 +119,11 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, } /* set up SPI channel */ -int exynos_spi_open(struct exynos_spi *regs) +int spi_claim_bus(struct spi_slave *slave) { + struct exynos_spi_slave *espi = to_exynos_spi(slave); + struct exynos_spi *regs = espi->regs; + /* set the spi1 GPIO */ /* set pktcnt and enable it */ @@ -103,8 +150,17 @@ int exynos_spi_open(struct exynos_spi *regs) return 0; } -int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, + void *din, unsigned int bitsin) +{ + // TODO(hungte) Invoke exynos_spi_rx_tx to transfer data. + return -1; +} + +static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, + uint32_t off) { + struct exynos_spi *regs = to_exynos_spi(slave)->regs; int upto, todo; int i; clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ @@ -125,8 +181,9 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) return len; } -int exynos_spi_close(struct exynos_spi *regs) +void spi_release_bus(struct spi_slave *slave) { + struct exynos_spi *regs = to_exynos_spi(slave)->regs; /* * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet @@ -142,25 +199,25 @@ int exynos_spi_close(struct exynos_spi *regs) clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); - return 0; } // SPI as CBFS media. struct exynos_spi_media { - struct exynos_spi *regs; + struct spi_slave *slave; struct cbfs_simple_buffer buffer; }; static int exynos_spi_cbfs_open(struct cbfs_media *media) { struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_open\n"); - return exynos_spi_open(spi->regs); + return spi_claim_bus(spi->slave); } static int exynos_spi_cbfs_close(struct cbfs_media *media) { struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_close\n"); - return exynos_spi_close(spi->regs); + spi_release_bus(spi->slave); + return 0; } static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest, @@ -168,10 +225,10 @@ static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest, struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; int bytes; DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count); - bytes = exynos_spi_read(spi->regs, dest, count, offset); + bytes = exynos_spi_read(spi->slave, dest, count, offset); // Flush and re-open the device. - exynos_spi_close(spi->regs); - exynos_spi_open(spi->regs); + spi_release_bus(spi->slave); + spi_claim_bus(spi->slave); return bytes; } @@ -197,9 +254,15 @@ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, size_t buffer_size) { // TODO Replace static variable to support multiple streams. static struct exynos_spi_media context; + static struct exynos_spi_slave eslave = { + .slave = { .bus = 1, .rw = SPI_READ_FLAG, }, + .regs = samsung_get_base_spi1(), + .fifo_size = 64, + .half_duplex = 0, + }; DEBUG_SPI("initialize_exynos_spi_cbfs_media\n"); - context.regs = EXYNOS_BASE_SPI1; + context.slave = &eslave.slave; context.buffer.allocated = context.buffer.last_allocate = 0; context.buffer.buffer = buffer_address; context.buffer.size = buffer_size; diff --git a/src/cpu/samsung/exynos5420/spi.h b/src/cpu/samsung/exynos5420/spi.h index faf82b0..94b4fda 100644 --- a/src/cpu/samsung/exynos5420/spi.h +++ b/src/cpu/samsung/exynos5420/spi.h @@ -86,11 +86,6 @@ struct exynos_spi { #define SPI_RX_BYTE_SWAP (1 << 6) #define SPI_RX_HWORD_SWAP (1 << 7) -/* API */ -int exynos_spi_open(struct exynos_spi *regs); -int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off); -int exynos_spi_close(struct exynos_spi *regs); - /* Serve as CBFS media source */ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, void *buffer_address,

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New patch to review for coreboot: d331dec armv7/exynos5420: Clean up unused header and constants in spi.c
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3709 -gerrit commit d331decd0eaea0a2fe57316d7f2d371a1aef5646 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:03:47 2013 +0800 armv7/exynos5420: Clean up unused header and constants in spi.c Remove unused header and constant definition in SPI module. Change-Id: I339e603f48186e4a356e83518b0d0b4c907f11b8 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 642ae23..35fccb2 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -22,11 +22,9 @@ #include <arch/io.h> #include <stdlib.h> #include <assert.h> -#include "gpio.h" -#include "clk.h" + #include "spi.h" -#define OM_STAT (0x1f << 1) #define EXYNOS_BASE_SPI1 ((void *)0x12d30000) #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI

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New patch to review for coreboot: 97d9bf5 armv7/exynos5420: Revise SPI device list in cpu.h
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3708 -gerrit commit 97d9bf5c4881622fb737dddc6c806fcca81f2dbc Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 19:52:52 2013 +0800 armv7/exynos5420: Revise SPI device list in cpu.h Add SPI0 and SPI2 to Exynos 5 SPI list, and correct structure names. Also removed the un-enumerated devices (SPI_BASE, base_spi()). Change-Id: Ica6d9a41f9619c8c61eab664d5e988dd4a428e09 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 7d0a5d5..251abea 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -66,9 +66,10 @@ #define EXYNOS5_SROMC_BASE 0x12250000 #define EXYNOS5_UART_BASE 0x12C00000 +#define EXYNOS5_SPI0_BASE 0x12D20000 #define EXYNOS5_SPI1_BASE 0x12D30000 +#define EXYNOS5_SPI2_BASE 0x12D40000 #define EXYNOS5_I2C_BASE 0x12C60000 -#define EXYNOS5_SPI_BASE 0x12D20000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 #define EXYNOS5_I2S_BASE 0x12D60000 @@ -191,9 +192,10 @@ #define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE) #define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE) #define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE) -#define samsung_get_base_spi1() ((struct exynos5_spi1 *)EXYNOS5_SPI1_BASE) +#define samsung_get_base_spi0() ((struct exynos_spi *)EXYNOS5_SPI0_BASE) +#define samsung_get_base_spi1() ((struct exynos_spi *)EXYNOS5_SPI1_BASE) +#define samsung_get_base_spi2() ((struct exynos_spi *)EXYNOS5_SPI2_BASE) #define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE) -#define samsung_get_base_spi() ((struct exynos5_spi *)EXYNOS5_SPI_BASE) #define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE) #define EXYNOS5_SPI_NUM_CONTROLLERS 5

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New patch to review for coreboot: f755ff5 armv7/pit: Setup EC on SPI2.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3707 -gerrit commit f755ff58db0ed3afc985678de09ba3911e655602 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jun 24 20:02:01 2013 +0800 armv7/pit: Setup EC on SPI2. The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 41b64b2..7ba66a4 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -122,6 +122,14 @@ static void setup_storage(void) exynos_pinmux_sdmmc2(); } +static void setup_ec(void) +{ + /* SPI2 (EC) is slower and needs to work in half-duplex mode with + * single byte bus width. */ + clock_set_rate(PERIPH_ID_SPI2, 500000); + exynos_pinmux_spi2(); +} + static void setup_graphics(void) { exynos_pinmux_dphpd(); @@ -271,6 +279,7 @@ void main(void) setup_storage(); setup_gpio(); setup_graphics(); + setup_ec(); simple_spi_test(); /* Set SPI (primary CBFS media) clock to 50MHz. */

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New patch to review for coreboot: a619a3a arm/exynos: Correct SPI session commands.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3706 -gerrit commit a619a3a4c9cc9216fdcbe76be9da4dcaba95cab6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sun Jun 23 08:14:30 2013 +0800 arm/exynos: Correct SPI session commands. Some initialization / shutdown commands should be paired correctly in a SPI I/O session. For example, setting CS should be enabled and disabled in each read; and the bus width (byte or word) should be configured only when opening / closing the SPI device. Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/spi.c | 13 +++++++------ src/cpu/samsung/exynos5420/spi.c | 13 +++++++------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c index 503cee9..642ae23 100644 --- a/src/cpu/samsung/exynos5250/spi.c +++ b/src/cpu/samsung/exynos5250/spi.c @@ -102,7 +102,6 @@ int exynos_spi_open(struct exynos_spi *regs) /* now set rx and tx channel ON */ setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ return 0; } @@ -110,6 +109,8 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + /* Send read instruction (0x3h) followed by a 24 bit addr */ writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data); @@ -123,6 +124,11 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + return len; +} + +int exynos_spi_close(struct exynos_spi *regs) +{ /* * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet @@ -131,11 +137,6 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); writel(0, &regs->swap_cfg); - return len; -} - -int exynos_spi_close(struct exynos_spi *regs) -{ /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 503cee9..642ae23 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -102,7 +102,6 @@ int exynos_spi_open(struct exynos_spi *regs) /* now set rx and tx channel ON */ setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ return 0; } @@ -110,6 +109,8 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + /* Send read instruction (0x3h) followed by a 24 bit addr */ writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data); @@ -123,6 +124,11 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + return len; +} + +int exynos_spi_close(struct exynos_spi *regs) +{ /* * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet @@ -131,11 +137,6 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); writel(0, &regs->swap_cfg); - return len; -} - -int exynos_spi_close(struct exynos_spi *regs) -{ /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel

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New patch to review for coreboot: 44bb4d5 pit: update I2C4 speed constant
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3705 -gerrit commit 44bb4d5a9fc2304012c0567afcc65784b7a10a33 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 22 19:42:15 2013 -0700 pit: update I2C4 speed constant Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/exynos5420.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/pit/exynos5420.h b/src/mainboard/google/pit/exynos5420.h index 562d9bc..21b704c 100644 --- a/src/mainboard/google/pit/exynos5420.h +++ b/src/mainboard/google/pit/exynos5420.h @@ -19,7 +19,7 @@ /* I2C */ #define I2C_0_SPEED 100000 -#define I2C_4_SPEED 100000 +#define I2C_4_SPEED 1000000 /* 1MHz */ #define I2C_SLAVE 0 /* Voltages */

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New patch to review for coreboot: 92a5dd8 exynos5420: i2c: Fix error handling.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3704 -gerrit commit 92a5dd84a3c163147390126e75e2b5cd9b2fbca2 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Jun 24 03:20:22 2013 -0700 exynos5420: i2c: Fix error handling. The functions which checked the status of a transfer would return success if the bus was no longer occupied, even if it's no longer occupied because the transfer failed. This change modifies those functions to return three possible values, 0 if the transfer isn't done, -1 if there was a fault, and 1 if the transaction completed successfully. Change-Id: Idcc5fdf73cab3c3ece0e96f14113a216db289e05 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/i2c.c | 55 ++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index b16d068..acb5bcf 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -357,23 +357,39 @@ void i2c_init(unsigned bus_num, int speed, int slaveadd) /* * Check whether the transfer is complete. + * Return values: + * 0 - transfer not done + * 1 - transfer finished successfully + * -1 - transfer failed */ static int hsi2c_check_transfer(struct exynos5_hsi2c *i2c) { uint32_t status = read32(&i2c->usi_trans_status); - if (status & HSI2C_TRANS_ABORT) - printk(BIOS_ERR, "%s: Transaction aborted.\n", __func__); - if (status & HSI2C_NO_DEV_ACK) - printk(BIOS_ERR, "%s: No ack from device.\n", __func__); - if (status & HSI2C_NO_DEV) - printk(BIOS_ERR, "%s: No response from device.\n", __func__); - if (status & HSI2C_TIMEOUT_AUTO) - printk(BIOS_ERR, "%s: Transaction time out.\n", __func__); - return !!(status & HSI2C_MASTER_BUSY); + if (status & (HSI2C_TRANS_ABORT | HSI2C_NO_DEV_ACK | + HSI2C_NO_DEV | HSI2C_TIMEOUT_AUTO)) { + if (status & HSI2C_TRANS_ABORT) + printk(BIOS_ERR, + "%s: Transaction aborted.\n", __func__); + if (status & HSI2C_NO_DEV_ACK) + printk(BIOS_ERR, + "%s: No ack from device.\n", __func__); + if (status & HSI2C_NO_DEV) + printk(BIOS_ERR, + "%s: No response from device.\n", __func__); + if (status & HSI2C_TIMEOUT_AUTO) + printk(BIOS_ERR, + "%s: Transaction time out.\n", __func__); + return -1; + } + return !(status & HSI2C_MASTER_BUSY); } /* * Wait for the transfer to finish. + * Return values: + * 0 - transfer not done + * 1 - transfer finished successfully + * -1 - transfer failed */ static int hsi2c_wait_for_transfer(struct exynos5_hsi2c *i2c) { @@ -383,17 +399,18 @@ static int hsi2c_wait_for_transfer(struct exynos5_hsi2c *i2c) end = current; mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000); while (mono_time_before(&current, &end)) { - if (!hsi2c_check_transfer(i2c)) - return 0; + int ret = hsi2c_check_transfer(i2c); + if (ret) + return ret; udelay(5); timer_monotonic_get(&current); } - return 1; + return 0; } static int hsi2c_senddata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) { - while (hsi2c_check_transfer(i2c) && len) { + while (!hsi2c_check_transfer(i2c) && len) { if (!(read32(&i2c->usi_fifo_stat) & HSI2C_TX_FIFO_FULL)) { write32(*data++, &i2c->usi_txdata); len--; @@ -404,7 +421,7 @@ static int hsi2c_senddata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) static int hsi2c_recvdata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) { - while (hsi2c_check_transfer(i2c) && len) { + while (!hsi2c_check_transfer(i2c) && len) { if (!(read32(&i2c->usi_fifo_stat) & HSI2C_RX_FIFO_EMPTY)) { *data++ = read32(&i2c->usi_rxdata); len--; @@ -422,7 +439,7 @@ static int hsi2c_write(struct exynos5_hsi2c *i2c, { uint32_t i2c_auto_conf; - if (hsi2c_wait_for_transfer(i2c)) + if (hsi2c_wait_for_transfer(i2c) != 1) return -1; /* chip address */ @@ -441,7 +458,7 @@ static int hsi2c_write(struct exynos5_hsi2c *i2c, if (hsi2c_senddata(i2c, addr, alen) || hsi2c_senddata(i2c, data, len) || - hsi2c_wait_for_transfer(i2c)) { + hsi2c_wait_for_transfer(i2c) != 1) { return -1; } @@ -460,7 +477,7 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, uint32_t i2c_auto_conf; /* start read */ - if (hsi2c_wait_for_transfer(i2c)) + if (hsi2c_wait_for_transfer(i2c) != 1) return -1; /* chip address */ @@ -475,7 +492,7 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, &i2c->usi_auto_conf); if (hsi2c_senddata(i2c, addr, alen) || - hsi2c_wait_for_transfer(i2c)) { + hsi2c_wait_for_transfer(i2c) != 1) { return -1; } @@ -490,7 +507,7 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, write32(i2c_auto_conf, &i2c->usi_auto_conf); if (hsi2c_recvdata(i2c, data, len) || - hsi2c_wait_for_transfer(i2c)) { + hsi2c_wait_for_transfer(i2c) != 1) { return -1; }

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New patch to review for coreboot: dc097d6 exynos5420: Clock the mmc blocks off of the mpll.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3703 -gerrit commit dc097d6fe319c58d68de65aa6e252675098ac418 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Jun 24 03:14:41 2013 -0700 exynos5420: Clock the mmc blocks off of the mpll. The exynos manual suggests hooking the mmc ip blocks to the mpll. They had been set to use a different pll. This changes them over and modifies the divider so that the frequency stays the same. Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/setup.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 7d63772..e89ed8e 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -222,7 +222,7 @@ struct exynos5_phy_control; #define CLK_DIV_CPU0_VAL 0x01440020 /* CLK_SRC_TOP */ -#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP0_VAL 0x12222222 #define CLK_SRC_TOP1_VAL 0x00100200 #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 @@ -231,7 +231,7 @@ struct exynos5_phy_control; #define CLK_SRC_TOP7_VAL 0x00022200 /* CLK_DIV_TOP */ -#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP0_VAL 0x23713311 #define CLK_DIV_TOP1_VAL 0x13100B00 #define CLK_DIV_TOP2_VAL 0x11101100

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New patch to review for coreboot: ef19e80 pit: Configure the pinmux for the i2c busses that are connected on pit.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3702 -gerrit commit ef19e8015dea86043511e1788ba2468e155826ef Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 23 03:16:46 2013 -0700 pit: Configure the pinmux for the i2c busses that are connected on pit. Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/mainboard.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 1608788..64783ad 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -159,6 +159,17 @@ static void disable_usb30_pll(void) gpio_direction_output(usb3_pll_l, 0); } +static void gpio_init(void) +{ + /* Set up the I2C busses. */ + exynos_pinmux_i2c2(); + exynos_pinmux_i2c4(); + exynos_pinmux_i2c7(); + exynos_pinmux_i2c8(); + exynos_pinmux_i2c9(); + exynos_pinmux_i2c10(); +} + /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { @@ -169,6 +180,8 @@ static void mainboard_init(device_t dev) }; void *fb_addr; + gpio_init(); + tmu_init(&exynos5420_tmu_info); /* Clock Gating all the unused IP's to save power */

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coreboot-gerrit July 2013