coreboot-gerrit July 2013

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Patch set updated for coreboot: 84287e4 SMBIOS: Allow overriding default Manufacturer and Product names
by Peter Stuge 09 Jul '13

09 Jul '13

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1556 -gerrit commit 84287e42b9dfb0b744f10cb1abff3a9f77b93884 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:18:13 2012 +0200 SMBIOS: Allow overriding default Manufacturer and Product names The vendor and part name from coreboot is normally stored in these SMBIOS structure fields, but it can be useful to override them. On Lenovo ThinkPads an override is e.g. needed to convince the Linux thinkpad_acpi.c driver that it is actually running on a ThinkPad. Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/arch/x86/boot/smbios.c | 6 +++--- src/mainboard/Kconfig | 15 +++++++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 308336a..073c7c5 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -192,8 +192,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); len = t->length + smbios_string_table_len(t->eos); @@ -210,7 +210,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index d6413c9..a8cf362 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -347,4 +347,19 @@ config MAINBOARD_VERSION default "1.0" help Define the used version number which will be used by SMBIOS tables. + +config MAINBOARD_SMBIOS_MANUFACTURER + string "SMBIOS Manufacturer" + depends on GENERATE_SMBIOS_TABLES + default MAINBOARD_VENDOR + help + Override the default Manufacturer stored in SMBIOS structures. + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string "SMBIOS Product name" + depends on GENERATE_SMBIOS_TABLES + default MAINBOARD_PART_NUMBER + help + Override the default Product name stored in SMBIOS structures. + endmenu

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Patch set updated for coreboot: 1cf1b3c AMD Fam15tn: Split DSDT into common sections
by Steve Goodrich 09 Jul '13

09 Jul '13

Steve Goodrich (steve.goodrich(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3629 -gerrit commit 1cf1b3c1621a8182cfe2ebe3dc56deb582e7bc7c Author: Steve Goodrich <steve.goodrich(a)se-eng.com> Date: Wed Jul 3 15:57:44 2013 -0600 AMD Fam15tn: Split DSDT into common sections Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits the DSDT table into includable ASL files which carry details specific to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. Initially, this split was done by moving each piece of functionality into its own file (e.g. IRQ routing and mapping, processor tree, sleep states and sleep methods, etc.) and those pieces were #included in dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d) with the extant version of the table. Once the new tables were found to exactly match the existing tables, the pieces were rearranged into reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.). Some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl, sata.asl, etc.). Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710 Signed-off-by: Steve Goodrich <steve.goodrich(a)se-eng.com> --- src/cpu/amd/agesa/family15tn/acpi/cpu.asl | 83 ++ src/mainboard/amd/parmer/acpi/gpe.asl | 80 ++ src/mainboard/amd/parmer/acpi/ide.asl | 244 ---- src/mainboard/amd/parmer/acpi/mainboard.asl | 43 + src/mainboard/amd/parmer/acpi/routing.asl | 59 +- src/mainboard/amd/parmer/acpi/sata.asl | 148 -- src/mainboard/amd/parmer/acpi/si.asl | 28 + src/mainboard/amd/parmer/acpi/sleep.asl | 104 ++ src/mainboard/amd/parmer/acpi/superio.asl | 20 + src/mainboard/amd/parmer/acpi/thermal.asl | 20 + src/mainboard/amd/parmer/acpi/usb.asl | 114 -- src/mainboard/amd/parmer/acpi/usb_oc.asl | 31 + src/mainboard/amd/parmer/devicetree.cb | 14 +- src/mainboard/amd/parmer/dsdt.asl | 1451 +------------------- .../amd/agesa/family15tn/acpi/northbridge.asl | 90 ++ src/southbridge/amd/agesa/hudson/acpi/audio.asl | 56 + src/southbridge/amd/agesa/hudson/acpi/fch.asl | 190 +++ src/southbridge/amd/agesa/hudson/acpi/lpc.asl | 112 ++ src/southbridge/amd/agesa/hudson/acpi/pci_int.asl | 471 +++++++ src/southbridge/amd/agesa/hudson/acpi/pcie.asl | 96 ++ .../amd/agesa/hudson/acpi/sleepstates.asl | 41 + src/southbridge/amd/agesa/hudson/acpi/smbus.asl | 21 + src/southbridge/amd/agesa/hudson/acpi/usb.asl | 65 + 23 files changed, 1611 insertions(+), 1970 deletions(-) diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl new file mode 100755 index 0000000..597fa3d --- /dev/null +++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl new file mode 100755 index 0000000..83d506a --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + diff --git a/src/mainboard/amd/parmer/acpi/ide.asl b/src/mainboard/amd/parmer/acpi/ide.asl deleted file mode 100644 index 1ff2e79..0000000 --- a/src/mainboard/amd/parmer/acpi/ide.asl +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/parmer/acpi/mainboard.asl b/src/mainboard/amd/parmer/acpi/mainboard.asl new file mode 100755 index 0000000..ca4147c --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/mainboard.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* AcpiGpe0Blk */ + OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, + } diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl index 4967edb..273afc0 100644 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ b/src/mainboard/amd/parmer/acpi/routing.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012, 2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,16 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { + /* Routing is in System Bus scope */ Name(PR0, Package(){ /* NB devices */ /* Bus 0, Dev 0 - F15 Host Controller */ @@ -70,17 +61,17 @@ Scope(\_SB) { Package(){0x0007FFFF, 2, INTB, 0 }, Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* SB devices */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, Package(){0x0014FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ + /* SB devices */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, INTC, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, @@ -90,7 +81,7 @@ Scope(\_SB) { Package(){0x0016FFFF, 0, INTC, 0 }, Package(){0x0016FFFF, 1, INTB, 0 }, - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ Package(){0x0010FFFF, 0, INTC, 0 }, Package(){0x0010FFFF, 1, INTB, 0 }, @@ -110,7 +101,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, 0, 17 }, - package(){0x0001FFFF, 1, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 18 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, @@ -148,17 +139,17 @@ Scope(\_SB) { Package(){0x0007FFFF, 2, 0, 17 }, Package(){0x0007FFFF, 3, 0, 18 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, 0, 18 }, Package(){0x0012FFFF, 1, 0, 17 }, @@ -168,7 +159,7 @@ Scope(\_SB) { Package(){0x0016FFFF, 0, 0, 18 }, Package(){0x0016FFFF, 1, 0, 17 }, - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ Package(){0x0010FFFF, 0, 0, 0x12}, Package(){0x0010FFFF, 1, 0, 0x11}, @@ -197,23 +188,6 @@ Scope(\_SB) { Package(){0x0000FFFF, 3, 0, 17 }, }) -#if 0 //parmer not use - Name(PS3, Package(){ - /* The external GFX - Hooked to PCIe slot 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS3, Package(){ - /* The external GFX - Hooked to PCIe slot 3 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) -#endif - Name(PS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ Package(){0x0000FFFF, 0, INTA, 0 }, @@ -346,11 +320,4 @@ Scope(\_SB) { Package(){0x0006FFFF, 1, 0, 0x16 }, Package(){0x0006FFFF, 2, 0, 0x17 }, Package(){0x0006FFFF, 3, 0, 0x14 }, -/* - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, -*/ }) -} diff --git a/src/mainboard/amd/parmer/acpi/sata.asl b/src/mainboard/amd/parmer/acpi/sata.asl deleted file mode 100644 index c817b6e..0000000 --- a/src/mainboard/amd/parmer/acpi/sata.asl +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/parmer/acpi/si.asl b/src/mainboard/amd/parmer/acpi/si.asl new file mode 100755 index 0000000..2eee572 --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/si.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl new file mode 100755 index 0000000..4628f59 --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/sleep.asl @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,USBS) + + Return(WKST) +} /* End Method(\_WAK) */ + diff --git a/src/mainboard/amd/parmer/acpi/superio.asl b/src/mainboard/amd/parmer/acpi/superio.asl new file mode 100755 index 0000000..9b1ef60 --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/amd/parmer/acpi/thermal.asl b/src/mainboard/amd/parmer/acpi/thermal.asl new file mode 100755 index 0000000..c7451da --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/thermal.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No thermal zone functionality */ diff --git a/src/mainboard/amd/parmer/acpi/usb.asl b/src/mainboard/amd/parmer/acpi/usb.asl deleted file mode 100644 index 857c78f..0000000 --- a/src/mainboard/amd/parmer/acpi/usb.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* simple name description */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} diff --git a/src/mainboard/amd/parmer/acpi/usb_oc.asl b/src/mainboard/amd/parmer/acpi/usb_oc.asl new file mode 100755 index 0000000..f92c600 --- /dev/null +++ b/src/mainboard/amd/parmer/acpi/usb_oc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012, 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 62b37e1..1b294cb 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012,2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -45,10 +45,10 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 10.0 on end # XHCI HC0 device pci 10.1 on end # XHCI HC1 device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB + device pci 12.0 on end # USB - OHCI + device pci 12.2 on end # USB - EHCI + device pci 13.0 on end # USB - OHCI + device pci 13.2 on end # USB - EHCI device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 device i2c 50 on end # 7-bit SPD address @@ -61,13 +61,15 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 + device pci 14.5 on end # USB 2 - OHCI device pci 14.6 off end # Gec device pci 14.7 on end # SD device pci 15.0 off end # PCIe 0 device pci 15.1 off end # PCIe 1 device pci 15.2 off end # PCIe 2 device pci 15.3 off end # PCIe 3 + device pci 16.0 on end # USB - OHCI + device pci 16.2 on end # USB - EHCI register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #chip southbridge/amd/hudson diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index e36965e..2b98bfa 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012,2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,1439 +19,66 @@ /* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00010001 /* OEM Revision */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ + /* Globals for the platform */ + #include "acpi/mainboard.asl" - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - /* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ + /* Describe the supported Sleep States for this Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - - Processor( - P001, /* name space name */ - 1, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P002, /* name space name */ - 2, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P003, /* name space name */ - 3, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P004, /* name space name */ - 4, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P005, /* name space name */ - 5, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P006, /* name space name */ - 6, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P007, /* name space name */ - 7, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0xEE), - UPWS, 3, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" Scope(\_SB) { - /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ - OperationRegion(PCFG, SystemMemory, PCBA, PCLN) - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(CkOT, 0){ - - if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - if(CondRefOf(\_OSI,Local1)) - { - Store(1, OSTP) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSTP) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSTP) /* Linux */ - } Else { - Store(4, OSTP) /* Gotta be WinCE */ - } - } - Return(OSTP) - } + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - //Store(0, PIRA) - //Store(0, PIRB) - //Store(0, PIRC) - //Store(0, PIRD) - //Store(0, PIRE) - //Store(0, PIRF) - //Store(0, PIRG) - //Store(0, PIRH) } - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - //Store(0x1F, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - //Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - //Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - //Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - //Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - //Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - //Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - //Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - //Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - //Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> } /* End Scope(_SB) */ - /* Supported sleep states: */ - Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - - If (LAnd(SSFG, 0x01)) { - Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ - } - If (LAnd(SSFG, 0x02)) { - Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ - } - If (LAnd(SSFG, 0x04)) { - Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ - } - If (LAnd(SSFG, 0x08)) { - Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ - } - - Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ - - Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ - Name(CSMS, 0) /* Current System State */ - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - //if (LEqual(Arg0,3)){ - // Store(0,URRE) - //} - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - } /* End Method(\_PTS) */ + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" - /* Re-enable HPET */ - //Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - //if (LEqual(Arg0,3)){ - // Store(1,URRE) - //} - - /* Arbitrarily clear PciExpWakeStatus */ - //Store(PWST, PWST) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Store(1, USBS) - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - //#include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices Dev0 ,Func0*/ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - -#if 0 //not used in Parmer - /* Dev3 is also an external GFX bridge */ - Device(PBR3) { - Name(_ADR, 0x00030000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS3) } /* APIC mode */ - Return (PS3) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR3 */ -#endif - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - //#include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(XHC0) { - Name(_ADR, 0x00100000) - Name(_PRW, Package() {0x0B, 4}) - } /* end XHC0 */ - Device(XHC1) { - Name(_ADR, 0x00100001) - Name(_PRW, Package() {0x0B, 4}) - } /* end XHC1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - //#include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space - Field(CFG,DWordAcc,NoLock,Preserve){ - Offset(0xA0), - BAR,32} // SPI Controller Base Address Register (Index 0xA0) - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources - Name (CRS, ResourceTemplate () // Current Motherboard resources - { - Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address - 0x00000000, // Address Base - 0x00000000, // Address Length - BAR0 // Descriptor Name - ) - }) - - Method(_CRS,0,NotSerialized) - { - CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address - CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length - Store(BAR,SPIB) // SPI base address mapped - Store(0x1000,SPIL) // 4k space mapped - Return(CRS) - } - } - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03B0, /* range minimum */ - 0x03DF, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - CkOT() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - /* TODO: It is unstable. */ - //#include "acpi/AmdImc.asl" /* Hudson IMC function */ - //ITZE() /* enable IMC Fan Control*/ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ } /* End of ASL file */ diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl new file mode 100755 index 0000000..81697e5 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ + +Method (_BBN, 0, NotSerialized) +{ + Return (Zero) +} + +Method (_STA, 0, NotSerialized) +{ + Return (0x0B) +} + +Method (_PRT, 0, NotSerialized) +{ + If (PMOD) + { + Return (APR0) + } + + Return (PR0) +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Dev4 GPP0 Root Port Bridge */ +Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Dev5 GPP1 Root Port Bridge */ +Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Dev6 GPP2 Root Port Bridge */ +Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* The onboard EtherNet chip */ +Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl new file mode 100755 index 0000000..b9353e1 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/audio.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + Method (_INI, 0, NotSerialized) + { + If (LEqual (OSTP, 0x03)) + { + Store (Zero, NSEN) + Store (One, NSDO) + Store (One, NSDI) + } + } +} /* end AZHD */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl new file mode 100755 index 0000000..da60e2e --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011,2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* South Bridge */ +/* _SB.PCI0 */ + +/* Describe the Southbridge devices */ + +// #include "pcie.asl" + +/* PCI slot 1, 2, 3 */ +Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } +} + +Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" +} /* end STCR */ + +#include "usb.asl" + +Device(SBUS) { + Name(_ADR, 0x00140000) +} /* end SBUS */ + +/* Primary (and only) IDE channel */ +Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" +} /* end IDEC */ + +#include "audio.asl" + +#include "lpc.asl" + +Device(HPBR) { + Name(_ADR, 0x00140004) +} /* end HostPciBr */ + +Device(ACAD) { + Name(_ADR, 0x00140005) +} /* end Ac97audio */ + +Device(ACMD) { + Name(_ADR, 0x00140006) +} /* end Ac97modem */ + +Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) +}) /* End Name(_SB.PCI0.CRES) */ + +Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ +} /* end of Method(_SB.PCI0._CRS) */ + +/* +* +* FIRST METHOD CALLED UPON BOOT +* +* 1. If debugging, print current OS and ACPI interpreter. +* 2. Get PCI Interrupt routing from ACPI VSM, this +* value is based on user choice in BIOS setup. +*/ +Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ +} /* End Method(_SB._INI) */ + +Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) +} + +Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ +} diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl new file mode 100755 index 0000000..f8751fa --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space + Field(CFG,DWordAcc,NoLock,Preserve){ + Offset(0xA0), + BAR,32} // SPI Controller Base Address Register (Index 0xA0) + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources + Name (CRS, ResourceTemplate () // Current Motherboard resources + { + Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address + 0x00000000, // Address Base + 0x00000000, // Address Length + BAR0 // Descriptor Name + ) + }) + + Method(_CRS,0,NotSerialized) + { + CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address + CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length + Store(BAR,SPIB) // SPI base address mapped + Store(0x1000,SPIL) // 4k space mapped + Return(CRS) + } + } + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + #include "acpi/superio.asl" +} /* end LIBR */ + diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl new file mode 100755 index 0000000..4512c59 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -0,0 +1,471 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* SATA reg 24h Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* OHCI0 reg 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* SMBUS reg 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* SMBUS reg 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* SMBUS reg 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* SMBUS reg 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + + Method(CIRQ, 0x00, NotSerialized){ + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_SRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl new file mode 100755 index 0000000..2b4e088 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* PCI IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0xEE), + UPWS, 3, + } + diff --git a/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl b/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl new file mode 100755 index 0000000..b515e55 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Supported sleep states: */ +Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + +If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ +} +If (LAnd (SSFG, 0x02)) { + Name (_S2, Package () {0x02, 0x02, Zero, Zero} ) /* (S2) - "light" Suspend to RAM */ +} + +If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ +} +If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ +} + +Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + +Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ +Name(CSMS, 0) /* Current System State */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/smbus.asl b/src/southbridge/amd/agesa/hudson/acpi/smbus.asl new file mode 100755 index 0000000..a40dfbd --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/smbus.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* SMBUS Support */ + diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl new file mode 100755 index 0000000..ea6ea02 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH1 */ + +Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH2 */ + +Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH3 */ + +Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH4 */ + +Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) +} /* end UEH1 */ + +Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) +} /* end XHC0 */ +Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) +} /* end XHC1 */ +

1 0

Patch set updated for coreboot: d1a7734 device: Fix spelling
by Martin Roth 09 Jul '13

09 Jul '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3730 -gerrit commit d1a7734e6d187aac59a17977a5c33ae82fe61b76 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 8 16:24:19 2013 -0600 device: Fix spelling Change-Id: I53a40d114aa2da76398c5b97443d4096809dcf36 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/device/device.c | 14 +++++++------- src/device/device_util.c | 4 ++-- src/device/dram/ddr3.c | 6 +++--- src/device/hypertransport.c | 10 +++++----- src/device/oprom/include/x86emu/regs.h | 4 ++-- src/device/oprom/include/x86emu/x86emu.h | 8 ++++---- src/device/oprom/realmode/x86_interrupts.c | 4 ++-- src/device/oprom/x86emu/debug.h | 2 +- src/device/oprom/x86emu/decode.c | 10 +++++----- src/device/oprom/x86emu/ops.c | 16 ++++++++-------- src/device/oprom/x86emu/prim_ops.c | 14 +++++++------- src/device/oprom/x86emu/sys.c | 4 ++-- src/device/oprom/x86emu/x86emui.h | 2 +- src/device/oprom/yabel/biosemu.c | 4 ++-- src/device/oprom/yabel/biosemu.h | 6 +++--- src/device/oprom/yabel/compat/functions.c | 2 +- src/device/oprom/yabel/device.c | 20 ++++++++++---------- src/device/oprom/yabel/interrupt.c | 4 ++-- src/device/oprom/yabel/io.c | 12 ++++++------ src/device/oprom/yabel/mem.c | 8 ++++---- src/device/oprom/yabel/pmm.c | 2 +- src/device/oprom/yabel/pmm.h | 6 +++--- src/device/oprom/yabel/vbe.c | 4 ++-- 23 files changed, 83 insertions(+), 83 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index a971270..3837928 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -83,7 +83,7 @@ uint64_t uma_memory_size = 0; /** * Allocate a new device structure. * - * Allocte a new device structure and attach it to the device tree as a + * Allocate a new device structure and attach it to the device tree as a * child of the parent bus. * * @param parent Parent bus the newly created device should be attached to. @@ -415,7 +415,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * A PCI bridge resource does not need to be a power of two size, but * it does have a minimum granularity. Round the size up to that * minimum granularity so we know not to place something else at an - * address postitively decoded by the bridge. + * address positively decoded by the bridge. */ bridge->size = round(base, bridge->gran) - round(bridge->base, bridge->align); @@ -730,7 +730,7 @@ device_t vga_pri = 0; static void set_vga_bridge_bits(void) { /* - * FIXME: Modify set_vga_bridge() so it is less PCI centric! + * FIXME: Modify set_vga_bridge() so it is less PCI-centric! * This function knows too much about PCI stuff, it should be just * an iterator/visitor. */ @@ -835,7 +835,7 @@ void assign_resources(struct bus *bus) * * The parent's resources should be enabled first to avoid having enabling * order problem. This is done by calling the parent's enable_resources() - * method before its childrens' enable_resources() methods. + * method before its children's enable_resources() methods. * * @param link The link whose devices' resources are to be enabled. */ @@ -959,7 +959,7 @@ void dev_enumerate(void) * * Starting at the root of the device tree, travel it recursively in two * passes. In the first pass, we compute and allocate resources (ranges) - * requried by each device. In the second pass, the resources ranges are + * required by each device. In the second pass, the resources ranges are * relocated to their final position and stored to the hardware. * * I/O resources grow upward. MEM resources grow downward. @@ -1025,7 +1025,7 @@ void dev_configure(void) /* * Now we need to adjust the resources. MEM resources need to start at - * the highest address managable. + * the highest address manageable. */ for (child = root->link_list->children; child; child = child->sibling) { if (child->path.type != DEVICE_PATH_DOMAIN) @@ -1093,7 +1093,7 @@ void dev_enable(void) * Initialize a specific device. * * The parent should be initialized first to avoid having an ordering problem. - * This is done by calling the parent's init() method before its childrens' + * This is done by calling the parent's init() method before its children's * init() methods. * * @param dev The device to be initialized. diff --git a/src/device/device_util.c b/src/device/device_util.c index 180169d..d2c99e1 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -285,7 +285,7 @@ int path_eq(struct device_path *path1, struct device_path *path2) equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; default: - printk(BIOS_ERR, "Uknown device type: %d\n", path1->type); + printk(BIOS_ERR, "Unknown device type: %d\n", path1->type); break; } @@ -544,7 +544,7 @@ const char *resource_type(struct resource *resource) /** * Print the resource that was just stored. * - * @param dev The device the stored resorce lives on. + * @param dev The device the stored resource lives on. * @param resource The resource that was just stored. * @param comment TODO */ diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 6e3fc2a..d98de91 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -55,7 +55,7 @@ int dimm_is_registered(enum spd_dimm_type type) * @ref dimm_attr structure. The SPD data must first be read in a contiguous * array, and passed to this function. * - * @param dimm pointer to @ref dimm_attr stucture where the decoded data is to + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to * be stored * @param spd array of raw data previously read from the SPD. * @@ -309,7 +309,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) if (spd[63] & 0x01) { dimm->flags.pins_mirrored = 1; - printram(" DIMM Rank1 Address bits mirrorred!!!\n"); + printram(" DIMM Rank1 Address bits mirrored!!!\n"); } return ret; @@ -336,7 +336,7 @@ static void print_ns(const char *msg, u32 val) * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is * selected, or for a purely informative output. * -* @param dimm pointer to already decoded @ref dimm_attr stucture +* @param dimm pointer to already decoded @ref dimm_attr structure */ void dram_print_spd_ddr3(const dimm_attr * dimm) { diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 11ea9a5..d9ab486 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -106,7 +106,7 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos) #if CONFIG_K8_HT_FREQ_1G_SUPPORT #if !CONFIG_K8_REV_F_SUPPORT - /* Only e0 later suupport 1GHz HT. */ + /* Only e0 later support 1GHz HT. */ if (is_cpu_pre_e0()) freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif @@ -176,7 +176,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off); - /* Calculate the highest useable frequency. */ + /* Calculate the highest usable frequency. */ freq = log2(present_freq_cap & upstream_freq_cap); /* Calculate the highest width. */ @@ -436,7 +436,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, device_t real_last_dev = NULL; #endif - /* Restore the hypertransport chain to it's unitialized state. */ + /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); /* See which static device nodes I have. */ @@ -571,7 +571,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, if (next_unitid > max_unitid) max_unitid = next_unitid; - /* Setup the hypetransport link. */ + /* Setup the hypertransport link. */ bus->reset_needed |= ht_setup_link(&prev, dev, pos); printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", @@ -658,7 +658,7 @@ end_of_chain: * @param bus TODO * @param min_devfn TODO * @param max_devfn TODO - * @param max The highest bus number assgined up to now. + * @param max The highest bus number assigned up to now. * @return The maximum bus number found, after scanning all subordinate busses. */ static unsigned int hypertransport_scan_chain_x(struct bus *bus, diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index d738974..4bf1294 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -231,8 +231,8 @@ struct i386_segment_regs { #define SYSMODE_PREFIX_REPNE 0x00000100 #define SYSMODE_PREFIX_DATA 0x00000200 #define SYSMODE_PREFIX_ADDR 0x00000400 -//phueper: for REP(E|NE) Instructions, we need to decide wether it should be using -//the 32bit ECX register as or the 16bit CX register as count register +//phueper: for REP(E|NE) Instructions, we need to decide whether it should be +//using the 32bit ECX register as or the 16bit CX register as count register #define SYSMODE_32BIT_REP 0x00000800 #define SYSMODE_INTR_PENDING 0x10000000 #define SYSMODE_EXTRN_INTR 0x20000000 diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 3ceee49..b912bd2 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -59,11 +59,11 @@ /**************************************************************************** REMARKS: -Data structure containing ponters to programmed I/O functions used by the +Data structure containing pointers to programmed I/O functions used by the emulator. This is used so that the user program can hook all programmed I/O for the emulator to handled as necessary by the user program. By default the emulator contains simple functions that do not do access the -hardware in any way. To allow the emualtor access the hardware, you will +hardware in any way. To allow the emulator access the hardware, you will need to override the programmed I/O functions using the X86EMU_setupPioFuncs function. @@ -89,11 +89,11 @@ typedef struct { /**************************************************************************** REMARKS: -Data structure containing ponters to memory access functions used by the +Data structure containing pointers to memory access functions used by the emulator. This is used so that the user program can hook all memory access functions as necessary for the emulator. By default the emulator contains simple functions that only access the internal memory of the -emulator. If you need specialised functions to handle access to different +emulator. If you need specialized functions to handle access to different types of memory (ie: hardware framebuffer accesses and BIOS memory access etc), you will need to override this using the X86EMU_setupMemFuncs function. diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index b3764f9..383c736 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -123,7 +123,7 @@ int int1a_handler(void) unsigned short func = (unsigned short)X86_EAX; int retval = 1; unsigned short devid, vendorid, devfn; - /* Use short to get rid of gabage in upper half of 32-bit register */ + /* Use short to get rid of garbage in upper half of 32-bit register */ short devindex; unsigned char bus; struct device *dev; @@ -137,7 +137,7 @@ int int1a_handler(void) X86_EAX &= 0xffff0000; /* Clear AH / AL */ X86_EAX |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1; // last bus in the system. Hard code to 255 for now. - // dev_enumerate() does not seem to tell us (publically) + // dev_enumerate() does not seem to tell us (publicly) X86_ECX = 0xff; X86_EDI = 0x00000000; /* protected mode entry */ retval = 1; diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index 1b2c3a3..6858f15 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -118,7 +118,7 @@ /* * The following allow us to look at the bytes of an instruction. The - * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * first INCR_INSTRN_LEN, is called every time bytes are consumed in * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index ed96dc6..3d3f77d 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -33,7 +33,7 @@ * Developer: Kendall Bennett * * Description: This file includes subroutines which are related to -* instruction decoding and accessess of immediate data via IP. etc. +* instruction decoding and accesses of immediate data via IP. etc. * ****************************************************************************/ @@ -43,7 +43,7 @@ /**************************************************************************** REMARKS: -Handles any pending asychronous interrupts. +Handles any pending asynchronous interrupts. ****************************************************************************/ static void x86emu_intr_handle(void) { @@ -77,7 +77,7 @@ next instruction. void x86emu_intr_raise( u8 intrnum) { - printf("%s, raising exeception %x\n", __func__, intrnum); + printf("%s, raising exception %x\n", __func__, intrnum); x86emu_dump_regs(); M.x86.intno = intrnum; M.x86.intr |= INTR_SYNCH; @@ -243,7 +243,7 @@ no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to addresses relative to SS (ie: on the stack). So, at the minimum, all decodings of addressing modes would have to set/clear a bit describing whether the access is relative to DS or SS. That is the function of the -cpu-state-varible M.x86.mode. There are several potential states: +cpu-state-variable M.x86.mode. There are several potential states: repe prefix seen (handled elsewhere) repne prefix seen (ditto) @@ -255,7 +255,7 @@ cpu-state-varible M.x86.mode. There are several potential states: gs segment override ss segment override - ds/ss select (in absense of override) + ds/ss select (in absence of override) Each of the above 7 items are handled with a bit in the mode field. ****************************************************************************/ diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index 6917a08..c805b58 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -39,7 +39,7 @@ * to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * -* Each opcode proc has a comment preceeding it which gives it's table +* Each opcode proc has a comment preceding it which gives it's table * address. Several opcodes are missing (undefined) in the table. * * Each proc includes information for decoding (DECODE_PRINTF and @@ -2530,7 +2530,7 @@ static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -2577,7 +2577,7 @@ static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -2773,7 +2773,7 @@ static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); @@ -2820,7 +2820,7 @@ static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -2858,7 +2858,7 @@ static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) else inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { M.x86.R_AL = fetch_data_byte(M.x86.R_SI); @@ -2905,7 +2905,7 @@ static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -4075,7 +4075,7 @@ static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) END_OF_INSTR(); } -/* instuctions D8 .. DF are in i87_ops.c */ +/* Instructions D8 .. DF are in i87_ops.c */ /**************************************************************************** REMARKS: diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 20e7597..e73f217 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -134,7 +134,7 @@ static u32 x86emu_parity_tab[8] = /**************************************************************************** REMARKS: -implements side efects for byte operations that don't overflow +implements side effects for byte operations that don't overflow ****************************************************************************/ static void set_parity_flag(u32 res) @@ -790,7 +790,7 @@ u8 rcl_byte(u8 d, u8 s) /* OVERFLOW is set *IFF* cnt==1, then it is the xor of CF and the most significant bit. Blecck. */ /* parenthesized this expression since it appears to - be causing OF to be misset */ + be causing OF to be missed */ CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), F_OF); @@ -1800,7 +1800,7 @@ void test_byte(u8 d, u8 s) CLEAR_FLAG(F_OF); set_szp_flags_8((u8)res); - /* AF == dont care */ + /* AF == don't care */ CLEAR_FLAG(F_CF); } @@ -1816,7 +1816,7 @@ void test_word(u16 d, u16 s) CLEAR_FLAG(F_OF); set_szp_flags_16((u16)res); - /* AF == dont care */ + /* AF == don't care */ CLEAR_FLAG(F_CF); } @@ -1832,7 +1832,7 @@ void test_long(u32 d, u32 s) CLEAR_FLAG(F_OF); set_szp_flags_32(res); - /* AF == dont care */ + /* AF == don't care */ CLEAR_FLAG(F_CF); } @@ -2311,7 +2311,7 @@ void ins(int size) inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* in until (E)CX is ZERO. */ u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX); @@ -2353,7 +2353,7 @@ void outs(int size) inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* out until (E)CX is ZERO. */ u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX); diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index b3b3cd7..9785a9d 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -35,7 +35,7 @@ * Description: This file includes subroutines which are related to * programmed I/O and memory access. Included in this module * are default functions with limited usefulness. For real -* uses these functions will most likely be overriden by the +* uses these functions will most likely be overridden by the * user library. * ****************************************************************************/ @@ -381,7 +381,7 @@ PARAMETERS: int - New software interrupt to prepare for REMARKS: -This function is used to set up the emulator state to exceute a software +This function is used to set up the emulator state to execute a software interrupt. This can be used by the user application code to allow an interrupt to be hooked, examined and then reflected back to the emulator so that the code in the emulator will continue processing the software diff --git a/src/device/oprom/x86emu/x86emui.h b/src/device/oprom/x86emu/x86emui.h index e34a1ba..37339d5 100644 --- a/src/device/oprom/x86emu/x86emui.h +++ b/src/device/oprom/x86emu/x86emui.h @@ -33,7 +33,7 @@ * Developer: Kendall Bennett * * Description: Header file for system specific functions. These functions -* are always compiled and linked in the OS depedent libraries, +* are always compiled and linked in the OS dependent libraries, * and never in a binary portable driver. * ****************************************************************************/ diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index f42d4e1..d27a5f1 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -219,7 +219,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad my_wrb(0x000ffe6e, 0xcf); // setup BIOS Data Area (0000:04xx, or 0040:00xx) - // we currently 0 this area, meaning "we dont have + // we currently 0 this area, meaning "we don't have // any hardware" :-) no serial/parallel ports, floppys, ... memset(biosmem + 0x400, 0x0, 0x100); @@ -388,7 +388,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad */ if ((pop_word() == 0xf4f4) && (M.x86.R_SS == STACK_SEGMENT) && (M.x86.R_SP == STACK_START_OFFSET)) { - DEBUG_PRINTF("Stack is clean, initialization successfull!\n"); + DEBUG_PRINTF("Stack is clean, initialization successful!\n"); } else { printf("Stack unclean, initialization probably NOT COMPLETE!\n"); DEBUG_PRINTF("SS:SP = %04x:%04x, expected: %04x:%04x\n", diff --git a/src/device/oprom/yabel/biosemu.h b/src/device/oprom/yabel/biosemu.h index 4f5c4aa..69e1fc3 100644 --- a/src/device/oprom/yabel/biosemu.h +++ b/src/device/oprom/yabel/biosemu.h @@ -24,7 +24,7 @@ #define VBE_SEGMENT 0x3000 #define PMM_CONV_SEGMENT 0x4000 // 4000:xxxx is PMM conventional memory area, extended memory area - // will be anything beyound MIN_REQUIRED_MEMORY_SIZE + // will be anything beyond MIN_REQUIRED_MEMORY_SIZE #define PNP_DATA_SEGMENT 0x5000 #define OPTION_ROM_CODE_SEGMENT 0xc000 @@ -38,9 +38,9 @@ // Address, there will only be a call to this INT and a RETF #define PNP_INT_NUM 0xFD -/* array of funtion pointers to override generic interrupt handlers +/* array of function pointers to override generic interrupt handlers * a YABEL caller can add functions to this array before calling YABEL - * if a interrupt occurs, YABEL checks wether a function is set in + * if a interrupt occurs, YABEL checks whether a function is set in * this array and only runs the generic interrupt handler code, if * the function pointer is NULL */ typedef int (* yabel_handleIntFunc)(void); diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index f693d7b..1b2d011 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -10,7 +10,7 @@ ****************************************************************************/ /* this file contains functions provided by SLOF, that the current biosemu implementation needs - * they should go away inthe future... + * they should go away in the future... */ #include <types.h> diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index b09f50e..2f41847 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -60,7 +60,7 @@ biosemu_dev_get_addr_info(void) r->index; translate_address_array[taa_index].address = r->base; translate_address_array[taa_index].size = r->size; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; } @@ -71,7 +71,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0x30; translate_address_array[taa_index].address = bios_device.img_addr; translate_address_array[taa_index].size = 0; /* TODO: do we need the size? */ - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; /* legacy ranges if its a VGA card... */ @@ -84,7 +84,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = 0x3b0; translate_address_array[taa_index].size = 0xc; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; /* I/O 0x3C0-0x3DF */ @@ -94,7 +94,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = 0x3c0; translate_address_array[taa_index].size = 0x20; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; /* Mem 0xA0000-0xBFFFF */ @@ -104,7 +104,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = 0xa0000; translate_address_array[taa_index].size = 0x20000; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; } @@ -130,7 +130,7 @@ void translate_address_dev(u64 *, phandle_t); u64 get_puid(phandle_t node); -// scan all adresses assigned to the device ("assigned-addresses" and "reg") +// scan all addresses assigned to the device ("assigned-addresses" and "reg") // store in translate_address_array for faster translation using dev_translate_address void biosemu_dev_get_addr_info(void) @@ -171,7 +171,7 @@ biosemu_dev_get_addr_info(void) len = of_getprop(bios_device.phandle, "reg", buf, sizeof(buf)); for (i = 0; i < (len / sizeof(assigned_address_t)); i++) { if ((buf[i].size == 0) || (buf[i].cfg_space_offset != 0)) { - // we dont care for ranges with size 0 and + // we don't care for ranges with size 0 and // BARs and Expansion ROM must be in assigned-addresses... so in reg // we only look for those without config space offset set... // i.e. the legacy ranges @@ -211,7 +211,7 @@ biosemu_dev_get_addr_info(void) // "special memory" is a hack to make some parts of memory fall through to real memory // (ie. no translation). Necessary if option ROMs attempt DMA there, map registers or -// do similarily crazy things. +// do similarly crazy things. void biosemu_add_special_memory(u32 start, u32 size) { @@ -222,7 +222,7 @@ biosemu_add_special_memory(u32 start, u32 size) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = start; translate_address_array[taa_index].size = size; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; } @@ -443,7 +443,7 @@ biosemu_dev_translate_address(int type, unsigned long * addr) int i = 0; translate_address_t ta; #if !CONFIG_PCI_OPTION_ROM_RUN_YABEL - /* we dont need this hack for coreboot... we can access legacy areas */ + /* we don't need this hack for coreboot... we can access legacy areas */ //check if it is an access to legacy VGA Mem... if it is, map the address //to the vmem BAR and then translate it... // (translation info provided by Ben Herrenschmidt) diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index e5b4a3c..cf430be 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -243,7 +243,7 @@ handleInt16(void) // since we currently always read the char from the FW buffer, // we misuse the ring buffer, we use it as pointer to a u64 that stores // multi-byte keys (e.g. special keys in VT100 terminal) - // and as long as a key is available (not 0) we dont read further keys + // and as long as a key is available (not 0) we don't read further keys u64 *keycode = (u64 *) (M.mem_base + 0x41e); s8 c; // function number in AH @@ -538,7 +538,7 @@ handleInterrupt(int intNum) DEBUG_PRINTF_INTR("%s(%x)\n", __func__, intNum); #endif - /* check wether this interrupt has a function pointer set in yabel_intFuncArray and run that */ + /* check whether this interrupt has a function pointer set in yabel_intFuncArray and run that */ if (yabel_intFuncArray[intNum]) { DEBUG_PRINTF_INTR("%s(%x) intHandler overridden, calling it...\n", __func__, intNum); int_handled = (*yabel_intFuncArray[intNum])(); diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index d1172dc..94f610d 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -188,7 +188,7 @@ my_inb(X86EMU_pioAddr addr) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__, addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -238,7 +238,7 @@ my_inw(X86EMU_pioAddr addr) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__, addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -283,7 +283,7 @@ my_inl(X86EMU_pioAddr addr) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__, addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -329,7 +329,7 @@ my_outb(X86EMU_pioAddr addr, u8 val) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -361,7 +361,7 @@ my_outw(X86EMU_pioAddr addr, u16 val) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -402,7 +402,7 @@ my_outl(X86EMU_pioAddr addr, u32 val) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index 4b4a552..a7d0289 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -177,7 +177,7 @@ static inline void DEBUG_CHECK_VMEM_WRITE(u32 _addr, u32 _val) {}; static void update_time(u32 cur_val) { - //for convenience, we let the start of timebase be at midnight, we currently dont support + //for convenience, we let the start of timebase be at midnight, we currently don't support //real daytime anyway... u64 ticks_per_day = tb_freq * 60 * 24; // at 18Hz a period is ~55ms, converted to ticks (tb_freq is ticks/second) @@ -202,7 +202,7 @@ my_rdb(u32 addr) u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); u8 rval; if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%08x): access to VGA Memory\n", __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -234,7 +234,7 @@ my_rdw(u32 addr) u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); u16 rval; if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%08x): access to VGA Memory\n", __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -285,7 +285,7 @@ my_rdl(u32 addr) u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); u32 rval; if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%x): access to VGA Memory\n", __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); diff --git a/src/device/oprom/yabel/pmm.c b/src/device/oprom/yabel/pmm.c index 19d14d4..d6c528d 100644 --- a/src/device/oprom/yabel/pmm.c +++ b/src/device/oprom/yabel/pmm.c @@ -222,7 +222,7 @@ void pmm_handleInt() DEBUG_PRINTF_PMM("%s: pmmDeallocate: PMM segment offset: %x\n", __func__, buffer); i = 0; - /* rval = 0 means we deallocated the buffer, so set it to 1 in case we dont find it and + /* rval = 0 means we deallocated the buffer, so set it to 1 in case we don't find it and * thus cannot deallocate */ rval = 1; diff --git a/src/device/oprom/yabel/pmm.h b/src/device/oprom/yabel/pmm.h index 3cc3c17..6416c11 100644 --- a/src/device/oprom/yabel/pmm.h +++ b/src/device/oprom/yabel/pmm.h @@ -24,9 +24,9 @@ typedef struct { u8 checksum; u32 entry_point_offset; u8 reserved[5]; - /* Code is not part of the speced PMM struct, however, since I cannot - * put the handling of PMM in the virtual memory (I dont want to hack it - * together in x86 assembly ;-)) this code array is pointed to by + /* Code is not part of the specced PMM struct, however, since I cannot + * put the handling of PMM in the virtual memory (I don't want to hack + * it together in x86 assembly ;-)) this code array is pointed to by * entry_point_offset, in code there is only a INT call and a RETF, * thus every PMM call will issue a PMM INT (only defined in YABEL, * see interrupt.c) and the INT Handler will do the actual PMM work. diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 5952dae..8658b77 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -103,7 +103,7 @@ vbe_info(vbe_info_t * info) // offset 4: 16bit le containing VbeVersion info->version = in16le(vbe_info_buffer + 4); - // offset 6: 32bit le containg segment:offset of OEM String in virtual Mem. + // offset 6: 32bit le containing segment:offset of OEM String in virtual Mem. info->oem_string_ptr = biosmem + ((in16le(vbe_info_buffer + 8) << 4) + in16le(vbe_info_buffer + 6)); @@ -457,7 +457,7 @@ vbe_get_info(void) // as input, it must contain a screen_info_input_t with the following content: // byte[0:3] = "DDC\0" (zero-terminated signature header) // byte[4:5] = reserved space for the return struct... just in case we ever change - // the struct and dont have reserved enough memory (and let's hope the struct + // the struct and don't have reserved enough memory (and let's hope the struct // never gets larger than 64KB) // byte[6] = monitor port number for DDC requests ("only" one byte... so lets hope we never have more than 255 monitors... // byte[7:8] = max. screen width (OF may want to limit this)

1 0

New patch to review for coreboot: ddc7dd9 device: Fix spelling
by Martin Roth 09 Jul '13

09 Jul '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3730 -gerrit commit ddc7dd9f9182b9f9492d67a13198c5a51f8ebf3c Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 8 16:24:19 2013 -0600 device: Fix spelling Change-Id: I53a40d114aa2da76398c5b97443d4096809dcf36 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/device/base | 74 ++++++++++++++++++++++++++++++ src/device/device.c | 14 +++--- src/device/device_util.c | 4 +- src/device/dram/ddr3.c | 6 +-- src/device/hypertransport.c | 10 ++-- src/device/oprom/include/x86emu/regs.h | 4 +- src/device/oprom/include/x86emu/x86emu.h | 8 ++-- src/device/oprom/realmode/x86_interrupts.c | 4 +- src/device/oprom/x86emu/debug.h | 2 +- src/device/oprom/x86emu/decode.c | 10 ++-- src/device/oprom/x86emu/ops.c | 16 +++---- src/device/oprom/x86emu/prim_ops.c | 14 +++--- src/device/oprom/x86emu/sys.c | 4 +- src/device/oprom/x86emu/x86emui.h | 2 +- src/device/oprom/yabel/biosemu.c | 4 +- src/device/oprom/yabel/biosemu.h | 6 +-- src/device/oprom/yabel/compat/functions.c | 2 +- src/device/oprom/yabel/device.c | 20 ++++---- src/device/oprom/yabel/interrupt.c | 4 +- src/device/oprom/yabel/io.c | 12 ++--- src/device/oprom/yabel/mem.c | 8 ++-- src/device/oprom/yabel/pmm.c | 2 +- src/device/oprom/yabel/pmm.h | 6 +-- src/device/oprom/yabel/vbe.c | 4 +- 24 files changed, 157 insertions(+), 83 deletions(-) diff --git a/src/device/base b/src/device/base new file mode 100644 index 0000000..b6ae4b9 --- /dev/null +++ b/src/device/base @@ -0,0 +1,74 @@ +pci_device.c: res->limit = 0xffffUL; +pci_device.c: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | +pci_device.c: res->limit = 0xffffffffULL; +pci_device.c: res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | +pci_device.c: for (res = dev->resource_list; res; res = res->next) +device_util.c: prev->next = res->next; +device_util.c: dev->resource_list = res->next; +device_util.c: res->next = free_resources; +device_util.c: next = res->next; +device_util.c: if (!res->flags) +device_util.c: for (res = dev->resource_list; res; res = res->next) { +device_util.c: if (res->index == index) +device_util.c: for (res = curdev->resource_list; res; res = res->next) { +device_util.c: if ((res->flags & type_mask) != type) +device_util.c: if (res->flags & IORESOURCE_SUBTRACTIVE) { +device_util.c: == IOINDEX_SUBTRACTIVE_LINK(res->index)) +device_util.c: for (res = curdev->resource_list; res; res = res->next) { +device_util.c: if ((res->flags & type_mask) != type) +device_util.c: if (res->flags & IORESOURCE_SUBTRACTIVE) +device_util.c: for (res = root->resource_list; res; res = res->next) { +device_util.c: indent, dev_path(root), res->base, res->size, +device_util.c: res->align, res->gran, res->limit, res->flags, +device_util.c: res->index); +device_util.c: for (res = dev->resource_list; res; res = res->next) +pnp_device.c: for (res = dev->resource_list; res; res = res->next) +device.c: for (res = dev->resource_list; res; res = res->next) { +device.c: if (!(res->flags & IORESOURCE_FIXED)) +device.c: if (!res->size) { +device.c: "size=0!\n", dev_path(dev), res->index); +device.c: if ((res->flags & MEM_MASK) == PREF_TYPE) +device.c: else if ((res->flags & MEM_MASK) == MEM_TYPE) +device.c: else if ((res->flags & IO_MASK) == IO_TYPE) +device.c: if (((res->base + res->size -1) < lim->base) +device.c: || (res->base > lim->limit)) +device.c: if ((signed long long)(lim->limit - (res->base + res->size -1)) +device.c: > (signed long long)(res->base - lim->base)) +device.c: lim->base = res->base + res->size; +device.c: lim->limit = res->base -1; +device.c: for (res = dev->resource_list; res; res = res->next) { +device.c: if ((res->flags & IORESOURCE_FIXED)) +device.c: dev_path(dev), res->index, res->limit); +device.c: if ((res->flags & MEM_MASK) == PREF_TYPE && +device.c: (res->limit < limits.pref.limit)) +device.c: limits.pref.limit = res->limit; +device.c: if ((res->flags & MEM_MASK) == MEM_TYPE && +device.c: (res->limit < limits.mem.limit)) +device.c: limits.mem.limit = res->limit; +device.c: if ((res->flags & IO_MASK) == IO_TYPE && +device.c: (res->limit < limits.io.limit)) +device.c: limits.io.limit = res->limit; +device.c: for (res = dev->resource_list; res; res = res->next) { +device.c: if ((res->flags & IORESOURCE_FIXED)) +device.c: if ((res->flags & MEM_MASK) == PREF_TYPE) +device.c: else if ((res->flags & MEM_MASK) == MEM_TYPE) +device.c: else if ((res->flags & IO_MASK) == IO_TYPE) +device.c: dev_path(dev), res->index, res->limit); +device.c: if (lim->base > res->base) +device.c: res->base = lim->base; +device.c: if (res->limit > lim->limit) +device.c: res->limit = lim->limit; +device.c: for (res = child->resource_list; res; res = res->next) { +device.c: if (res->flags & IORESOURCE_FIXED) +device.c: if (res->flags & IORESOURCE_PREFETCH) { +device.c: if (res->flags & IORESOURCE_MEM) { +device.c: if (res->flags & IORESOURCE_IO) { +device.c: for (res = child->resource_list; res; res = res->next) { +device.c: if (!(res->flags & IORESOURCE_MEM) || +device.c: res->flags & IORESOURCE_FIXED) +device.c: res->base = resource_max(res); +device.c: for (res = child->resource_list; res; res = res->next) { +device.c: if (res->flags & IORESOURCE_FIXED) +device.c: if (res->flags & IORESOURCE_PREFETCH) { +device.c: if (res->flags & IORESOURCE_MEM) { +device.c: if (res->flags & IORESOURCE_IO) { diff --git a/src/device/device.c b/src/device/device.c index a971270..3837928 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -83,7 +83,7 @@ uint64_t uma_memory_size = 0; /** * Allocate a new device structure. * - * Allocte a new device structure and attach it to the device tree as a + * Allocate a new device structure and attach it to the device tree as a * child of the parent bus. * * @param parent Parent bus the newly created device should be attached to. @@ -415,7 +415,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * A PCI bridge resource does not need to be a power of two size, but * it does have a minimum granularity. Round the size up to that * minimum granularity so we know not to place something else at an - * address postitively decoded by the bridge. + * address positively decoded by the bridge. */ bridge->size = round(base, bridge->gran) - round(bridge->base, bridge->align); @@ -730,7 +730,7 @@ device_t vga_pri = 0; static void set_vga_bridge_bits(void) { /* - * FIXME: Modify set_vga_bridge() so it is less PCI centric! + * FIXME: Modify set_vga_bridge() so it is less PCI-centric! * This function knows too much about PCI stuff, it should be just * an iterator/visitor. */ @@ -835,7 +835,7 @@ void assign_resources(struct bus *bus) * * The parent's resources should be enabled first to avoid having enabling * order problem. This is done by calling the parent's enable_resources() - * method before its childrens' enable_resources() methods. + * method before its children's enable_resources() methods. * * @param link The link whose devices' resources are to be enabled. */ @@ -959,7 +959,7 @@ void dev_enumerate(void) * * Starting at the root of the device tree, travel it recursively in two * passes. In the first pass, we compute and allocate resources (ranges) - * requried by each device. In the second pass, the resources ranges are + * required by each device. In the second pass, the resources ranges are * relocated to their final position and stored to the hardware. * * I/O resources grow upward. MEM resources grow downward. @@ -1025,7 +1025,7 @@ void dev_configure(void) /* * Now we need to adjust the resources. MEM resources need to start at - * the highest address managable. + * the highest address manageable. */ for (child = root->link_list->children; child; child = child->sibling) { if (child->path.type != DEVICE_PATH_DOMAIN) @@ -1093,7 +1093,7 @@ void dev_enable(void) * Initialize a specific device. * * The parent should be initialized first to avoid having an ordering problem. - * This is done by calling the parent's init() method before its childrens' + * This is done by calling the parent's init() method before its children's * init() methods. * * @param dev The device to be initialized. diff --git a/src/device/device_util.c b/src/device/device_util.c index 180169d..d2c99e1 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -285,7 +285,7 @@ int path_eq(struct device_path *path1, struct device_path *path2) equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; default: - printk(BIOS_ERR, "Uknown device type: %d\n", path1->type); + printk(BIOS_ERR, "Unknown device type: %d\n", path1->type); break; } @@ -544,7 +544,7 @@ const char *resource_type(struct resource *resource) /** * Print the resource that was just stored. * - * @param dev The device the stored resorce lives on. + * @param dev The device the stored resource lives on. * @param resource The resource that was just stored. * @param comment TODO */ diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 6e3fc2a..d98de91 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -55,7 +55,7 @@ int dimm_is_registered(enum spd_dimm_type type) * @ref dimm_attr structure. The SPD data must first be read in a contiguous * array, and passed to this function. * - * @param dimm pointer to @ref dimm_attr stucture where the decoded data is to + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to * be stored * @param spd array of raw data previously read from the SPD. * @@ -309,7 +309,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) if (spd[63] & 0x01) { dimm->flags.pins_mirrored = 1; - printram(" DIMM Rank1 Address bits mirrorred!!!\n"); + printram(" DIMM Rank1 Address bits mirrored!!!\n"); } return ret; @@ -336,7 +336,7 @@ static void print_ns(const char *msg, u32 val) * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is * selected, or for a purely informative output. * -* @param dimm pointer to already decoded @ref dimm_attr stucture +* @param dimm pointer to already decoded @ref dimm_attr structure */ void dram_print_spd_ddr3(const dimm_attr * dimm) { diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 11ea9a5..d9ab486 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -106,7 +106,7 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos) #if CONFIG_K8_HT_FREQ_1G_SUPPORT #if !CONFIG_K8_REV_F_SUPPORT - /* Only e0 later suupport 1GHz HT. */ + /* Only e0 later support 1GHz HT. */ if (is_cpu_pre_e0()) freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif @@ -176,7 +176,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off); - /* Calculate the highest useable frequency. */ + /* Calculate the highest usable frequency. */ freq = log2(present_freq_cap & upstream_freq_cap); /* Calculate the highest width. */ @@ -436,7 +436,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, device_t real_last_dev = NULL; #endif - /* Restore the hypertransport chain to it's unitialized state. */ + /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); /* See which static device nodes I have. */ @@ -571,7 +571,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, if (next_unitid > max_unitid) max_unitid = next_unitid; - /* Setup the hypetransport link. */ + /* Setup the hypertransport link. */ bus->reset_needed |= ht_setup_link(&prev, dev, pos); printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", @@ -658,7 +658,7 @@ end_of_chain: * @param bus TODO * @param min_devfn TODO * @param max_devfn TODO - * @param max The highest bus number assgined up to now. + * @param max The highest bus number assigned up to now. * @return The maximum bus number found, after scanning all subordinate busses. */ static unsigned int hypertransport_scan_chain_x(struct bus *bus, diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index d738974..4bf1294 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -231,8 +231,8 @@ struct i386_segment_regs { #define SYSMODE_PREFIX_REPNE 0x00000100 #define SYSMODE_PREFIX_DATA 0x00000200 #define SYSMODE_PREFIX_ADDR 0x00000400 -//phueper: for REP(E|NE) Instructions, we need to decide wether it should be using -//the 32bit ECX register as or the 16bit CX register as count register +//phueper: for REP(E|NE) Instructions, we need to decide whether it should be +//using the 32bit ECX register as or the 16bit CX register as count register #define SYSMODE_32BIT_REP 0x00000800 #define SYSMODE_INTR_PENDING 0x10000000 #define SYSMODE_EXTRN_INTR 0x20000000 diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 3ceee49..b912bd2 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -59,11 +59,11 @@ /**************************************************************************** REMARKS: -Data structure containing ponters to programmed I/O functions used by the +Data structure containing pointers to programmed I/O functions used by the emulator. This is used so that the user program can hook all programmed I/O for the emulator to handled as necessary by the user program. By default the emulator contains simple functions that do not do access the -hardware in any way. To allow the emualtor access the hardware, you will +hardware in any way. To allow the emulator access the hardware, you will need to override the programmed I/O functions using the X86EMU_setupPioFuncs function. @@ -89,11 +89,11 @@ typedef struct { /**************************************************************************** REMARKS: -Data structure containing ponters to memory access functions used by the +Data structure containing pointers to memory access functions used by the emulator. This is used so that the user program can hook all memory access functions as necessary for the emulator. By default the emulator contains simple functions that only access the internal memory of the -emulator. If you need specialised functions to handle access to different +emulator. If you need specialized functions to handle access to different types of memory (ie: hardware framebuffer accesses and BIOS memory access etc), you will need to override this using the X86EMU_setupMemFuncs function. diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index b3764f9..383c736 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -123,7 +123,7 @@ int int1a_handler(void) unsigned short func = (unsigned short)X86_EAX; int retval = 1; unsigned short devid, vendorid, devfn; - /* Use short to get rid of gabage in upper half of 32-bit register */ + /* Use short to get rid of garbage in upper half of 32-bit register */ short devindex; unsigned char bus; struct device *dev; @@ -137,7 +137,7 @@ int int1a_handler(void) X86_EAX &= 0xffff0000; /* Clear AH / AL */ X86_EAX |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1; // last bus in the system. Hard code to 255 for now. - // dev_enumerate() does not seem to tell us (publically) + // dev_enumerate() does not seem to tell us (publicly) X86_ECX = 0xff; X86_EDI = 0x00000000; /* protected mode entry */ retval = 1; diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index 1b2c3a3..6858f15 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -118,7 +118,7 @@ /* * The following allow us to look at the bytes of an instruction. The - * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * first INCR_INSTRN_LEN, is called every time bytes are consumed in * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index ed96dc6..3d3f77d 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -33,7 +33,7 @@ * Developer: Kendall Bennett * * Description: This file includes subroutines which are related to -* instruction decoding and accessess of immediate data via IP. etc. +* instruction decoding and accesses of immediate data via IP. etc. * ****************************************************************************/ @@ -43,7 +43,7 @@ /**************************************************************************** REMARKS: -Handles any pending asychronous interrupts. +Handles any pending asynchronous interrupts. ****************************************************************************/ static void x86emu_intr_handle(void) { @@ -77,7 +77,7 @@ next instruction. void x86emu_intr_raise( u8 intrnum) { - printf("%s, raising exeception %x\n", __func__, intrnum); + printf("%s, raising exception %x\n", __func__, intrnum); x86emu_dump_regs(); M.x86.intno = intrnum; M.x86.intr |= INTR_SYNCH; @@ -243,7 +243,7 @@ no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to addresses relative to SS (ie: on the stack). So, at the minimum, all decodings of addressing modes would have to set/clear a bit describing whether the access is relative to DS or SS. That is the function of the -cpu-state-varible M.x86.mode. There are several potential states: +cpu-state-variable M.x86.mode. There are several potential states: repe prefix seen (handled elsewhere) repne prefix seen (ditto) @@ -255,7 +255,7 @@ cpu-state-varible M.x86.mode. There are several potential states: gs segment override ss segment override - ds/ss select (in absense of override) + ds/ss select (in absence of override) Each of the above 7 items are handled with a bit in the mode field. ****************************************************************************/ diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index 6917a08..c805b58 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -39,7 +39,7 @@ * to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * -* Each opcode proc has a comment preceeding it which gives it's table +* Each opcode proc has a comment preceding it which gives it's table * address. Several opcodes are missing (undefined) in the table. * * Each proc includes information for decoding (DECODE_PRINTF and @@ -2530,7 +2530,7 @@ static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -2577,7 +2577,7 @@ static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -2773,7 +2773,7 @@ static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); @@ -2820,7 +2820,7 @@ static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -2858,7 +2858,7 @@ static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) else inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { M.x86.R_AL = fetch_data_byte(M.x86.R_SI); @@ -2905,7 +2905,7 @@ static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* move them until (E)CX is ZERO. */ count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; M.x86.R_CX = 0; @@ -4075,7 +4075,7 @@ static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) END_OF_INSTR(); } -/* instuctions D8 .. DF are in i87_ops.c */ +/* Instructions D8 .. DF are in i87_ops.c */ /**************************************************************************** REMARKS: diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 20e7597..e73f217 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -134,7 +134,7 @@ static u32 x86emu_parity_tab[8] = /**************************************************************************** REMARKS: -implements side efects for byte operations that don't overflow +implements side effects for byte operations that don't overflow ****************************************************************************/ static void set_parity_flag(u32 res) @@ -790,7 +790,7 @@ u8 rcl_byte(u8 d, u8 s) /* OVERFLOW is set *IFF* cnt==1, then it is the xor of CF and the most significant bit. Blecck. */ /* parenthesized this expression since it appears to - be causing OF to be misset */ + be causing OF to be missed */ CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), F_OF); @@ -1800,7 +1800,7 @@ void test_byte(u8 d, u8 s) CLEAR_FLAG(F_OF); set_szp_flags_8((u8)res); - /* AF == dont care */ + /* AF == don't care */ CLEAR_FLAG(F_CF); } @@ -1816,7 +1816,7 @@ void test_word(u16 d, u16 s) CLEAR_FLAG(F_OF); set_szp_flags_16((u16)res); - /* AF == dont care */ + /* AF == don't care */ CLEAR_FLAG(F_CF); } @@ -1832,7 +1832,7 @@ void test_long(u32 d, u32 s) CLEAR_FLAG(F_OF); set_szp_flags_32(res); - /* AF == dont care */ + /* AF == don't care */ CLEAR_FLAG(F_CF); } @@ -2311,7 +2311,7 @@ void ins(int size) inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* in until (E)CX is ZERO. */ u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX); @@ -2353,7 +2353,7 @@ void outs(int size) inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ + /* don't care whether REPE or REPNE */ /* out until (E)CX is ZERO. */ u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX); diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index b3b3cd7..9785a9d 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -35,7 +35,7 @@ * Description: This file includes subroutines which are related to * programmed I/O and memory access. Included in this module * are default functions with limited usefulness. For real -* uses these functions will most likely be overriden by the +* uses these functions will most likely be overridden by the * user library. * ****************************************************************************/ @@ -381,7 +381,7 @@ PARAMETERS: int - New software interrupt to prepare for REMARKS: -This function is used to set up the emulator state to exceute a software +This function is used to set up the emulator state to execute a software interrupt. This can be used by the user application code to allow an interrupt to be hooked, examined and then reflected back to the emulator so that the code in the emulator will continue processing the software diff --git a/src/device/oprom/x86emu/x86emui.h b/src/device/oprom/x86emu/x86emui.h index e34a1ba..37339d5 100644 --- a/src/device/oprom/x86emu/x86emui.h +++ b/src/device/oprom/x86emu/x86emui.h @@ -33,7 +33,7 @@ * Developer: Kendall Bennett * * Description: Header file for system specific functions. These functions -* are always compiled and linked in the OS depedent libraries, +* are always compiled and linked in the OS dependent libraries, * and never in a binary portable driver. * ****************************************************************************/ diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index f42d4e1..d27a5f1 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -219,7 +219,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad my_wrb(0x000ffe6e, 0xcf); // setup BIOS Data Area (0000:04xx, or 0040:00xx) - // we currently 0 this area, meaning "we dont have + // we currently 0 this area, meaning "we don't have // any hardware" :-) no serial/parallel ports, floppys, ... memset(biosmem + 0x400, 0x0, 0x100); @@ -388,7 +388,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad */ if ((pop_word() == 0xf4f4) && (M.x86.R_SS == STACK_SEGMENT) && (M.x86.R_SP == STACK_START_OFFSET)) { - DEBUG_PRINTF("Stack is clean, initialization successfull!\n"); + DEBUG_PRINTF("Stack is clean, initialization successful!\n"); } else { printf("Stack unclean, initialization probably NOT COMPLETE!\n"); DEBUG_PRINTF("SS:SP = %04x:%04x, expected: %04x:%04x\n", diff --git a/src/device/oprom/yabel/biosemu.h b/src/device/oprom/yabel/biosemu.h index 4f5c4aa..69e1fc3 100644 --- a/src/device/oprom/yabel/biosemu.h +++ b/src/device/oprom/yabel/biosemu.h @@ -24,7 +24,7 @@ #define VBE_SEGMENT 0x3000 #define PMM_CONV_SEGMENT 0x4000 // 4000:xxxx is PMM conventional memory area, extended memory area - // will be anything beyound MIN_REQUIRED_MEMORY_SIZE + // will be anything beyond MIN_REQUIRED_MEMORY_SIZE #define PNP_DATA_SEGMENT 0x5000 #define OPTION_ROM_CODE_SEGMENT 0xc000 @@ -38,9 +38,9 @@ // Address, there will only be a call to this INT and a RETF #define PNP_INT_NUM 0xFD -/* array of funtion pointers to override generic interrupt handlers +/* array of function pointers to override generic interrupt handlers * a YABEL caller can add functions to this array before calling YABEL - * if a interrupt occurs, YABEL checks wether a function is set in + * if a interrupt occurs, YABEL checks whether a function is set in * this array and only runs the generic interrupt handler code, if * the function pointer is NULL */ typedef int (* yabel_handleIntFunc)(void); diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index f693d7b..1b2d011 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -10,7 +10,7 @@ ****************************************************************************/ /* this file contains functions provided by SLOF, that the current biosemu implementation needs - * they should go away inthe future... + * they should go away in the future... */ #include <types.h> diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index b09f50e..2f41847 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -60,7 +60,7 @@ biosemu_dev_get_addr_info(void) r->index; translate_address_array[taa_index].address = r->base; translate_address_array[taa_index].size = r->size; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; } @@ -71,7 +71,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0x30; translate_address_array[taa_index].address = bios_device.img_addr; translate_address_array[taa_index].size = 0; /* TODO: do we need the size? */ - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; /* legacy ranges if its a VGA card... */ @@ -84,7 +84,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = 0x3b0; translate_address_array[taa_index].size = 0xc; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; /* I/O 0x3C0-0x3DF */ @@ -94,7 +94,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = 0x3c0; translate_address_array[taa_index].size = 0x20; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; /* Mem 0xA0000-0xBFFFF */ @@ -104,7 +104,7 @@ biosemu_dev_get_addr_info(void) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = 0xa0000; translate_address_array[taa_index].size = 0x20000; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; taa_index++; } @@ -130,7 +130,7 @@ void translate_address_dev(u64 *, phandle_t); u64 get_puid(phandle_t node); -// scan all adresses assigned to the device ("assigned-addresses" and "reg") +// scan all addresses assigned to the device ("assigned-addresses" and "reg") // store in translate_address_array for faster translation using dev_translate_address void biosemu_dev_get_addr_info(void) @@ -171,7 +171,7 @@ biosemu_dev_get_addr_info(void) len = of_getprop(bios_device.phandle, "reg", buf, sizeof(buf)); for (i = 0; i < (len / sizeof(assigned_address_t)); i++) { if ((buf[i].size == 0) || (buf[i].cfg_space_offset != 0)) { - // we dont care for ranges with size 0 and + // we don't care for ranges with size 0 and // BARs and Expansion ROM must be in assigned-addresses... so in reg // we only look for those without config space offset set... // i.e. the legacy ranges @@ -211,7 +211,7 @@ biosemu_dev_get_addr_info(void) // "special memory" is a hack to make some parts of memory fall through to real memory // (ie. no translation). Necessary if option ROMs attempt DMA there, map registers or -// do similarily crazy things. +// do similarly crazy things. void biosemu_add_special_memory(u32 start, u32 size) { @@ -222,7 +222,7 @@ biosemu_add_special_memory(u32 start, u32 size) translate_address_array[taa_index].cfg_space_offset = 0; translate_address_array[taa_index].address = start; translate_address_array[taa_index].size = size; - /* dont translate addresses... all addresses are 1:1 */ + /* don't translate addresses... all addresses are 1:1 */ translate_address_array[taa_index].address_offset = 0; } @@ -443,7 +443,7 @@ biosemu_dev_translate_address(int type, unsigned long * addr) int i = 0; translate_address_t ta; #if !CONFIG_PCI_OPTION_ROM_RUN_YABEL - /* we dont need this hack for coreboot... we can access legacy areas */ + /* we don't need this hack for coreboot... we can access legacy areas */ //check if it is an access to legacy VGA Mem... if it is, map the address //to the vmem BAR and then translate it... // (translation info provided by Ben Herrenschmidt) diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index e5b4a3c..cf430be 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -243,7 +243,7 @@ handleInt16(void) // since we currently always read the char from the FW buffer, // we misuse the ring buffer, we use it as pointer to a u64 that stores // multi-byte keys (e.g. special keys in VT100 terminal) - // and as long as a key is available (not 0) we dont read further keys + // and as long as a key is available (not 0) we don't read further keys u64 *keycode = (u64 *) (M.mem_base + 0x41e); s8 c; // function number in AH @@ -538,7 +538,7 @@ handleInterrupt(int intNum) DEBUG_PRINTF_INTR("%s(%x)\n", __func__, intNum); #endif - /* check wether this interrupt has a function pointer set in yabel_intFuncArray and run that */ + /* check whether this interrupt has a function pointer set in yabel_intFuncArray and run that */ if (yabel_intFuncArray[intNum]) { DEBUG_PRINTF_INTR("%s(%x) intHandler overridden, calling it...\n", __func__, intNum); int_handled = (*yabel_intFuncArray[intNum])(); diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index d1172dc..94f610d 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -188,7 +188,7 @@ my_inb(X86EMU_pioAddr addr) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__, addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -238,7 +238,7 @@ my_inw(X86EMU_pioAddr addr) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__, addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -283,7 +283,7 @@ my_inl(X86EMU_pioAddr addr) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__, addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -329,7 +329,7 @@ my_outb(X86EMU_pioAddr addr, u8 val) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -361,7 +361,7 @@ my_outw(X86EMU_pioAddr addr, u16 val) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -402,7 +402,7 @@ my_outl(X86EMU_pioAddr addr, u32 val) unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_IO, &translated_addr); if (translated != 0) { - //translation successfull, access Device I/O (BAR or Legacy...) + //translation successful, access Device I/O (BAR or Legacy...) DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index 4b4a552..a7d0289 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -177,7 +177,7 @@ static inline void DEBUG_CHECK_VMEM_WRITE(u32 _addr, u32 _val) {}; static void update_time(u32 cur_val) { - //for convenience, we let the start of timebase be at midnight, we currently dont support + //for convenience, we let the start of timebase be at midnight, we currently don't support //real daytime anyway... u64 ticks_per_day = tb_freq * 60 * 24; // at 18Hz a period is ~55ms, converted to ticks (tb_freq is ticks/second) @@ -202,7 +202,7 @@ my_rdb(u32 addr) u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); u8 rval; if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%08x): access to VGA Memory\n", __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -234,7 +234,7 @@ my_rdw(u32 addr) u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); u16 rval; if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%08x): access to VGA Memory\n", __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -285,7 +285,7 @@ my_rdl(u32 addr) u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); u32 rval; if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%x): access to VGA Memory\n", __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); diff --git a/src/device/oprom/yabel/pmm.c b/src/device/oprom/yabel/pmm.c index 19d14d4..d6c528d 100644 --- a/src/device/oprom/yabel/pmm.c +++ b/src/device/oprom/yabel/pmm.c @@ -222,7 +222,7 @@ void pmm_handleInt() DEBUG_PRINTF_PMM("%s: pmmDeallocate: PMM segment offset: %x\n", __func__, buffer); i = 0; - /* rval = 0 means we deallocated the buffer, so set it to 1 in case we dont find it and + /* rval = 0 means we deallocated the buffer, so set it to 1 in case we don't find it and * thus cannot deallocate */ rval = 1; diff --git a/src/device/oprom/yabel/pmm.h b/src/device/oprom/yabel/pmm.h index 3cc3c17..6416c11 100644 --- a/src/device/oprom/yabel/pmm.h +++ b/src/device/oprom/yabel/pmm.h @@ -24,9 +24,9 @@ typedef struct { u8 checksum; u32 entry_point_offset; u8 reserved[5]; - /* Code is not part of the speced PMM struct, however, since I cannot - * put the handling of PMM in the virtual memory (I dont want to hack it - * together in x86 assembly ;-)) this code array is pointed to by + /* Code is not part of the specced PMM struct, however, since I cannot + * put the handling of PMM in the virtual memory (I don't want to hack + * it together in x86 assembly ;-)) this code array is pointed to by * entry_point_offset, in code there is only a INT call and a RETF, * thus every PMM call will issue a PMM INT (only defined in YABEL, * see interrupt.c) and the INT Handler will do the actual PMM work. diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 5952dae..8658b77 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -103,7 +103,7 @@ vbe_info(vbe_info_t * info) // offset 4: 16bit le containing VbeVersion info->version = in16le(vbe_info_buffer + 4); - // offset 6: 32bit le containg segment:offset of OEM String in virtual Mem. + // offset 6: 32bit le containing segment:offset of OEM String in virtual Mem. info->oem_string_ptr = biosmem + ((in16le(vbe_info_buffer + 8) << 4) + in16le(vbe_info_buffer + 6)); @@ -457,7 +457,7 @@ vbe_get_info(void) // as input, it must contain a screen_info_input_t with the following content: // byte[0:3] = "DDC\0" (zero-terminated signature header) // byte[4:5] = reserved space for the return struct... just in case we ever change - // the struct and dont have reserved enough memory (and let's hope the struct + // the struct and don't have reserved enough memory (and let's hope the struct // never gets larger than 64KB) // byte[6] = monitor port number for DDC requests ("only" one byte... so lets hope we never have more than 255 monitors... // byte[7:8] = max. screen width (OF may want to limit this)

1 0

New patch to review for coreboot: 61d6af3 cpu: Fix spelling
by Martin Roth 09 Jul '13

09 Jul '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3729 -gerrit commit 61d6af319a582e204624522f20a40bf1a578a0fd Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 8 16:23:54 2013 -0600 cpu: Fix spelling Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/cpu/amd/car/post_cache_as_ram.c | 4 ++-- src/cpu/amd/dualcore/amd_sibling.c | 4 ++-- src/cpu/amd/geode_gx2/cpubug.c | 6 +++--- src/cpu/amd/geode_gx2/cpureginit.c | 4 ++-- src/cpu/amd/geode_lx/cpubug.c | 2 +- src/cpu/amd/model_10xxx/defaults.h | 2 +- src/cpu/amd/model_10xxx/fidvid.c | 6 +++--- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 2 +- src/cpu/amd/model_fxx/powernow_acpi.c | 6 +++--- src/cpu/amd/mtrr/amd_mtrr.c | 4 ++-- src/cpu/amd/quadcore/amd_sibling.c | 4 ++-- src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/intel/haswell/haswell_init.c | 10 +++++----- src/cpu/intel/haswell/mp_init.c | 8 ++++---- src/cpu/intel/haswell/smmrelocate.c | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++-- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/slot_1/l2_cache.c | 6 +++--- src/cpu/samsung/exynos5-common/clk.h | 6 +++--- src/cpu/samsung/exynos5-common/exynos-tmu.c | 4 ++-- src/cpu/samsung/exynos5-common/exynos-tmu.h | 2 +- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 8 ++++---- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 4 ++-- src/cpu/samsung/exynos5-common/spi.c | 4 ++-- src/cpu/samsung/exynos5-common/sromc.c | 2 +- src/cpu/samsung/exynos5250/clk.h | 4 ++-- src/cpu/samsung/exynos5250/clock.c | 8 ++++---- src/cpu/samsung/exynos5250/cpu.c | 2 +- src/cpu/samsung/exynos5250/dmc.h | 2 +- src/cpu/samsung/exynos5250/dmc_common.c | 6 +++--- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 6 +++--- src/cpu/samsung/exynos5250/fimd.h | 4 ++-- src/cpu/samsung/exynos5250/pinmux.c | 4 ++-- src/cpu/samsung/exynos5250/setup.h | 4 ++-- src/cpu/samsung/exynos5250/uart.c | 4 ++-- src/cpu/ti/am335x/uart.c | 2 +- src/cpu/ti/am335x/uart.h | 4 ++-- src/cpu/via/nano/update_ucode.c | 4 ++-- src/cpu/via/nano/update_ucode.h | 4 ++-- src/cpu/x86/car.c | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 4 ++-- src/cpu/x86/mtrr/mtrr.c | 18 +++++++++--------- src/cpu/x86/smm/smm_module_loader.c | 14 +++++++------- 46 files changed, 107 insertions(+), 107 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 68e7c09..18c278e 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -88,7 +88,7 @@ static void post_cache_as_ram(void) #endif #if 1 { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ unsigned v_esp; __asm__ volatile ( "movl %%esp, %0\n\t" @@ -123,7 +123,7 @@ static void post_cache_as_ram(void) /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%esp\n\t" ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) - /* discard all registers (eax is used for %0), so gcc redo everything + /* discard all registers (eax is used for %0), so gcc redoes everything after the stack is moved */ : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" ); diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 13b9e37..b3df0a3 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -91,10 +91,10 @@ unsigned get_apicid_base(unsigned ioapic_num) } #endif - //contruct apicid_base + //Construct apicid_base if((!disable_siblings) && (siblings>0) ) { - /* for 8 way dual core, we will used up apicid 16:16, actualy 16 is not allowed by current kernel + /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */ diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index 54d7e0e..eddc924 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -163,7 +163,7 @@ static void eng2900(void) * clocks when CPU is snooped. Because setting XSTATE to 0 * overrides any other XSTATE action, the code will always * stall for 4 GeodeLink clocks after a snoop request goes - * away even if it occured a clock or two later than a + * away even if it occurred a clock or two later than a * different snoop; the stall signal will never 'glitch high' * for only one or two CPU clocks with this code. */ @@ -201,7 +201,7 @@ static void eng2900(void) msr.lo = 0x30000; wrmsr(MSR_GLCP + 0x0073, msr); - /* Writing action number 5: STALL_CPU_PIPE when exitting idle + /* Writing action number 5: STALL_CPU_PIPE when exiting idle state or not in idle state */ msr.hi = 0; msr.lo = 0x00430000; @@ -293,7 +293,7 @@ static void bug118339(void) * * PBZ 3659: * The MC reordered transactions incorrectly and breaks coherency. - * Disable reording and take a potential performance hit. + * Disable reordering and take a potential performance hit. * This is safe to do here and not in MC init since there is nothing * to maintain coherency with and the cache is not enabled yet. */ diff --git a/src/cpu/amd/geode_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c index 0fc852d..e0ecd62 100644 --- a/src/cpu/amd/geode_gx2/cpureginit.c +++ b/src/cpu/amd/geode_gx2/cpureginit.c @@ -15,7 +15,7 @@ void cpuRegInit (void) /* Set up GLCP to grab BTM data. */ msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; - msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */ + msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ /* Turn off debug clock */ @@ -119,7 +119,7 @@ void cpuRegInit (void) wrmsr(msrnum, msr); } -/* FPU impercise exceptions bit */ +/* FPU imprecise exceptions bit */ { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index 4110454..ebadec7 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -67,7 +67,7 @@ static void pcideadlock(void) /***/ /** PBZ 3659:*/ /** The MC reordered transactions incorrectly and breaks coherency.*/ -/** Disable reording and take a potential performance hit.*/ +/** Disable reordering and take a potential performance hit.*/ /** This is safe to do here and not in MC init since there is nothing*/ /** to maintain coherency with and the cache is not enabled yet.*/ /***/ diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index f7b8b2f..3d33dda 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -54,7 +54,7 @@ static const struct { { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR, 0x00000000, 0x00000000, - 0x00000000, 0x00000C00 }, /* Errata 326 */ + 0x00000000, 0x00000C00 }, /* Erratum 326 */ { NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 0x00000000, 1 << 22, diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index ebe44dd..4297c90 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -68,7 +68,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 9.- TODO Requires information on current delivery capability (depends on mainboard and maybe power supply ?). One might use a config - option with the maximum number of Ampers that the board can deliver to CPU. + option with the maximum number of Amperes that the board can deliver to CPU. 10.- [Multiprocessor] TODO 2.4.2.12 [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, @@ -79,7 +79,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway) 12.- generate ACPI for p-states. FIXME - Needs more assesment. There's some kind of fixed support that + Needs more assessment. There's some kind of fixed support that does not seem to depend on CPU revision or actual MSRC001_00[68:64] as BKDG apparently requires. http://www.coreboot.org/ACPI#CPU_Power_Management @@ -935,7 +935,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) static void finalPstateChange(void) { - /* Enble P0 on all cores for best performance. + /* Enable P0 on all cores for best performance. * Linux can slow them down later if need be. * It is safe since they will be in C1 halt * most of the time anyway. diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 3d5ddcf..eb047b8 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -424,7 +424,7 @@ static void start_node(u8 node) /** * static void setup_remote_node(u32 node) * - * Copy the BSP Adress Map to each AP. + * Copy the BSP Address Map to each AP. */ static void setup_remote_node(u8 node) { diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 06ff636..e68611b 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -496,7 +496,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) continue; if ((readback & 0xff) == 2) { timeout = 0; - break; /* target ap is stage 2, it's FID has beed set */ + break; /* target ap is stage 2, its FID has been set */ } } @@ -603,7 +603,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* For all APs ( We know the APIC ID of all AP even the APIC ID is lifted) * send signal to the AP it could change it's fid/vid */ - /* remote read singnal from AP that AP is done */ + /* remote read signal from AP that AP is done */ fv.common_fidvid &= 0xffff00; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index a18b982..42c6f95 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -509,7 +509,7 @@ static void model_fxx_init(device_t dev) id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set - /* Is this a bad location? In particular can another node prefecth + /* Is this a bad location? In particular can another node prefetch * data from this node before we have initialized it? */ if (id.coreid == 0) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 820d426..af1e24b 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -75,7 +75,7 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid #if CONFIG_K8_REV_F_SUPPORT /* -* Details about this algorithm , refert to BDKG 10.5.1 +* Details about this algorithm , refer to BDKG 10.5.1 * Two parts are included, the another is the DSDT reconstruction process */ @@ -202,7 +202,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) goto write_pstates; } - /* Get the multipier of the fid frequency */ + /* Get the multiplier of the fid frequency */ /* * Fid multiplier is always 100 revF and revG. */ @@ -316,7 +316,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_num++; } - /* Constuct P[Min] State */ + /* Construct P[Min] State */ if (Max_fid == 0x2A && Max_vid != 0x0) { Pstate_fid[Pstate_num] = 0x2; Pstate_feq[Pstate_num] = diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 2f3e6e3..033ec53 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -128,10 +128,10 @@ void amd_setup_mtrrs(void) } /* Now that I have mapped what is memory and what is not - * Setup the mtrrs so we can cache the memory. + * Set up the mtrrs so we can cache the memory. */ - // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need + // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need // variable MTRR to span memory above 4GB // Lower revisions K8 need variable MTRR over 4GB x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1); diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index e0d173d..d653a85 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -95,10 +95,10 @@ u32 get_apicid_base(u32 ioapic_num) nb_cfg_54 = read_nb_cfg_54(); - //contruct apicid_base + //Construct apicid_base if((!disable_siblings) && (siblings>0) ) { - /* for 8 way dual core, we will used up apicid 16:16, actualy + /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4a739a9..ac082b8 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -169,7 +169,7 @@ void smm_initiate_relocation(void); void smm_initiate_relocation_parallel(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); -/* Returns 0 on succes. < 0 on failure. */ +/* Returns 0 on success. < 0 on failure. */ int setup_ap_init(struct bus *cpu_bus, int *max_cpus, const void *microcode_patch); /* Returns 0 on success, < 0 on failure. */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 0bf98ec..43bf96a 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -40,7 +40,7 @@ #include "chip.h" /* - * List of suported C-states in this processor + * List of supported C-states in this processor * * Latencies are typical worst-case package exit time in uS * taken from the SandyBridge BIOS specification. @@ -325,7 +325,7 @@ static void configure_thermal_target(void) return; conf = lapic->chip_info; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); @@ -509,8 +509,8 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) int num_aps; const void *microcode_patch; - /* Perform any necesarry BSP initialization before APs are brought up. - * This call alos allows the BSP to prepare for any secondary effects + /* Perform any necessary BSP initialization before APs are brought up. + * This call also allows the BSP to prepare for any secondary effects * from calling cpu_initialize() such as smm_init(). */ bsp_init_before_ap_bringup(cpu_bus); @@ -530,7 +530,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) } if (smm_initialize()) { - printk(BIOS_CRIT, "SMM Initialiazation failed...\n"); + printk(BIOS_CRIT, "SMM Initialization failed...\n"); return; } diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 1358418..51130a5 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -78,7 +78,7 @@ static device_t cpu_devs[CONFIG_MAX_CPUS]; static atomic_t num_aps; /* Number of APs that have relocated their SMM handler. */ static atomic_t num_aps_relocated_smm; -/* Barrier to stop APs from performing SMM relcoation. */ +/* Barrier to stop APs from performing SMM relocation. */ static int smm_relocation_barrier_begin __attribute__ ((aligned (64))); /* Determine if hyperthreading is disabled. */ int ht_disabled; @@ -145,7 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel) /* The mtrr code sets up ROM caching on the BSP, but not the others. However, * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for tha APs before going to sleep. */ + * ensure the caching is disabled for the APs before going to sleep. */ static void cleanup_rom_caching(void) { x86_mtrr_disable_rom_caching(); @@ -178,7 +178,7 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) ap_initiate_smm_relocation(); - /* Indicate that SMM relocation has occured on this thread. */ + /* Indicate that SMM relocation has occurred on this thread. */ atomic_inc(&num_aps_relocated_smm); /* After SMM relocation a 2nd microcode load is required. */ @@ -401,7 +401,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads) /* Allocate the new cpu device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); if (new == NULL) { - printk(BIOS_CRIT, "Could not allocte cpu device\n"); + printk(BIOS_CRIT, "Could not allocate cpu device\n"); max_cpus--; } cpu_devs[i] = new; diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 4fe6489..3f4f45a 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -348,7 +348,7 @@ static void setup_ied_area(struct smm_relocation_params *params) memset(ied_base + (1 << 20), 0, (32 << 10)); /* According to the BWG MP init section 2MiB of memory at IEDBASE + - * 2MiB should be zeroed as well. However, I suspect what is inteneded + * 2MiB should be zeroed as well. However, I suspect what is intended * is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */ //memset(ied_base + (2 << 20), 0, (2 << 20)); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f430276..8b8dfe3 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -40,7 +40,7 @@ #include "chip.h" /* - * List of suported C-states in this processor + * List of supported C-states in this processor * * Latencies are typical worst-case package exit time in uS * taken from the SandyBridge BIOS specification. @@ -250,7 +250,7 @@ static void configure_thermal_target(void) return; conf = lapic->chip_info; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 6bf158e..1cb87c9 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -40,7 +40,7 @@ #include "chip.h" /* - * List of suported C-states in this processor + * List of supported C-states in this processor * * Latencies are typical worst-case package exit time in uS * taken from the SandyBridge BIOS specification. @@ -375,7 +375,7 @@ static void configure_thermal_target(void) return; conf = lapic->chip_info; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index eca0c89..a974d24 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -34,7 +34,7 @@ */ /* This code is ported from coreboot v1. - * The L2 cache initalization sequence here only apply to SECC/SECC2 P6 family + * The L2 cache initialization sequence here only apply to SECC/SECC2 P6 family * CPUs with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. * It is not required for Coppermine (68x) and Tualatin (6bx) cores. * It is currently not known if Celerons with Mendocino (66x) core require the @@ -295,7 +295,7 @@ int write_l2(u32 address, u32 data) // data1 = ffffffff // data2 = 000000dc // address = 00aaaaaa - // Final address signalled: + // Final address signaled: // 000fffff fff000c0 000dcaaa aaa00000 data1 = data & 0xff; data1 = data1 << 21; @@ -343,7 +343,7 @@ int test_l2_address_alias(u32 address1, u32 address2, /* Calculates the L2 cache size. * - * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual + * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. * */ diff --git a/src/cpu/samsung/exynos5-common/clk.h b/src/cpu/samsung/exynos5-common/clk.h index 9de4f45..071a39a 100644 --- a/src/cpu/samsung/exynos5-common/clk.h +++ b/src/cpu/samsung/exynos5-common/clk.h @@ -59,11 +59,11 @@ unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); /** - * get the clk frequency of the required peripherial + * get the clk frequency of the required peripheral * - * @param peripherial Peripherial id + * @param peripheral Peripheral id * - * @return frequency of the peripherial clk + * @return frequency of the peripheral clk */ unsigned long clock_get_periph_rate(enum periph_id peripheral); diff --git a/src/cpu/samsung/exynos5-common/exynos-tmu.c b/src/cpu/samsung/exynos5-common/exynos-tmu.c index 26777fc..9ad6a99 100644 --- a/src/cpu/samsung/exynos5-common/exynos-tmu.c +++ b/src/cpu/samsung/exynos5-common/exynos-tmu.c @@ -49,8 +49,8 @@ /* * After reading temperature code from register, compensating - * its value and calculating celsius temperatue, - * get current temperatue. + * its value and calculating celsius temperature, + * get current temperature. * * @return current temperature of the chip as sensed by TMU */ diff --git a/src/cpu/samsung/exynos5-common/exynos-tmu.h b/src/cpu/samsung/exynos5-common/exynos-tmu.h index 40eda56..2929e4a 100644 --- a/src/cpu/samsung/exynos5-common/exynos-tmu.h +++ b/src/cpu/samsung/exynos5-common/exynos-tmu.h @@ -63,7 +63,7 @@ enum tmu_status_t { TMU_STATUS_TRIPPED, }; -/* Tmeperature threshold values for various thermal events */ +/* Temperature threshold values for various thermal events */ struct temperature_params { /* minimum value in temperature code range */ unsigned int min_val; diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 4df848d..afadfb8 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -20,7 +20,7 @@ #define MAX_CR_LOOP 5 #define MAX_EQ_LOOP 4 -/* Link tare type */ +/* Link rate type */ enum link_rate { LINK_RATE_1_62GBPS = 0x06, LINK_RATE_2_70GBPS = 0x0a @@ -125,7 +125,7 @@ typedef struct vidinfo { */ void s5p_dp_reset(struct s5p_dp_device *dp); /* - * Initialize DP to recieve video stream + * Initialize DP to receive video stream * * param dp pointer to main s5p-dp structure */ @@ -213,8 +213,8 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp); * * param dp pointer to main s5p-dp structure * param type clock_recovery_m_value_type - * param m_value to caluculate m_vid value - * param n_value to caluculate n_vid value + * param m_value to calculate m_vid value + * param n_value to calculate n_vid value */ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, enum clock_recovery_m_value_type type, diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index cce8c6d..c8e7d47 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -82,7 +82,7 @@ void s5p_dp_reset(struct s5p_dp_device *dp) /* Set interrupt pin assertion polarity as high */ writel(INT_POL0 | INT_POL1, &base->int_ctl); - /* Clear pending regisers */ + /* Clear pending registers */ writel(0xff, &base->common_int_sta_1); writel(0x4f, &base->common_int_sta_2); writel(0xe0, &base->common_int_sta_3); @@ -147,7 +147,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; - /* Clear inerrupts related to AUX channel */ + /* Clear interrupts related to AUX channel */ reg = RPLY_RECEIV | AUX_ERR; writel(reg, &base->dp_int_sta); diff --git a/src/cpu/samsung/exynos5-common/spi.c b/src/cpu/samsung/exynos5-common/spi.c index 33f4d99..92a29a4 100644 --- a/src/cpu/samsung/exynos5-common/spi.c +++ b/src/cpu/samsung/exynos5-common/spi.c @@ -47,7 +47,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); unsigned int out_bytes, in_bytes; - // TODO In currrent implementation, every read/write must be aligned to + // TODO In current implementation, every read/write must be aligned to // 4 bytes, otherwise you may get timeout or other unexpected results. assert(todo % 4 == 0); @@ -95,7 +95,7 @@ int exynos_spi_open(struct exynos_spi *regs) SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ - /* clear rx and tx channel if set priveously */ + /* clear rx and tx channel if set previously */ clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); setbits_le32(&regs->swap_cfg, diff --git a/src/cpu/samsung/exynos5-common/sromc.c b/src/cpu/samsung/exynos5-common/sromc.c index 7bc93e7..20c9a03 100644 --- a/src/cpu/samsung/exynos5-common/sromc.c +++ b/src/cpu/samsung/exynos5-common/sromc.c @@ -29,7 +29,7 @@ * s5p_config_sromc() - select the proper SROMC Bank and configure the * band width control and bank control registers * srom_bank - SROM - * srom_bw_conf - SMC Band witdh reg configuration value + * srom_bw_conf - SMC Bandwidth reg configuration value * srom_bc_conf - SMC Bank Control reg configuration value */ void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 828e7d8..6b2c709 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -31,7 +31,7 @@ #define MCT_HZ 24000000 /* - * Set mshci controller instances clock drivder + * Set mshci controller instances clock divider * * @param enum periph_id instance of the mshci controller * @@ -482,7 +482,7 @@ struct exynos5_mct_regs { }; #define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ -#define EPLL_SRC_CLOCK 24000000 /*24 MHz Cristal Input */ +#define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */ #define TIMEOUT_EPLL_LOCK 1000 #define AUDIO_0_RATIO_MASK 0x0f diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 3622e28..b97afa6 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -165,7 +165,7 @@ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { {24, 1, 20, -1}, /* PERIPH_ID_SATA */ }; -/* Epll Clock division values to achive different frequency output */ +/* Epll Clock division values to achieve different frequency output */ static struct st_epll_con_val epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, { 180000000, 0, 45, 3, 1, 0 }, @@ -410,7 +410,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) u32 *reg; /* - * For now we only handle a very small subset of peipherals here. + * For now we only handle a very small subset of peripherals here. * Others will need to (and do) mangle the clock registers * themselves, At some point it is hoped that this function can work * from a table or calculated register offset / mask. For now this @@ -659,7 +659,7 @@ int clock_epll_set_rate(unsigned long rate) epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to genarate a stable clock output. + * Required period ( in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ @@ -698,7 +698,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) unsigned int div ; if ((dst_frq == 0) || (src_frq == 0)) { - debug("%s: Invalid requency input for prescaler\n", __func__); + debug("%s: Invalid frequency input for prescaler\n", __func__); debug("src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 8bf0d49..07aa874 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -74,7 +74,7 @@ static void exynos_displayport_init(device_t dev) * * Note: We may want to do something clever to ensure the framebuffer * region is aligned such that we don't change dcache policy for other - * stuff inadvertantly. + * stuff inadvertently. * * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index 0814c07..9dcd2e6 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -311,7 +311,7 @@ struct mem_timings { uint8_t chips_per_channel; /* number of chips per channel */ uint8_t chips_to_configure; /* number of chips to configure */ uint8_t send_zq_init; /* 1 to send this command */ - unsigned int impedance; /* drive strength impedeance */ + unsigned int impedance; /* drive strength impedance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ }; diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index bcfc9fe..141ba18 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -69,7 +69,7 @@ int dmc_config_zq(struct mem_timings *mem, val &= ~ZQ_MANUAL_STR; /* - * Since we are manaully calibrating the ZQ values, + * Since we are manually calibrating the ZQ values, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; @@ -102,12 +102,12 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) writel(val, &dmc->phycontrol0); } - /* Update DLL Information: Force DLL Resyncronization */ + /* Update DLL Information: Force DLL Resynchronization */ val = readl(&dmc->phycontrol0); val |= FP_RSYNC; writel(val, &dmc->phycontrol0); - /* Reset Force DLL Resyncronization */ + /* Reset Force DLL Resynchronization */ val = readl(&dmc->phycontrol0); val &= ~FP_RSYNC; writel(val, &dmc->phycontrol0); diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 132471d..9be9866 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -147,9 +147,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), &dmc->concontrol); - /* Memory Channel Inteleaving Size */ + /* Memory Channel Interleaving Size */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Memory Channel Inteleaving Size\n"); + "Memory Channel Interleaving Size\n"); writel(mem->iv_size, &dmc->ivcontrol); /* Set DMC MEMCONTROL register */ @@ -169,7 +169,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Power Down mode Configuration */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Power Down mode Configuraation\n"); + "Power Down mode Configuration\n"); writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, &dmc->pwrdnconfig); diff --git a/src/cpu/samsung/exynos5250/fimd.h b/src/cpu/samsung/exynos5250/fimd.h index a46ad5a..c7a9b2a 100644 --- a/src/cpu/samsung/exynos5250/fimd.h +++ b/src/cpu/samsung/exynos5250/fimd.h @@ -85,11 +85,11 @@ struct exynos5_fimd_panel { unsigned int upper_margin; /* Vertical Backporch */ unsigned int lower_margin; /* Vertical frontporch */ unsigned int vsync; /* Vertical Sync Pulse Width */ - unsigned int left_margin; /* Horizantal Backporch */ + unsigned int left_margin; /* Horizontal Backporch */ unsigned int right_margin; /* Horizontal Frontporch */ unsigned int hsync; /* Horizontal Sync Pulse Width */ unsigned int xres; /* X Resolution */ - unsigned int yres; /* Y Resopultion */ + unsigned int yres; /* Y Resolution */ }; /* LCDIF Register Map */ diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c index becced2..52ef75d 100644 --- a/src/cpu/samsung/exynos5250/pinmux.c +++ b/src/cpu/samsung/exynos5250/pinmux.c @@ -85,7 +85,7 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags) break; case PERIPH_ID_SDMMC3: /* - * TODO: Need to add defintions for GPC4 before + * TODO: Need to add definitions for GPC4 before * enabling this. */ debug("SDMMC3 not supported yet"); @@ -141,7 +141,7 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags) gpio_cfg_pin(GPIO_Y10 + i, EXYNOS_GPIO_FUNC(2)); /* - * EBI: 8 Addrss Lines + * EBI: 8 Address Lines * * GPY3[0] EBI_ADDR[0](2) * GPY3[1] EBI_ADDR[1](2) diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index f205b4d..d6b3a53 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -664,7 +664,7 @@ struct exynos5_phy_control; #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ +#define FP_RSYNC (1 << 3) /* Force DLL resynchronization */ /* Driver strength for CK, CKE, CS & CA */ #define IMP_OUTPUT_DRV_40_OHM 0x5 @@ -679,7 +679,7 @@ struct exynos5_phy_control; struct mem_timings; -/* Errors that we can encourter in low-level setup */ +/* Errors that we can encounter in low-level setup */ enum { SETUP_ERR_OK, SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1, diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 34d8e08..11f4da1 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -62,7 +62,7 @@ static inline struct s5p_uart *s5p_get_base_uart(int dev_index) * The coefficient, used to calculate the baudrate on S5P UARTs is * calculated as * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT - * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, + * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1, * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: */ static const int udivslot[] = { @@ -158,7 +158,7 @@ static int exynos5_uart_err_check(int op) /* * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is + * otherwise. When the function is successful, the character read is * written into its argument c. */ static unsigned char exynos5_uart_rx_byte(void) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 395ed86..bd2ff44 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -147,7 +147,7 @@ static void am335x_uart_init_dev(void) /* * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is + * otherwise. When the function is successful, the character read is * written into its argument c. */ static unsigned char am335x_uart_rx_byte(void) diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 56d4c51..645cd43 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -130,7 +130,7 @@ struct am335x_uart { uint8_t rsvd_0x36[2]; uint16_t blr; /* BOF control */ uint8_t rsvd_0x3a[2]; - uint16_t acreg; /* auxilliary control */ + uint16_t acreg; /* auxiliary control */ uint8_t rsvd_0x3e[2]; /* 0x40 */ @@ -139,7 +139,7 @@ struct am335x_uart { uint16_t ssr; /* supplementary status */ uint8_t rsvd_0x46[2]; - uint16_t eblr; /* BOF length (operatoinal mode only) */ + uint16_t eblr; /* BOF length (operational mode only) */ uint8_t rsvd_0x4a[6]; /* 0x50 */ diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index d5757f8..7471928 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -37,7 +37,7 @@ static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) msr.hi = 0; wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); - /* Let's see if we updated succesfully */ + /* Let's see if we updated successfully */ msr = rdmsr(MSR_UCODE_UPDATE_STATUS); return msr.lo & 0x07; @@ -80,7 +80,7 @@ static void nano_print_ucode_status(ucode_update_status stat) switch(stat) { case UCODE_UPDATE_SUCCESS: - printk(BIOS_INFO, "Microcode update succesful.\n"); + printk(BIOS_INFO, "Microcode update successful.\n"); break; case UCODE_UPDATE_FAIL: printk(BIOS_ALERT, "Microcode update failed, bad environment." diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index 6a22d18..ae58fb2 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -56,11 +56,11 @@ typedef struct { u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ u32 checksum; /* Two's complement checksum of ucode+header */ u32 loader_revision; /* Revision of hardware ucode update loader*/ - u32 rfu_1; /* Reservod for future use */ + u32 rfu_1; /* Reserved for future use */ u32 payload_size; /* Size of the ucode payload only */ u32 total_size; /* Size of the ucode, including header */ char name[8]; /* ASCII string of ucode filename */ - u32 rfu_2; /* Reservod for future use */ + u32 rfu_2; /* Reserved for future use */ /* First double-word of the ucode payload * Its address represents the beginning of the ucode update we need to * send to the CPU */ diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 88f2807..87fa98b 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -33,7 +33,7 @@ extern char _car_data_end[]; /* * The car_migrated global variable determines if the cache-as-ram space has - * been migrated to real RAM. It does this by asumming the following things: + * been migrated to real RAM. It does this by assuming the following things: * 1. cache-as-ram space is zero'd out once it is set up. * 2. Either the cache-as-ram space is memory-backed after getting torn down * or the space returns 0xff's for each byte read. diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index fbc8aa4..a3bab46 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -40,7 +40,7 @@ * will return 0, meaning no CPU. * * We actually handling that case by noting which cpus startup - * and not telling anyone about the ones that dont. + * and not telling anyone about the ones that don't. */ /* Start-UP IPI vector must be 4kB aligned and below 1MB. */ diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 55dbd2f..f16da27 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -32,7 +32,7 @@ static void cache_ramstage(void) const int addr_det = 0; /* the fixed and variable MTTRs are power-up with random values, - * clear them to MTRR_TYPE_UNCACHEABLE for safty. + * clear them to MTRR_TYPE_UNCACHEABLE for safety. */ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) { @@ -43,7 +43,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) msr_t msr; const unsigned long *msr_addr; - /* Inialize all of the relevant msrs to 0 */ + /* Initialize all of the relevant msrs to 0 */ msr.lo = 0; msr.hi = 0; unsigned long msr_nr; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index b69787b..8f1c35e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -94,7 +94,7 @@ static inline unsigned int fms(unsigned int x) return r; } -/* fls: find least sigificant bit set */ +/* fls: find least significant bit set */ static inline unsigned int fls(unsigned int x) { int r; @@ -160,8 +160,8 @@ static struct memranges *get_physical_address_space(void) static struct memranges addr_space_storage; /* In order to handle some chipsets not being able to pre-determine - * uncacheable ranges, such as graphics memory, at resource inseration - * time remove unacheable regions from the cacheable ones. */ + * uncacheable ranges, such as graphics memory, at resource insertion + * time remove uncacheable regions from the cacheable ones. */ if (addr_space == NULL) { struct range_entry *r; unsigned long mask; @@ -216,7 +216,7 @@ static struct memranges *get_physical_address_space(void) } /* Fixed MTRR descriptor. This structure defines the step size and begin - * and end (exclusive) address covered by a set of fixe MTRR MSRs. + * and end (exclusive) address covered by a set of fixed MTRR MSRs. * It also describes the offset in byte intervals to store the calculated MTRR * type in an array. */ struct fixed_mtrr_desc { @@ -533,7 +533,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, struct range_entry *next; /* - * Determine MTRRs based on the following algoirthm for the given entry: + * Determine MTRRs based on the following algorithm for the given entry: * +------------------+ b2 = ALIGN_UP(end) * | 0 or more bytes | <-- hole is carved out between b1 and b2 * +------------------+ a2 = b1 = end @@ -571,7 +571,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, b1 = a2; - /* First check if a1 is >= 4GiB and the current etnry is the last + /* First check if a1 is >= 4GiB and the current entry is the last * entry. If so perform an optimization of covering a larger range * defined by the base address' alignment. */ if (a1 >= RANGE_4GB && next == NULL) { @@ -686,10 +686,10 @@ static int calc_var_mtrrs(struct memranges *addr_space, * 1. UC as default type with no holes at top of range. * 2. UC as default using holes at top of range. * 3. WB as default. - * The lowest count is then used as default after totalling all - * MTRRs. Note that the optimal algoirthm for UC default is marked in + * The lowest count is then used as default after totaling all + * MTRRs. Note that the optimal algorithm for UC default is marked in * the tag of each range regardless of final decision. UC takes - * precedence in the MTRR archiecture. Therefore, only holes can be + * precedence in the MTRR architecture. Therefore, only holes can be * used when the type of the region is MTRR_TYPE_WRBACK with * MTRR_TYPE_UNCACHEABLE as the default type. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 5eb4c5a..478ae8c 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -24,16 +24,16 @@ #include <console/console.h> /* - * Compoments that make up the SMRAM: + * Components that make up the SMRAM: * 1. Save state - the total save state memory used * 2. Stack - stacks for the CPUs in the SMM handler * 3. Stub - SMM stub code for calling into handler * 4. Handler - C-based SMM handler. * - * The compoents are assumed to consist of one consecutive region. + * The components are assumed to consist of one consecutive region. */ -/* These paramters are used by the SMM stub code. A pointer to the params +/* These parameters are used by the SMM stub code. A pointer to the params * is also passed to the C-base handler. */ struct smm_stub_params { u32 stack_size; @@ -80,7 +80,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, /* Each entry point has an IP value of 0x8000. The SMBASE for each * cpu is different so the effective address of the entry instruction - * is different. Therefore, the relative displacment for each entry + * is different. Therefore, the relative displacement for each entry * instruction needs to be updated to reflect the current effective * IP. Additionally, the IP result from the jmp instruction is * calculated using the next instruction's address so the size of @@ -140,7 +140,7 @@ static void smm_stub_place_staggered_entry_points(char *base, stub_entry_offset = rmodule_entry_offset(smm_stub); /* If there are staggered entry points or the stub is not located - * at the SMM entry point then jmp instructionss need to be placed. */ + * at the SMM entry point then jmp instructions need to be placed. */ if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { int num_entries; @@ -297,7 +297,7 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) return -1; /* Since the relocation handler always uses stack, adjust the number - * of conccurent stack users to be CONFIG_MAX_CPUS. */ + * of concurrent stack users to be CONFIG_MAX_CPUS. */ if (params->num_concurrent_stacks == 0) params->num_concurrent_stacks = CONFIG_MAX_CPUS; @@ -318,7 +318,7 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) * * It should be noted that this algorithm will not work for * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm - * expectes a region large enough to encompass the handler and stacks + * expects a region large enough to encompass the handler and stacks * as well as the SMM_DEFAULT_SIZE. */ int smm_load_module(void *smram, int size, struct smm_loader_params *params)

1 0

New patch to review for coreboot: 095f8fd console: Fix spelling
by Martin Roth 09 Jul '13

09 Jul '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3728 -gerrit commit 095f8fde1ffdf980dff56ce410f458b2ad4170d2 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 8 16:22:54 2013 -0600 console: Fix spelling Change-Id: I1fef27c4a16ee4358ace8014a8d6e9fa92c4f790 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/console/printk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/printk.c b/src/console/printk.c index 7549088..e24c752 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -1,5 +1,5 @@ /* - * blantantly copied from linux/kernel/printk.c + * blatantly copied from linux/kernel/printk.c * * Copyright (C) 1991, 1992 Linus Torvalds *

1 0

New patch to review for coreboot: 3cfd53e arch: Fix spelling
by Martin Roth 09 Jul '13

09 Jul '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3727 -gerrit commit 3cfd53e2c4b2830372c5c1f5827b279deee3b8f8 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 8 16:22:10 2013 -0600 arch: Fix spelling Change-Id: Ifea10f0180c0c4b684030a168402a95fadf1a9db Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/arch/armv7/include/armv7.h | 2 +- src/arch/armv7/include/assembler.h | 2 +- src/arch/x86/boot/acpi.c | 4 ++-- src/arch/x86/boot/tables.c | 2 +- src/arch/x86/include/arch/cpu.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/armv7/include/armv7.h b/src/arch/armv7/include/armv7.h index dc111c1..1473234 100644 --- a/src/arch/armv7/include/armv7.h +++ b/src/arch/armv7/include/armv7.h @@ -59,7 +59,7 @@ /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 - * However, we use the CP15 based instructtions because we use + * However, we use the CP15 based instructions because we use * -march=armv5 in U-Boot */ #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h index 5e4789b..7acf0f4 100644 --- a/src/arch/armv7/include/assembler.h +++ b/src/arch/armv7/include/assembler.h @@ -55,6 +55,6 @@ #endif /* - * Cache alligned + * Cache aligned */ #define CALGN(code...) code diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 3b77caa..96cb270 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -248,7 +248,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) } /* - * This can be overriden by platform ACPI setup code, if it calls + * This can be overridden by platform ACPI setup code, if it calls * acpi_create_ssdt_generator(). */ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator( @@ -763,7 +763,7 @@ void acpi_jump_to_wakeup(void *vector) #endif #if CONFIG_SMP - // FIXME: This should go into the ACPI backup memory, too. No pork saussages. + // FIXME: This should go into the ACPI backup memory, too. No pork sausages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 6355a1b..3cc2c6b 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -66,7 +66,7 @@ struct lb_memory *write_tables(void) rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyound 0x400. Only multiboot, GDT + * in case our data structures grow beyond 0x400. Only multiboot, GDT * and the coreboot table use low_tables. */ low_table_start = 0; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 7363132..6944834 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -8,7 +8,7 @@ */ #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ -#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */ #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */

1 0

New patch to review for coreboot: 98a14c1 usbdebug: Split endpoint buffers
by Kyösti Mälkki 09 Jul '13

09 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3726 -gerrit commit 98a14c163913120a66fca42ee9f5ad3f63bf539f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 8 18:11:44 2013 +0300 usbdebug: Split endpoint buffers Refactor the structure to better support receive and another set of endpoints over usbdebug. Change-Id: Ib0f76afdf4e638363ff30c67010920142c58f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/usbdebug.h | 45 +++++++++++++++++++----------- src/lib/usbdebug.c | 76 ++++++++++++++++++++++++++++++-------------------- 2 files changed, 74 insertions(+), 47 deletions(-) diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index e32410e..e0bd6c9 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -40,16 +40,27 @@ void pci_ehci_read_resources(struct device *dev); #endif #endif +struct dbgp_pipe +{ + u8 ep_index; + u8 bufidx; + char buf[8]; +}; + +#define DBGP_MAX_ENDPOINTS 4 +#define DBGP_CONSOLE_EPOUT 0 +#define DBGP_CONSOLE_EPIN 1 + struct ehci_debug_info { - void *ehci_caps; - void *ehci_regs; - void *ehci_debug; - u32 devnum; - u32 endpoint_out; - u32 endpoint_in; - char buf[8]; - u8 bufidx; - u8 status; + u8 devnum; + u8 endpoint[DBGP_MAX_ENDPOINTS]; + u8 ep_status[DBGP_MAX_ENDPOINTS]; + + void *ehci_caps; + void *ehci_regs; + void *ehci_debug; + + struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; }; #define DBGP_EP_VALID (1<<0) @@ -57,15 +68,15 @@ struct ehci_debug_info { #define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) void enable_usbdebug(unsigned int port); -int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); -int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); void set_debug_port(unsigned port); int usbdebug_init(void); -struct ehci_debug_info *dbgp_ehci_info(void); -#define dbgp_console_output dbgp_ehci_info -#define dbgp_console_input dbgp_ehci_info -int dbgp_ep_is_active(struct ehci_debug_info *dbg_info); -void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); -void usbdebug_tx_flush(struct ehci_debug_info *info); + +struct dbgp_pipe *dbgp_console_output(void); +struct dbgp_pipe *dbgp_console_input(void); +int dbgp_ep_is_active(struct dbgp_pipe *pipe); +int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size); +int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size); +void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data); +void usbdebug_tx_flush(struct dbgp_pipe *pipe); #endif diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index f3c0d05..e8a07eb 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -210,10 +210,11 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, return ret; } -int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size) +int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size) { + struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); return dbgp_bulk_write(dbg_info->ehci_debug, dbg_info->devnum, - dbg_info->endpoint_out, bytes, size); + dbg_info->endpoint[pipe->ep_index], bytes, size); } static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, @@ -247,10 +248,11 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, return ret; } -int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size) +int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size) { + struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, - dbg_info->endpoint_in, data, size, DBGP_LOOPS); + dbg_info->endpoint[pipe->ep_index], data, size, DBGP_LOOPS); } static void dbgp_mdelay(int ms) @@ -374,8 +376,6 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ struct ehci_caps *ehci_caps; struct ehci_regs *ehci_regs; struct ehci_dbg_port *ehci_debug; - unsigned dbgp_endpoint_out; - unsigned dbgp_endpoint_in; struct usb_debug_descriptor dbgp_desc; u32 cmd, ctrl, status, portsc, hcs_params; @@ -391,8 +391,12 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; - info->bufidx = 0; - info->status = 0; + + memset(&info->ep_pipe, 0, sizeof (info->ep_pipe)); + for (i=0; i<DBGP_MAX_ENDPOINTS; i++) { + info->ep_status[i] = 0; + info->ep_pipe[i].ep_index = i; + } try_next_time: port_map_tried = 0; @@ -511,8 +515,6 @@ try_next_port: ret = -6; goto err; } - dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint; - dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint; /* Move the device to 127 if it isn't already there */ if (devnum != USB_DEBUG_DEVNUM) { @@ -541,7 +543,7 @@ try_next_port: dbgp_printk("EHCI debug interface enabled.\n"); /* Perform a small write to get the even/odd data state in sync */ - ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_endpoint_out, "USB\r\n",5); + ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_desc.bDebugOutEndpoint, "USB\r\n",5); if (ret < 0) { dbgp_printk("dbgp_bulk_write failed: %d\n", ret); ret = -9; @@ -553,10 +555,11 @@ try_next_port: info->ehci_regs = ehci_regs; info->ehci_debug = ehci_debug; info->devnum = devnum; - info->endpoint_out = dbgp_endpoint_out; - info->endpoint_in = dbgp_endpoint_in; - info->status |= DBGP_EP_ENABLED | DBGP_EP_VALID; + info->endpoint[DBGP_CONSOLE_EPOUT] = dbgp_desc.bDebugOutEndpoint; + info->endpoint[DBGP_CONSOLE_EPIN] = dbgp_desc.bDebugInEndpoint; + info->ep_status[DBGP_CONSOLE_EPOUT] |= DBGP_EP_ENABLED | DBGP_EP_VALID; + info->ep_status[DBGP_CONSOLE_EPIN] |= DBGP_EP_ENABLED | DBGP_EP_VALID; return 0; err: /* Things didn't work so remove my claim */ @@ -581,22 +584,22 @@ next_debug_port: return -10; } -void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) +void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data) { - if (dbgp_is_ep_active(dbg_info)) { - dbg_info->buf[dbg_info->bufidx++] = data; - if (dbg_info->bufidx >= 8) { - dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); - dbg_info->bufidx = 0; + if (dbgp_ep_is_active(pipe)) { + pipe->buf[pipe->bufidx++] = data; + if (pipe->bufidx >= 8) { + dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); + pipe->bufidx = 0; } } } -void usbdebug_tx_flush(struct ehci_debug_info *dbg_info) +void usbdebug_tx_flush(struct dbgp_pipe *pipe) { - if (dbgp_is_ep_active(dbg_info) && dbg_info->bufidx > 0) { - dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); - dbg_info->bufidx = 0; + if (dbgp_ep_is_active(pipe) && pipe->bufidx > 0) { + dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); + pipe->bufidx = 0; } } @@ -605,6 +608,7 @@ static void usbdebug_re_enable(unsigned ehci_base) { struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); unsigned diff; + int i; if (!dbg_info->ehci_debug) return; @@ -613,13 +617,17 @@ static void usbdebug_re_enable(unsigned ehci_base) dbg_info->ehci_regs -= diff; dbg_info->ehci_debug -= diff; dbg_info->ehci_caps = (void*)ehci_base; - dbg_info->status |= DBGP_EP_ENABLED; + + for (i=0; i<DBGP_MAX_ENDPOINTS; i++) + dbg_info->ep_status[i] |= DBGP_EP_ENABLED; } static void usbdebug_disable(void) { struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); - dbg_info->status &= ~DBGP_EP_ENABLED; + int i; + for (i=0; i<DBGP_MAX_ENDPOINTS; i++) + dbg_info->ep_status[i] &= ~DBGP_EP_ENABLED; } static void pci_ehci_set_resources(struct device *dev) @@ -656,14 +664,22 @@ void pci_ehci_read_resources(struct device *dev) } #endif -int dbgp_ep_is_active(struct ehci_debug_info *dbg_info) +int dbgp_ep_is_active(struct dbgp_pipe *pipe) { - return (dbg_info->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); + struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); + return (dbg_info->ep_status[pipe->ep_index] & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); +} + +struct dbgp_pipe *dbgp_console_output(void) +{ + struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); + return &dbg_info->ep_pipe[DBGP_CONSOLE_EPOUT]; } -struct ehci_debug_info *dbgp_ehci_info(void) +struct dbgp_pipe *dbgp_console_input(void) { - return car_get_var_ptr(&glob_dbg_info); + struct ehci_debug_info *dbg_info = car_get_var_ptr(&glob_dbg_info); + return &dbg_info->ep_pipe[DBGP_CONSOLE_EPIN]; } int usbdebug_init(void)

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Patch set updated for coreboot: f0278ed usbdebug: Move ehci_debug_info allocation
by Kyösti Mälkki 09 Jul '13

09 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3625 -gerrit commit f0278edfde21bd854327a5342acfe66d655092ba Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 6 11:56:49 2013 +0300 usbdebug: Move ehci_debug_info allocation Move ehci_debug_info allocation from console to lib, as console code was only built for ramstage. Implement dbgp_ehci_info() to return the EHCI context. Alread alias this as dbgp_console_input() and _output() to return the console stream context later on. Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 4 +-- src/console/console.c | 3 +- src/console/usbdebug_console.c | 32 +++++++++----------- src/include/usbdebug.h | 6 ++-- src/lib/usbdebug.c | 47 +++++++++++++++-------------- src/northbridge/intel/sandybridge/raminit.c | 2 +- 6 files changed, 48 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 2013bb7..2e743ad 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -48,7 +48,7 @@ void console_tx_byte(unsigned char byte) uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif #if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); + usbdebug_tx_byte(dbgp_console_output(), byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -73,7 +73,7 @@ void console_tx_flush(void) ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); #endif #if CONFIG_USBDEBUG - usbdebug_tx_flush(0); + usbdebug_tx_flush(dbgp_console_output()); #endif } diff --git a/src/console/console.c b/src/console/console.c index 2f7de02..a24336b 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -104,8 +104,7 @@ void console_init(void) #if CONFIG_EARLY_CONSOLE #if CONFIG_USBDEBUG - enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); + usbdebug_init(); #endif #if CONFIG_CONSOLE_SERIAL uart_init(); diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index d674779..7b5dcc0 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -24,27 +24,28 @@ #include <device/pci.h> #include <pc80/mc146818rtc.h> -static struct ehci_debug_info dbg_info; static struct device_operations *ehci_drv_ops; static struct device_operations ehci_dbg_ops; static void usbdebug_re_enable(unsigned ehci_base) { + struct ehci_debug_info *dbg_info = dbgp_ehci_info(); unsigned diff; - if (!dbg_info.ehci_debug) + if (!dbg_info->ehci_debug) return; - diff = (unsigned)dbg_info.ehci_caps - ehci_base; - dbg_info.ehci_regs -= diff; - dbg_info.ehci_debug -= diff; - dbg_info.ehci_caps = (void*)ehci_base; - dbg_info.status |= DBGP_EP_ENABLED; + diff = (unsigned)dbg_info->ehci_caps - ehci_base; + dbg_info->ehci_regs -= diff; + dbg_info->ehci_debug -= diff; + dbg_info->ehci_caps = (void*)ehci_base; + dbg_info->status |= DBGP_EP_ENABLED; } static void usbdebug_disable(void) { - dbg_info.status &= ~DBGP_EP_ENABLED; + struct ehci_debug_info *dbg_info = dbgp_ehci_info(); + dbg_info->status &= ~DBGP_EP_ENABLED; } static void pci_ehci_set_resources(struct device *dev) @@ -82,35 +83,32 @@ void pci_ehci_read_resources(struct device *dev) static void dbgp_init(void) { -#if !CONFIG_EARLY_CONSOLE - enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); -#endif - usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info); + usbdebug_init(); } static void dbgp_tx_byte(unsigned char data) { - usbdebug_tx_byte(&dbg_info, data); + usbdebug_tx_byte(dbgp_console_output(), data); } static unsigned char dbgp_rx_byte(void) { unsigned char data = 0xff; - if (dbgp_ep_is_active(&dbg_info)) - dbgp_bulk_read_x(&dbg_info, &data, 1); + if (dbgp_ep_is_active(dbgp_console_input())) + dbgp_bulk_read_x(dbgp_console_input(), &data, 1); return data; } static void dbgp_tx_flush(void) { - usbdebug_tx_flush(&dbg_info); + usbdebug_tx_flush(dbgp_console_output()); } static int dbgp_tst_byte(void) { - return dbgp_ep_is_active(&dbgp_info); + return dbgp_ep_is_active(dbgp_console_input()); } static const struct console_driver usbdebug_direct_console __console = { diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index fe4ef32..e32410e 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -60,10 +60,12 @@ void enable_usbdebug(unsigned int port); int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); void set_debug_port(unsigned port); -int early_usbdebug_init(void); +int usbdebug_init(void); +struct ehci_debug_info *dbgp_ehci_info(void); +#define dbgp_console_output dbgp_ehci_info +#define dbgp_console_input dbgp_ehci_info int dbgp_ep_is_active(struct ehci_debug_info *dbg_info); void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); void usbdebug_tx_flush(struct ehci_debug_info *info); -int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 129493c..6143d4b 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -86,6 +86,10 @@ #define DBGP_MAX_PACKET 8 #define DBGP_LOOPS 1000 +#if !defined(__PRE_RAM__) && !defined(__SMM__) +static struct ehci_debug_info glob_dbg_info; +#endif + static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) { u32 ctrl; @@ -361,8 +365,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) return -1; //-ENOTCONN; } - -int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) +static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; struct ehci_regs *ehci_regs; @@ -574,22 +577,8 @@ next_debug_port: return -10; } -int early_usbdebug_init(void) -{ - struct ehci_debug_info *dbg_info = (struct ehci_debug_info *) - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); - - return usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); -} - void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) { - if (!dbg_info) { - /* "Find" dbg_info structure in Cache */ - dbg_info = (struct ehci_debug_info *) - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); - } - if (dbgp_is_ep_active(dbg_info)) { dbg_info->buf[dbg_info->bufidx++] = data; if (dbg_info->bufidx >= 8) { @@ -601,12 +590,6 @@ void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) void usbdebug_tx_flush(struct ehci_debug_info *dbg_info) { - if (!dbg_info) { - /* "Find" dbg_info structure in Cache */ - dbg_info = (struct ehci_debug_info *) - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); - } - if (dbgp_is_ep_active(dbg_info) && dbg_info->bufidx > 0) { dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); dbg_info->bufidx = 0; @@ -617,3 +600,23 @@ int dbgp_ep_is_active(struct ehci_debug_info *dbg_info) { return (dbg_info->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); } + +struct ehci_debug_info *dbgp_ehci_info(void) +{ +#if __PRE_RAM__ + /* "Find" dbg_info structure in Cache */ + return (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); +#else + return &glob_dbg_info; +#endif +} + +int usbdebug_init(void) +{ + struct ehci_debug_info *dbg_info = dbgp_ehci_info(); +#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE + enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); +#endif + return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 78eedb8..3eb2fb3 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -278,7 +278,7 @@ void sdram_initialize(struct pei_data *pei_data) #if CONFIG_USBDEBUG /* mrc.bin reconfigures USB, so reinit it to have debug */ - early_usbdebug_init(); + usbdebug_init(); #endif /* For reference print the System Agent version

1 0

Patch set updated for coreboot: 1487b85 usbdebug: Refactor disable logic
by Kyösti Mälkki 09 Jul '13

09 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3624 -gerrit commit 1487b854c0054fe222ee71e00eed9042d71f0fb3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 5 21:38:54 2013 +0300 usbdebug: Refactor disable logic Output to usbdebug console needs to be disabled until hardware is initialized and while EHCI BAR is relocated. Add separate field ehci_info to point to back to EHCI context when hardware is ready to transfer data. Change-Id: If7d441b561819ab8ae23ed9f3f320f7742ed231e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/usbdebug_console.c | 30 +++++++++++------------------- src/include/usbdebug.h | 10 +++++++--- src/lib/usbdebug.c | 15 +++++++++------ 3 files changed, 27 insertions(+), 28 deletions(-) diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index 9cfb454..d674779 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -28,7 +28,7 @@ static struct ehci_debug_info dbg_info; static struct device_operations *ehci_drv_ops; static struct device_operations ehci_dbg_ops; -void set_ehci_base(unsigned ehci_base) +static void usbdebug_re_enable(unsigned ehci_base) { unsigned diff; @@ -39,36 +39,28 @@ void set_ehci_base(unsigned ehci_base) dbg_info.ehci_regs -= diff; dbg_info.ehci_debug -= diff; dbg_info.ehci_caps = (void*)ehci_base; + dbg_info.status |= DBGP_EP_ENABLED; } -void set_ehci_debug(unsigned ehci_debug) +static void usbdebug_disable(void) { - dbg_info.ehci_debug = (void*)ehci_debug; -} - -unsigned get_ehci_debug(void) -{ - return (unsigned)dbg_info.ehci_debug; + dbg_info.status &= ~DBGP_EP_ENABLED; } static void pci_ehci_set_resources(struct device *dev) { struct resource *res; - u32 base; - u32 usb_debug; printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev)); - usb_debug = get_ehci_debug(); - set_ehci_debug(0); + usbdebug_disable(); if (ehci_drv_ops->set_resources) ehci_drv_ops->set_resources(dev); - res = find_resource(dev, EHCI_BAR_INDEX); - set_ehci_debug(usb_debug); - if (!res) return; - base = res->base; - set_ehci_base(base); + if (!res) + return; + + usbdebug_re_enable((u32)res->base); report_resource_stored(dev, res, ""); printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev)); } @@ -105,7 +97,7 @@ static unsigned char dbgp_rx_byte(void) { unsigned char data = 0xff; - if (dbg_info.ehci_debug) + if (dbgp_ep_is_active(&dbg_info)) dbgp_bulk_read_x(&dbg_info, &data, 1); return data; @@ -118,7 +110,7 @@ static void dbgp_tx_flush(void) static int dbgp_tst_byte(void) { - return (int)dbg_info.ehci_debug; + return dbgp_ep_is_active(&dbgp_info); } static const struct console_driver usbdebug_direct_console __console = { diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 990312a..fe4ef32 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -49,16 +49,20 @@ struct ehci_debug_info { u32 endpoint_in; char buf[8]; u8 bufidx; + u8 status; }; +#define DBGP_EP_VALID (1<<0) +#define DBGP_EP_ENABLED (1<<1) +#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) + void enable_usbdebug(unsigned int port); int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); -void set_ehci_base(unsigned ehci_base); -void set_ehci_debug(unsigned ehci_debug); -unsigned get_ehci_debug(void); void set_debug_port(unsigned port); int early_usbdebug_init(void); + +int dbgp_ep_is_active(struct ehci_debug_info *dbg_info); void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); void usbdebug_tx_flush(struct ehci_debug_info *info); int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 200121f..129493c 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -385,6 +385,7 @@ int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *in ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; info->bufidx = 0; + info->status = 0; try_next_time: port_map_tried = 0; @@ -547,6 +548,7 @@ try_next_port: info->devnum = devnum; info->endpoint_out = dbgp_endpoint_out; info->endpoint_in = dbgp_endpoint_in; + info->status |= DBGP_EP_ENABLED | DBGP_EP_VALID; return 0; err: @@ -582,35 +584,36 @@ int early_usbdebug_init(void) void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) { -#if DBGP_DEBUG == 0 if (!dbg_info) { /* "Find" dbg_info structure in Cache */ dbg_info = (struct ehci_debug_info *) (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); } - if (dbg_info->ehci_debug) { + if (dbgp_is_ep_active(dbg_info)) { dbg_info->buf[dbg_info->bufidx++] = data; if (dbg_info->bufidx >= 8) { dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); dbg_info->bufidx = 0; } } -#endif } void usbdebug_tx_flush(struct ehci_debug_info *dbg_info) { -#if DBGP_DEBUG == 0 if (!dbg_info) { /* "Find" dbg_info structure in Cache */ dbg_info = (struct ehci_debug_info *) (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); } - if (dbg_info->ehci_debug && dbg_info->bufidx > 0) { + if (dbgp_is_ep_active(dbg_info) && dbg_info->bufidx > 0) { dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); dbg_info->bufidx = 0; } -#endif +} + +int dbgp_ep_is_active(struct ehci_debug_info *dbg_info) +{ + return (dbg_info->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); }

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coreboot-gerrit July 2013