coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: e946f98 ec/google: Support Chrome EC protocol version 3.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit e946f981a4c603d93eced2e0ccf8837fca7c8cd4 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sat Jun 22 11:18:39 2013 +0800 ec/google: Support Chrome EC protocol version 3. Add the new Chrome EC protocol version 3 to Coreboot. Note, protocol version 3 is not applied on any bus implementations yet. LPC (x86) and I2C (arm/snow) are still using v2 protocol. The first one to use v3 protocol will be SPI bus (arm/pit). LPC / I2C will be updated to v3 only when they are ready to change. Change-Id: I3006435295fb509c6351afbb97de0fcedcb1d8c4 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3750 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3750 for details. -gerrit

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Patch merged into coreboot/master: 23fb997 ec/google: Generalize communication protocol support in EC drivers.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 23fb9979d999a155a2560a9f09f4fcdc1b96e9e7 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Jun 21 20:11:47 2013 +0800 ec/google: Generalize communication protocol support in EC drivers. Since EC protocol v3, the packet format will be the same for all buses (inclding I2C, SPI, and LPC). That will simplify the implementation in each individual bus driver source file. To prepare for that, we will move the protocol part into crosec_proto.c: crosec_command_proto, with bus driver in callback "crosec_io". Change-Id: I9ccd19a57a182899dd1ef1cd90598679c1546295 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3749 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3749 for details. -gerrit

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Patch merged into coreboot/master: c357aed armv7/pit: Setup EC on SPI2.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit c357aed3d7954c87375ab5f7f6c0902a302adf09 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jun 24 20:02:01 2013 +0800 armv7/pit: Setup EC on SPI2. The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3707 for details. -gerrit

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Patch merged into coreboot/master: e42030d arm/exynos: Correct SPI session commands.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit e42030d23600990e95db2af1e9e1a366ff3d4ec7 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sun Jun 23 08:14:30 2013 +0800 arm/exynos: Correct SPI session commands. Some initialization / shutdown commands should be paired correctly in a SPI I/O session. For example, setting CS should be enabled and disabled in each read; and the bus width (byte or word) should be configured only when opening / closing the SPI device. Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3706 for details. -gerrit

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Patch merged into coreboot/master: 8b95c13 AMD: Kconfig cleanup
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 8b95c134207de9573f8e5eb758e5cee51741604a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 11:30:48 2013 +0300 AMD: Kconfig cleanup Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3623 for details. -gerrit

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Patch merged into coreboot/master: 3ad5a9b pit: update I2C4 speed constant
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 3ad5a9b97f2d66764880e0cf01b1833d39ddd5ce Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 22 19:42:15 2013 -0700 pit: update I2C4 speed constant Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3705 for details. -gerrit

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Patch merged into coreboot/master: f396ad5 exynos5420: i2c: Fix error handling.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit f396ad5a6c5dec6c84343005a38c0931e7281e69 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Jun 24 03:20:22 2013 -0700 exynos5420: i2c: Fix error handling. The functions which checked the status of a transfer would return success if the bus was no longer occupied, even if it's no longer occupied because the transfer failed. This change modifies those functions to return three possible values, 0 if the transfer isn't done, -1 if there was a fault, and 1 if the transaction completed successfully. Change-Id: Idcc5fdf73cab3c3ece0e96f14113a216db289e05 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3704 for details. -gerrit

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Patch merged into coreboot/master: 7c2ae7a exynos5420: Clock the mmc blocks off of the mpll.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 7c2ae7ae53ac2bc4dadc55ba5445d0556ee32251 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Jun 24 03:14:41 2013 -0700 exynos5420: Clock the mmc blocks off of the mpll. The exynos manual suggests hooking the mmc ip blocks to the mpll. They had been set to use a different pll. This changes them over and modifies the divider so that the frequency stays the same. Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3703 for details. -gerrit

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Patch merged into coreboot/master: 04d6e01 pit: Configure the pinmux for the i2c busses that are connected on pit.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 04d6e01d43626383fb80936ef1237df67cf23ca1 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 23 03:16:46 2013 -0700 pit: Configure the pinmux for the i2c busses that are connected on pit. Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3702 for details. -gerrit

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Patch merged into coreboot/master: be58278 exynos5420: use speed parameter in i2c_init() for HSI2C
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit be58278a8654ce089dbe94be2193539ef7f26c1e Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 22 19:40:43 2013 -0700 exynos5420: use speed parameter in i2c_init() for HSI2C This allows us to set different speeds for each HSI2C bus. Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3701 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3701 for details. -gerrit

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coreboot-gerrit July 2013