coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 2b31679 armv7/pit: Correct EC device in mainboard configuration.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 2b3167908be680b5aa1cd6fe2f42a44d4c118f3f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 19:48:43 2013 +0800 armv7/pit: Correct EC device in mainboard configuration. The ChromeOS EC for peach_pit is connected to SPI2 bus, not I2C. Change-Id: Ifeb8a626aa4fc3d3a181a7bc016e3f91be948ae5 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3716 for details. -gerrit

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Patch merged into coreboot/master: f473df1 armv7/exynos5420: Remove the extra reopen when reading SPI.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit f473df141956d639ccc9e2ad8c60b313294d6e8d Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 21:22:55 2013 +0800 armv7/exynos5420: Remove the extra reopen when reading SPI. The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be removed now. Change-Id: I6b1bf717c916903999a137998a578b0a866829bd Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3715 for details. -gerrit

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Patch merged into coreboot/master: a965a37 armv7/exynos5420: Apply new implementation for SPI transmission.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit a965a37810f5fbbc35a435f1912d7f1617e36a81 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:31:22 2013 +0800 armv7/exynos5420: Apply new implementation for SPI transmission. Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3714 for details. -gerrit

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Patch merged into coreboot/master: 8644207 armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 864420766ad85c8ed0dd98aefd8f527aeb506aa5 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:29:06 2013 +0800 armv7/exynos5420: Add output ability and half-duplex mode in SPI driver. The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and only full-duplex mode. To communicate with devices like ChromeOS EC, we need both output (tx) and half-duplex (searching frame header) features. This commit adds a spi_rx_tx that can handle all cases we need. Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3713 for details. -gerrit

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Patch merged into coreboot/master: cab3621 armv7/exynos5420: Revise SPI open/close/reset procedure.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit cab3621446542fadf67e9406c4ae39fb63a0536f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:22:50 2013 +0800 armv7/exynos5420: Revise SPI open/close/reset procedure. The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3712 for details. -gerrit

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Patch merged into coreboot/master: ed1742c armv7/exynos5420: Provide configuration for SPI0~SPI2.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit ed1742cafec5627023e12f8bde52282247d17ddd Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:17:42 2013 +0800 armv7/exynos5420: Provide configuration for SPI0~SPI2. Fill the SPI device parameters for spi_setup_slave on Exynos 5420. Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3711 for details. -gerrit

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Patch merged into coreboot/master: ffa5bad armv7/exynos5420: Change SPI module to standard <spi-generic> interface.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit ffa5bada722a60e0115775ee69cd681c3737f17a Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:16:13 2013 +0800 armv7/exynos5420: Change SPI module to standard <spi-generic> interface. The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard (spi-generic.h) and will be a problem when we want to share SPI drivers. This commit replaces exynos_spi_* by spi_* functions. Note, exynos_spi_read is kept and changed to a static function because its usage is different from the standard API "spi_xfer". Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3710 for details. -gerrit

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Patch merged into coreboot/master: 45d524d armv7/exynos5420: Clean up unused header and constants in spi.c
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 45d524d2783adad9fee62a5bf909baf675e83fc9 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:03:47 2013 +0800 armv7/exynos5420: Clean up unused header and constants in spi.c Remove unused header and constant definition in SPI module. Change-Id: I339e603f48186e4a356e83518b0d0b4c907f11b8 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3709 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3709 for details. -gerrit

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Patch merged into coreboot/master: 16cb010 armv7/exynos5420: Revise SPI device list in cpu.h
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 16cb01044010b4bd1bacad3160aebf91ebd86681 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 19:52:52 2013 +0800 armv7/exynos5420: Revise SPI device list in cpu.h Add SPI0 and SPI2 to Exynos 5 SPI list, and correct structure names. Also removed the un-enumerated devices (SPI_BASE, base_spi()). Change-Id: Ica6d9a41f9619c8c61eab664d5e988dd4a428e09 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3708 for details. -gerrit

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Patch merged into coreboot/master: 0ee7062 ec/google: Support ChromeOS EC on SPI bus.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 0ee7062e305c6ba4457e1edf10de8d5b3b388a70 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 19:42:12 2013 +0800 ec/google: Support ChromeOS EC on SPI bus. For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface (see spi-generic.h) to exchange data. Note: Only EC protocol v3 is supported for SPI bus. Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3751 for details. -gerrit

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coreboot-gerrit July 2013