Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3732
-gerrit
commit 7f92be0a9c697e2f990f59535489013cee344b74
Author: Peter Stuge <peter(a)stuge.se>
Date: Tue Jul 9 19:37:20 2013 +0200
SMBIOS: Clarify prompts and help texts for Serial and Version numbers
Change-Id: If1fa39db79eeecbef90c8695143d2fe2adf2f21a
Signed-off-by: Peter Stuge <peter(a)stuge.se>
---
src/mainboard/Kconfig | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index a8cf362..3f5c673 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -335,18 +335,18 @@ config ENABLE_POWER_BUTTON
def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE
config MAINBOARD_SERIAL_NUMBER
- string "Serial number"
+ string "SMBIOS Serial number"
depends on GENERATE_SMBIOS_TABLES
default "123456789"
help
- Define the used serial number which will be used by SMBIOS tables.
+ The Serial Number to store in SMBIOS structures.
config MAINBOARD_VERSION
- string "Version number"
+ string "SMBIOS Version number"
depends on GENERATE_SMBIOS_TABLES
default "1.0"
help
- Define the used version number which will be used by SMBIOS tables.
+ The Version Number to store in SMBIOS structures.
config MAINBOARD_SMBIOS_MANUFACTURER
string "SMBIOS Manufacturer"
the following patch was just integrated into master:
commit b25a9da6e7692036fd34ee9327bc082e10c29ae0
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jun 26 08:19:14 2013 +0300
Unify PCI configuration cycles
Split PCI IO configuration and MMIO configuration cycles to separate
files. Modern hardware does not use IO cycles for PCI configuration
after initial setup in bootblock.
Note that the pci_mmio_ and pcie_ functions were different in masking
the alignment for register address. PCI standard requires that 16-bit
and 32-bit configuration register writes do not cross boundaries.
Change-Id: Ie6441283e1a033b4b395e972c18c31277f973897
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3554
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
See http://review.coreboot.org/3554 for details.
-gerrit
the following patch was just integrated into master:
commit 33e5df3f25b4594c008788625cd405d988fc6e6b
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jul 3 10:51:34 2013 +0300
Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.
Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3607 for details.
-gerrit
the following patch was just integrated into master:
commit 52914323bf876342ab3497bfc527f139680d1612
Author: Andrew Wu <arw(a)dmp.com.tw>
Date: Tue Jul 9 21:29:25 2013 +0800
Vortex86EX southbridge routes more built-in PCI device IRQs.
Routes IRQs for USB device, SPI1, MOTOR, HD audio, CAN bus.
Change-Id: I995a5c6d3ed6a7dca4f0d21545c928132ccbbc21
Signed-off-by: Andrew Wu <arw(a)dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3725 for details.
-gerrit
the following patch was just integrated into master:
commit 8ee04d784cbaeb8a30276ac22aa99ddda44092b7
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Jul 6 11:41:09 2013 +0300
usbdebug: Put ehci_debug_info in CAR_GLOBAL
Store EHCI Debug Port runtime variables in CAR_GLOBAL.
For platforms without CAR_MIGRATION, logging on EHCI Debug Port is
temporarily lost when CAR is torn down at end of romstage.
On model_2065x and model_206ax ehci_debug_info was overlapping the MRC
variable region and additionally migration used incorrect size for
the structure.
Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3475
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/3475 for details.
-gerrit
the following patch was just integrated into master:
commit 41c10cd2d73198e61573af1341d5826654f1133a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 9 04:19:22 2013 +0300
usbdebug: Move EHCI BAR relocation code
There are other uses for EHCI debug port besides console, so move
EHCI relocation code from console to lib.
Change-Id: I95cddd31be529351d9ec68f14782cc3cbe08c617
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3626
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/3626 for details.
-gerrit
the following patch was just integrated into master:
commit 9e7806a788f9617d3dd9139a74ab3f7b03eb9581
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Jul 6 11:56:49 2013 +0300
usbdebug: Move ehci_debug_info allocation
Move ehci_debug_info allocation from console to lib, as console code
was only built for ramstage.
Implement dbgp_ehci_info() to return the EHCI context. Alread alias this
as dbgp_console_input() and _output() to return the console stream context
later on.
Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3625
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3625 for details.
-gerrit