coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c852495 usbdebug: Drop old includes
by Kyösti Mälkki 11 Jul '13

11 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3764 -gerrit commit c8524950c2c974a13c88df6c4a003f7248b38668 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 11 06:43:43 2013 +0300 usbdebug: Drop old includes Change-Id: I4786bff41fef924c72087c354e394bdc1996cadc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 1 - src/cpu/intel/model_2065x/model_2065x_init.c | 1 - src/cpu/intel/model_206ax/model_206ax_init.c | 1 - src/cpu/intel/model_68x/model_68x_init.c | 1 - src/cpu/intel/model_6bx/model_6bx_init.c | 1 - src/cpu/intel/model_6ex/model_6ex_init.c | 1 - src/cpu/intel/model_6fx/model_6fx_init.c | 1 - 8 files changed, 8 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 0bf98ec..056b289 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -35,7 +35,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <pc80/mc146818rtc.h> -#include <usbdebug.h> #include "haswell.h" #include "chip.h" diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 9304b58..e0aa120 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -30,7 +30,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <usbdebug.h> static const uint32_t microcode_updates[] = { #include "microcode-M01106C2217.h" diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f430276..ab4db59 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -35,7 +35,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <pc80/mc146818rtc.h> -#include <usbdebug.h> #include "model_2065x.h" #include "chip.h" diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 6bf158e..fa974e5 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -35,7 +35,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <pc80/mc146818rtc.h> -#include <usbdebug.h> #include "model_206ax.h" #include "chip.h" diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 37145f1..c4bd7ac 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -31,7 +31,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <usbdebug.h> static const uint32_t microcode_updates[] = { #include "microcode-534-MU16810d.h" diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index 2076274..b7affd9 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -31,7 +31,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <usbdebug.h> static const uint32_t microcode_updates[] = { #include "microcode-737-MU16b11c.h" diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 4862cf3..e9c63da 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -32,7 +32,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <usbdebug.h> static const uint32_t microcode_updates[] = { #include "microcode-1624-m206e839.h" diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 31ba53a..faf1277 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -32,7 +32,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <usbdebug.h> static const uint32_t microcode_updates[] = { #include "microcode-m016fbBA.h"

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Patch set updated for coreboot: ba98a66 Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3761 -gerrit commit ba98a66c9a869bacf46065a5bb1a12f92f000b15 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:04:26 2013 -0700 Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove. Change-Id: I4b6a57e7d8e7e685c609b1d85368585b9dd197dc Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/Kconfig | 4 ++++ src/lib/Makefile.inc | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 14e7801..f65c8e3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -244,6 +244,10 @@ config HAVE_ARCH_MEMCPY bool default n +config HAVE_ARCH_MEMMOVE + bool + default n + menu "Chipset" comment "CPU" diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d44f4a7..f1783ba 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -26,6 +26,9 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) bootblock-y += memcpy.c endif bootblock-y += memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) +bootblock-y += memmove.c +endif ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c @@ -56,7 +59,9 @@ romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c endif romstage-y += compute_ip_checksum.c +ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) romstage-y += memmove.c +endif romstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += hardwaremain.c @@ -70,7 +75,9 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c endif ramstage-y += memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) ramstage-y += memmove.c +endif ramstage-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += delay.c

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Patch set updated for coreboot: a74123e Move the HAVE_ARCH_* config options from src/arch/x86 to src/.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3760 -gerrit commit a74123eb15a1ca7b248e2ae4d48c6a16b044dce0 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 13:52:37 2013 -0700 Move the HAVE_ARCH_* config options from src/arch/x86 to src/. The options that keep track of whether there are arch versions of the standard string functions shouldn't be in the arch/x86 directory since they apply to all architectures. Move them into the higher level, shared Kconfig defaulting to off. Then, in each applicable arch (currently all of them) they can be selected to on. Change-Id: I7ea64a583230fdc28773f17fd7cc23e0f0a5f3d6 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/Kconfig | 8 ++++++++ src/arch/armv7/Kconfig | 15 +++++++-------- src/arch/x86/Kconfig | 14 ++++++-------- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index fdf40e5..14e7801 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -236,6 +236,14 @@ if ARCH_ARMV7 source src/arch/armv7/Kconfig endif +config HAVE_ARCH_MEMSET + bool + default n + +config HAVE_ARCH_MEMCPY + bool + default n + menu "Chipset" comment "CPU" diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 633c5ef..130acb4 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -1,5 +1,12 @@ menu "Architecture (armv7)" + +config ARM_ARCH_OPTIONS + bool + default y + select HAVE_ARCH_MEMSET + select HAVE_ARCH_MEMCPY + # Maximum reboot count # TODO: Improve description. config MAX_REBOOT_CNT @@ -32,12 +39,4 @@ config UPDATE_IMAGE is a suitable file for further processing. The bootblock will not be modified. -config HAVE_ARCH_MEMSET - bool - default y - -config HAVE_ARCH_MEMCPY - bool - default y - endmenu diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 95fc172..287e2bc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,5 +1,11 @@ menu "Architecture (x86)" +config X86_ARCH_OPTIONS + bool + default y + select HAVE_ARCH_MEMSET + select HAVE_ARCH_MEMCPY + config MARK_GRAPHICS_MEM_WRCOMB bool "Mark graphics memory as write-combining." default n @@ -95,14 +101,6 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string -config HAVE_ARCH_MEMSET - bool - default y - -config HAVE_ARCH_MEMCPY - bool - default y - config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS

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Patch set updated for coreboot: 977965c arm: Add and enable an arch specific version of memmove.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3763 -gerrit commit 977965cf937ac34ed15885528032e6ee4cd76f47 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:15:22 2013 -0700 arm: Add and enable an arch specific version of memmove. This version is taken from arch/arm/lib/memmove.S in the Linux kernel. Change-Id: Ic875d0cf5b1cb407606530b7f465c406b134f0fa Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Kconfig | 1 + src/arch/armv7/Makefile.inc | 3 + src/arch/armv7/memmove.S | 197 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+) diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 130acb4..4f9fc34 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -6,6 +6,7 @@ config ARM_ARCH_OPTIONS default y select HAVE_ARCH_MEMSET select HAVE_ARCH_MEMCPY + select HAVE_ARCH_MEMMOVE # Maximum reboot count # TODO: Improve description. diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 31410e3..dafe98c 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -188,6 +188,9 @@ bootblock-y += memset.S romstage-y += memcpy.S ramstage-y += memcpy.S bootblock-y += memcpy.S +romstage-y += memmove.S +ramstage-y += memmove.S +bootblock-y += memmove.S $(obj)/arch/armv7/coreboot_table.ramstage.o : $(OPTION_TABLE_H) diff --git a/src/arch/armv7/memmove.S b/src/arch/armv7/memmove.S new file mode 100644 index 0000000..a2f9ea1 --- /dev/null +++ b/src/arch/armv7/memmove.S @@ -0,0 +1,197 @@ +/* + * linux/arch/arm/lib/memmove.S + * + * Author: Nicolas Pitre + * Created: Sep 28, 2005 + * Copyright: (C) MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <assembler.h> + + .text + +/* + * Prototype: void *memmove(void *dest, const void *src, size_t n); + * + * Note: + * + * If the memory regions don't overlap, we simply branch to memcpy which is + * normally a bit faster. Otherwise the copy is done going downwards. This + * is a transposition of the code from copy_template.S but with the copy + * occurring in the opposite direction. + */ + +.type memmove, function +.globl memmove +memmove: + subs ip, r0, r1 + cmphi r2, ip + bls memcpy + + stmfd sp!, {r0, r4, lr} + add r1, r1, r2 + add r0, r0, r2 + subs r2, r2, #4 + blt 8f + ands ip, r0, #3 + PLD( pld [r1, #-4] ) + bne 9f + ands ip, r1, #3 + bne 10f + +1: subs r2, r2, #(28) + stmfd sp!, {r5 - r8} + blt 5f + + CALGN( ands ip, r0, #31 ) + CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( bcs 2f ) + CALGN( adr r4, 6f ) + CALGN( subs r2, r2, ip ) @ C is set here + CALGN( rsb ip, ip, #32 ) + CALGN( add pc, r4, ip ) + + PLD( pld [r1, #-4] ) +2: PLD( subs r2, r2, #96 ) + PLD( pld [r1, #-32] ) + PLD( blt 4f ) + PLD( pld [r1, #-64] ) + PLD( pld [r1, #-96] ) + +3: PLD( pld [r1, #-128] ) +4: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr} + subs r2, r2, #32 + stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr} + bge 3b + PLD( cmn r2, #96 ) + PLD( bge 4b ) + +5: ands ip, r2, #28 + rsb ip, ip, #32 + addne pc, pc, ip @ C is always clear here + b 7f +6: W(nop) + W(ldr) r3, [r1, #-4]! + W(ldr) r4, [r1, #-4]! + W(ldr) r5, [r1, #-4]! + W(ldr) r6, [r1, #-4]! + W(ldr) r7, [r1, #-4]! + W(ldr) r8, [r1, #-4]! + W(ldr) lr, [r1, #-4]! + + add pc, pc, ip + nop + W(nop) + W(str) r3, [r0, #-4]! + W(str) r4, [r0, #-4]! + W(str) r5, [r0, #-4]! + W(str) r6, [r0, #-4]! + W(str) r7, [r0, #-4]! + W(str) r8, [r0, #-4]! + W(str) lr, [r0, #-4]! + + CALGN( bcs 2b ) + +7: ldmfd sp!, {r5 - r8} + +8: movs r2, r2, lsl #31 + ldrneb r3, [r1, #-1]! + ldrcsb r4, [r1, #-1]! + ldrcsb ip, [r1, #-1] + strneb r3, [r0, #-1]! + strcsb r4, [r0, #-1]! + strcsb ip, [r0, #-1] + ldmfd sp!, {r0, r4, pc} + +9: cmp ip, #2 + ldrgtb r3, [r1, #-1]! + ldrgeb r4, [r1, #-1]! + ldrb lr, [r1, #-1]! + strgtb r3, [r0, #-1]! + strgeb r4, [r0, #-1]! + subs r2, r2, ip + strb lr, [r0, #-1]! + blt 8b + ands ip, r1, #3 + beq 1b + +10: bic r1, r1, #3 + cmp ip, #2 + ldr r3, [r1, #0] + beq 17f + blt 18f + + + .macro backward_copy_shift push pull + + subs r2, r2, #28 + blt 14f + + CALGN( ands ip, r0, #31 ) + CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( subcc r2, r2, ip ) + CALGN( bcc 15f ) + +11: stmfd sp!, {r5 - r9} + + PLD( pld [r1, #-4] ) + PLD( subs r2, r2, #96 ) + PLD( pld [r1, #-32] ) + PLD( blt 13f ) + PLD( pld [r1, #-64] ) + PLD( pld [r1, #-96] ) + +12: PLD( pld [r1, #-128] ) +13: ldmdb r1!, {r7, r8, r9, ip} + mov lr, r3, push #\push + subs r2, r2, #32 + ldmdb r1!, {r3, r4, r5, r6} + orr lr, lr, ip, pull #\pull + mov ip, ip, push #\push + orr ip, ip, r9, pull #\pull + mov r9, r9, push #\push + orr r9, r9, r8, pull #\pull + mov r8, r8, push #\push + orr r8, r8, r7, pull #\pull + mov r7, r7, push #\push + orr r7, r7, r6, pull #\pull + mov r6, r6, push #\push + orr r6, r6, r5, pull #\pull + mov r5, r5, push #\push + orr r5, r5, r4, pull #\pull + mov r4, r4, push #\push + orr r4, r4, r3, pull #\pull + stmdb r0!, {r4 - r9, ip, lr} + bge 12b + PLD( cmn r2, #96 ) + PLD( bge 13b ) + + ldmfd sp!, {r5 - r9} + +14: ands ip, r2, #28 + beq 16f + +15: mov lr, r3, push #\push + ldr r3, [r1, #-4]! + subs ip, ip, #4 + orr lr, lr, r3, pull #\pull + str lr, [r0, #-4]! + bgt 15b + CALGN( cmp r2, #0 ) + CALGN( bge 11b ) + +16: add r1, r1, #(\pull / 8) + b 8b + + .endm + + + backward_copy_shift push=8 pull=24 + +17: backward_copy_shift push=16 pull=16 + +18: backward_copy_shift push=24 pull=8

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Patch set updated for coreboot: d5094db x86: Add and enable an arch verson of memmove.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3762 -gerrit commit d5094dbff635b44c0b8c28e64b3e468cd5f955f2 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:08:30 2013 -0700 x86: Add and enable an arch verson of memmove. This is from memcpy_32.c in the Linux kernel. There was no copyright header in the original file either. Change-Id: Ifd259cb8a87615dce79ed1e551cc4bacb0414b4f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/x86/Kconfig | 1 + src/arch/x86/lib/Makefile.inc | 4 + src/arch/x86/lib/memmove.c | 187 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 287e2bc..581a048 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -5,6 +5,7 @@ config X86_ARCH_OPTIONS default y select HAVE_ARCH_MEMSET select HAVE_ARCH_MEMCPY + select HAVE_ARCH_MEMMOVE config MARK_GRAPHICS_MEM_WRCOMB bool "Mark graphics memory as write-combining." diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 56e4171..8588c76 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memset.c ramstage-y += memcpy.c +ramstage-y += memmove.c ramstage-y += ebda.c ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c @@ -15,13 +16,16 @@ romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c +romstage-y += memmove.c romstage-y += rom_media.c smm-y += memset.c smm-y += memcpy.c +smm-y += memmove.c smm-y += rom_media.c rmodules-y += memset.c rmodules-y += memcpy.c +rmodules-y += memmove.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/memmove.c b/src/arch/x86/lib/memmove.c new file mode 100644 index 0000000..ba12127 --- /dev/null +++ b/src/arch/x86/lib/memmove.c @@ -0,0 +1,187 @@ +#include <string.h> + +void *memmove(void *dest, const void *src, size_t n) +{ + int d0,d1,d2,d3,d4,d5; + char *ret = dest; + + __asm__ __volatile__( + /* Handle more 16bytes in loop */ + "cmp $0x10, %0\n\t" + "jb 1f\n\t" + + /* Decide forward/backward copy mode */ + "cmp %2, %1\n\t" + "jb 2f\n\t" + + /* + * movs instruction have many startup latency + * so we handle small size by general register. + */ + "cmp $680, %0\n\t" + "jb 3f\n\t" + /* + * movs instruction is only good for aligned case. + */ + "mov %1, %3\n\t" + "xor %2, %3\n\t" + "and $0xff, %3\n\t" + "jz 4f\n\t" + "3:\n\t" + "sub $0x10, %0\n\t" + + /* + * We gobble 16byts forward in each loop. + */ + "3:\n\t" + "sub $0x10, %0\n\t" + "mov 0*4(%1), %3\n\t" + "mov 1*4(%1), %4\n\t" + "mov %3, 0*4(%2)\n\t" + "mov %4, 1*4(%2)\n\t" + "mov 2*4(%1), %3\n\t" + "mov 3*4(%1), %4\n\t" + "mov %3, 2*4(%2)\n\t" + "mov %4, 3*4(%2)\n\t" + "lea 0x10(%1), %1\n\t" + "lea 0x10(%2), %2\n\t" + "jae 3b\n\t" + "add $0x10, %0\n\t" + "jmp 1f\n\t" + + /* + * Handle data forward by movs. + */ + ".p2align 4\n\t" + "4:\n\t" + "mov -4(%1, %0), %3\n\t" + "lea -4(%2, %0), %4\n\t" + "shr $2, %0\n\t" + "rep movsl\n\t" + "mov %3, (%4)\n\t" + "jmp 11f\n\t" + /* + * Handle data backward by movs. + */ + ".p2align 4\n\t" + "6:\n\t" + "mov (%1), %3\n\t" + "mov %2, %4\n\t" + "lea -4(%1, %0), %1\n\t" + "lea -4(%2, %0), %2\n\t" + "shr $2, %0\n\t" + "std\n\t" + "rep movsl\n\t" + "mov %3,(%4)\n\t" + "cld\n\t" + "jmp 11f\n\t" + + /* + * Start to prepare for backward copy. + */ + ".p2align 4\n\t" + "2:\n\t" + "cmp $680, %0\n\t" + "jb 5f\n\t" + "mov %1, %3\n\t" + "xor %2, %3\n\t" + "and $0xff, %3\n\t" + "jz 6b\n\t" + + /* + * Calculate copy position to tail. + */ + "5:\n\t" + "add %0, %1\n\t" + "add %0, %2\n\t" + "sub $0x10, %0\n\t" + + /* + * We gobble 16byts backward in each loop. + */ + "7:\n\t" + "sub $0x10, %0\n\t" + + "mov -1*4(%1), %3\n\t" + "mov -2*4(%1), %4\n\t" + "mov %3, -1*4(%2)\n\t" + "mov %4, -2*4(%2)\n\t" + "mov -3*4(%1), %3\n\t" + "mov -4*4(%1), %4\n\t" + "mov %3, -3*4(%2)\n\t" + "mov %4, -4*4(%2)\n\t" + "lea -0x10(%1), %1\n\t" + "lea -0x10(%2), %2\n\t" + "jae 7b\n\t" + /* + * Calculate copy position to head. + */ + "add $0x10, %0\n\t" + "sub %0, %1\n\t" + "sub %0, %2\n\t" + + /* + * Move data from 8 bytes to 15 bytes. + */ + ".p2align 4\n\t" + "1:\n\t" + "cmp $8, %0\n\t" + "jb 8f\n\t" + "mov 0*4(%1), %3\n\t" + "mov 1*4(%1), %4\n\t" + "mov -2*4(%1, %0), %5\n\t" + "mov -1*4(%1, %0), %1\n\t" + + "mov %3, 0*4(%2)\n\t" + "mov %4, 1*4(%2)\n\t" + "mov %5, -2*4(%2, %0)\n\t" + "mov %1, -1*4(%2, %0)\n\t" + "jmp 11f\n\t" + + /* + * Move data from 4 bytes to 7 bytes. + */ + ".p2align 4\n\t" + "8:\n\t" + "cmp $4, %0\n\t" + "jb 9f\n\t" + "mov 0*4(%1), %3\n\t" + "mov -1*4(%1, %0), %4\n\t" + "mov %3, 0*4(%2)\n\t" + "mov %4, -1*4(%2, %0)\n\t" + "jmp 11f\n\t" + + /* + * Move data from 2 bytes to 3 bytes. + */ + ".p2align 4\n\t" + "9:\n\t" + "cmp $2, %0\n\t" + "jb 10f\n\t" + "movw 0*2(%1), %%dx\n\t" + "movw -1*2(%1, %0), %%bx\n\t" + "movw %%dx, 0*2(%2)\n\t" + "movw %%bx, -1*2(%2, %0)\n\t" + "jmp 11f\n\t" + + /* + * Move data for 1 byte. + */ + ".p2align 4\n\t" + "10:\n\t" + "cmp $1, %0\n\t" + "jb 11f\n\t" + "movb (%1), %%cl\n\t" + "movb %%cl, (%2)\n\t" + ".p2align 4\n\t" + "11:" + : "=&c" (d0), "=&S" (d1), "=&D" (d2), + "=r" (d3),"=r" (d4), "=r"(d5) + :"0" (n), + "1" (src), + "2" (dest) + :"memory"); + + return ret; + +}

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New patch to review for coreboot: c7d5ba1 arm: Add and enable an arch specific version of memmove.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3763 -gerrit commit c7d5ba16245675fdecaf625a0eaa71c2649856b1 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:15:22 2013 -0700 arm: Add and enable an arch specific version of memmove. This version is taken from arch/arm/lib/memmove.S in the Linux kernel. Change-Id: Ic875d0cf5b1cb407606530b7f465c406b134f0fa Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Kconfig | 1 + src/arch/armv7/Makefile.inc | 3 + src/arch/armv7/memmove.S | 197 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+) diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 048f069..3b66058 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -6,6 +6,7 @@ config ARM_ARCH_OPTIONS default y select HAVE_ARCH_MEMSET select HAVE_ARCH_MEMCPY + select HAVE_ARCH_MEMMOVE # Maximum reboot count # TODO: Improve description. diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 31410e3..dafe98c 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -188,6 +188,9 @@ bootblock-y += memset.S romstage-y += memcpy.S ramstage-y += memcpy.S bootblock-y += memcpy.S +romstage-y += memmove.S +ramstage-y += memmove.S +bootblock-y += memmove.S $(obj)/arch/armv7/coreboot_table.ramstage.o : $(OPTION_TABLE_H) diff --git a/src/arch/armv7/memmove.S b/src/arch/armv7/memmove.S new file mode 100644 index 0000000..a2f9ea1 --- /dev/null +++ b/src/arch/armv7/memmove.S @@ -0,0 +1,197 @@ +/* + * linux/arch/arm/lib/memmove.S + * + * Author: Nicolas Pitre + * Created: Sep 28, 2005 + * Copyright: (C) MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <assembler.h> + + .text + +/* + * Prototype: void *memmove(void *dest, const void *src, size_t n); + * + * Note: + * + * If the memory regions don't overlap, we simply branch to memcpy which is + * normally a bit faster. Otherwise the copy is done going downwards. This + * is a transposition of the code from copy_template.S but with the copy + * occurring in the opposite direction. + */ + +.type memmove, function +.globl memmove +memmove: + subs ip, r0, r1 + cmphi r2, ip + bls memcpy + + stmfd sp!, {r0, r4, lr} + add r1, r1, r2 + add r0, r0, r2 + subs r2, r2, #4 + blt 8f + ands ip, r0, #3 + PLD( pld [r1, #-4] ) + bne 9f + ands ip, r1, #3 + bne 10f + +1: subs r2, r2, #(28) + stmfd sp!, {r5 - r8} + blt 5f + + CALGN( ands ip, r0, #31 ) + CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( bcs 2f ) + CALGN( adr r4, 6f ) + CALGN( subs r2, r2, ip ) @ C is set here + CALGN( rsb ip, ip, #32 ) + CALGN( add pc, r4, ip ) + + PLD( pld [r1, #-4] ) +2: PLD( subs r2, r2, #96 ) + PLD( pld [r1, #-32] ) + PLD( blt 4f ) + PLD( pld [r1, #-64] ) + PLD( pld [r1, #-96] ) + +3: PLD( pld [r1, #-128] ) +4: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr} + subs r2, r2, #32 + stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr} + bge 3b + PLD( cmn r2, #96 ) + PLD( bge 4b ) + +5: ands ip, r2, #28 + rsb ip, ip, #32 + addne pc, pc, ip @ C is always clear here + b 7f +6: W(nop) + W(ldr) r3, [r1, #-4]! + W(ldr) r4, [r1, #-4]! + W(ldr) r5, [r1, #-4]! + W(ldr) r6, [r1, #-4]! + W(ldr) r7, [r1, #-4]! + W(ldr) r8, [r1, #-4]! + W(ldr) lr, [r1, #-4]! + + add pc, pc, ip + nop + W(nop) + W(str) r3, [r0, #-4]! + W(str) r4, [r0, #-4]! + W(str) r5, [r0, #-4]! + W(str) r6, [r0, #-4]! + W(str) r7, [r0, #-4]! + W(str) r8, [r0, #-4]! + W(str) lr, [r0, #-4]! + + CALGN( bcs 2b ) + +7: ldmfd sp!, {r5 - r8} + +8: movs r2, r2, lsl #31 + ldrneb r3, [r1, #-1]! + ldrcsb r4, [r1, #-1]! + ldrcsb ip, [r1, #-1] + strneb r3, [r0, #-1]! + strcsb r4, [r0, #-1]! + strcsb ip, [r0, #-1] + ldmfd sp!, {r0, r4, pc} + +9: cmp ip, #2 + ldrgtb r3, [r1, #-1]! + ldrgeb r4, [r1, #-1]! + ldrb lr, [r1, #-1]! + strgtb r3, [r0, #-1]! + strgeb r4, [r0, #-1]! + subs r2, r2, ip + strb lr, [r0, #-1]! + blt 8b + ands ip, r1, #3 + beq 1b + +10: bic r1, r1, #3 + cmp ip, #2 + ldr r3, [r1, #0] + beq 17f + blt 18f + + + .macro backward_copy_shift push pull + + subs r2, r2, #28 + blt 14f + + CALGN( ands ip, r0, #31 ) + CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( subcc r2, r2, ip ) + CALGN( bcc 15f ) + +11: stmfd sp!, {r5 - r9} + + PLD( pld [r1, #-4] ) + PLD( subs r2, r2, #96 ) + PLD( pld [r1, #-32] ) + PLD( blt 13f ) + PLD( pld [r1, #-64] ) + PLD( pld [r1, #-96] ) + +12: PLD( pld [r1, #-128] ) +13: ldmdb r1!, {r7, r8, r9, ip} + mov lr, r3, push #\push + subs r2, r2, #32 + ldmdb r1!, {r3, r4, r5, r6} + orr lr, lr, ip, pull #\pull + mov ip, ip, push #\push + orr ip, ip, r9, pull #\pull + mov r9, r9, push #\push + orr r9, r9, r8, pull #\pull + mov r8, r8, push #\push + orr r8, r8, r7, pull #\pull + mov r7, r7, push #\push + orr r7, r7, r6, pull #\pull + mov r6, r6, push #\push + orr r6, r6, r5, pull #\pull + mov r5, r5, push #\push + orr r5, r5, r4, pull #\pull + mov r4, r4, push #\push + orr r4, r4, r3, pull #\pull + stmdb r0!, {r4 - r9, ip, lr} + bge 12b + PLD( cmn r2, #96 ) + PLD( bge 13b ) + + ldmfd sp!, {r5 - r9} + +14: ands ip, r2, #28 + beq 16f + +15: mov lr, r3, push #\push + ldr r3, [r1, #-4]! + subs ip, ip, #4 + orr lr, lr, r3, pull #\pull + str lr, [r0, #-4]! + bgt 15b + CALGN( cmp r2, #0 ) + CALGN( bge 11b ) + +16: add r1, r1, #(\pull / 8) + b 8b + + .endm + + + backward_copy_shift push=8 pull=24 + +17: backward_copy_shift push=16 pull=16 + +18: backward_copy_shift push=24 pull=8

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New patch to review for coreboot: 84427fd x86: Add and enable an arch verson of memmove.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3762 -gerrit commit 84427fdbdfa4c6df288e305fccb7302ad6114a8b Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:08:30 2013 -0700 x86: Add and enable an arch verson of memmove. This is from memcpy_32.c in the Linux kernel. There was no copyright header in the original file either. Change-Id: Ifd259cb8a87615dce79ed1e551cc4bacb0414b4f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/x86/Kconfig | 1 + src/arch/x86/lib/Makefile.inc | 4 + src/arch/x86/lib/memmove.c | 187 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 287e2bc..581a048 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -5,6 +5,7 @@ config X86_ARCH_OPTIONS default y select HAVE_ARCH_MEMSET select HAVE_ARCH_MEMCPY + select HAVE_ARCH_MEMMOVE config MARK_GRAPHICS_MEM_WRCOMB bool "Mark graphics memory as write-combining." diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 56e4171..8588c76 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memset.c ramstage-y += memcpy.c +ramstage-y += memmove.c ramstage-y += ebda.c ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c @@ -15,13 +16,16 @@ romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c +romstage-y += memmove.c romstage-y += rom_media.c smm-y += memset.c smm-y += memcpy.c +smm-y += memmove.c smm-y += rom_media.c rmodules-y += memset.c rmodules-y += memcpy.c +rmodules-y += memmove.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/memmove.c b/src/arch/x86/lib/memmove.c new file mode 100644 index 0000000..ba12127 --- /dev/null +++ b/src/arch/x86/lib/memmove.c @@ -0,0 +1,187 @@ +#include <string.h> + +void *memmove(void *dest, const void *src, size_t n) +{ + int d0,d1,d2,d3,d4,d5; + char *ret = dest; + + __asm__ __volatile__( + /* Handle more 16bytes in loop */ + "cmp $0x10, %0\n\t" + "jb 1f\n\t" + + /* Decide forward/backward copy mode */ + "cmp %2, %1\n\t" + "jb 2f\n\t" + + /* + * movs instruction have many startup latency + * so we handle small size by general register. + */ + "cmp $680, %0\n\t" + "jb 3f\n\t" + /* + * movs instruction is only good for aligned case. + */ + "mov %1, %3\n\t" + "xor %2, %3\n\t" + "and $0xff, %3\n\t" + "jz 4f\n\t" + "3:\n\t" + "sub $0x10, %0\n\t" + + /* + * We gobble 16byts forward in each loop. + */ + "3:\n\t" + "sub $0x10, %0\n\t" + "mov 0*4(%1), %3\n\t" + "mov 1*4(%1), %4\n\t" + "mov %3, 0*4(%2)\n\t" + "mov %4, 1*4(%2)\n\t" + "mov 2*4(%1), %3\n\t" + "mov 3*4(%1), %4\n\t" + "mov %3, 2*4(%2)\n\t" + "mov %4, 3*4(%2)\n\t" + "lea 0x10(%1), %1\n\t" + "lea 0x10(%2), %2\n\t" + "jae 3b\n\t" + "add $0x10, %0\n\t" + "jmp 1f\n\t" + + /* + * Handle data forward by movs. + */ + ".p2align 4\n\t" + "4:\n\t" + "mov -4(%1, %0), %3\n\t" + "lea -4(%2, %0), %4\n\t" + "shr $2, %0\n\t" + "rep movsl\n\t" + "mov %3, (%4)\n\t" + "jmp 11f\n\t" + /* + * Handle data backward by movs. + */ + ".p2align 4\n\t" + "6:\n\t" + "mov (%1), %3\n\t" + "mov %2, %4\n\t" + "lea -4(%1, %0), %1\n\t" + "lea -4(%2, %0), %2\n\t" + "shr $2, %0\n\t" + "std\n\t" + "rep movsl\n\t" + "mov %3,(%4)\n\t" + "cld\n\t" + "jmp 11f\n\t" + + /* + * Start to prepare for backward copy. + */ + ".p2align 4\n\t" + "2:\n\t" + "cmp $680, %0\n\t" + "jb 5f\n\t" + "mov %1, %3\n\t" + "xor %2, %3\n\t" + "and $0xff, %3\n\t" + "jz 6b\n\t" + + /* + * Calculate copy position to tail. + */ + "5:\n\t" + "add %0, %1\n\t" + "add %0, %2\n\t" + "sub $0x10, %0\n\t" + + /* + * We gobble 16byts backward in each loop. + */ + "7:\n\t" + "sub $0x10, %0\n\t" + + "mov -1*4(%1), %3\n\t" + "mov -2*4(%1), %4\n\t" + "mov %3, -1*4(%2)\n\t" + "mov %4, -2*4(%2)\n\t" + "mov -3*4(%1), %3\n\t" + "mov -4*4(%1), %4\n\t" + "mov %3, -3*4(%2)\n\t" + "mov %4, -4*4(%2)\n\t" + "lea -0x10(%1), %1\n\t" + "lea -0x10(%2), %2\n\t" + "jae 7b\n\t" + /* + * Calculate copy position to head. + */ + "add $0x10, %0\n\t" + "sub %0, %1\n\t" + "sub %0, %2\n\t" + + /* + * Move data from 8 bytes to 15 bytes. + */ + ".p2align 4\n\t" + "1:\n\t" + "cmp $8, %0\n\t" + "jb 8f\n\t" + "mov 0*4(%1), %3\n\t" + "mov 1*4(%1), %4\n\t" + "mov -2*4(%1, %0), %5\n\t" + "mov -1*4(%1, %0), %1\n\t" + + "mov %3, 0*4(%2)\n\t" + "mov %4, 1*4(%2)\n\t" + "mov %5, -2*4(%2, %0)\n\t" + "mov %1, -1*4(%2, %0)\n\t" + "jmp 11f\n\t" + + /* + * Move data from 4 bytes to 7 bytes. + */ + ".p2align 4\n\t" + "8:\n\t" + "cmp $4, %0\n\t" + "jb 9f\n\t" + "mov 0*4(%1), %3\n\t" + "mov -1*4(%1, %0), %4\n\t" + "mov %3, 0*4(%2)\n\t" + "mov %4, -1*4(%2, %0)\n\t" + "jmp 11f\n\t" + + /* + * Move data from 2 bytes to 3 bytes. + */ + ".p2align 4\n\t" + "9:\n\t" + "cmp $2, %0\n\t" + "jb 10f\n\t" + "movw 0*2(%1), %%dx\n\t" + "movw -1*2(%1, %0), %%bx\n\t" + "movw %%dx, 0*2(%2)\n\t" + "movw %%bx, -1*2(%2, %0)\n\t" + "jmp 11f\n\t" + + /* + * Move data for 1 byte. + */ + ".p2align 4\n\t" + "10:\n\t" + "cmp $1, %0\n\t" + "jb 11f\n\t" + "movb (%1), %%cl\n\t" + "movb %%cl, (%2)\n\t" + ".p2align 4\n\t" + "11:" + : "=&c" (d0), "=&S" (d1), "=&D" (d2), + "=r" (d3),"=r" (d4), "=r"(d5) + :"0" (n), + "1" (src), + "2" (dest) + :"memory"); + + return ret; + +}

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New patch to review for coreboot: 63d3c4f Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3761 -gerrit commit 63d3c4f9ffd0c85f2917724c7a4655de4769eb3d Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:04:26 2013 -0700 Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove. Change-Id: I4b6a57e7d8e7e685c609b1d85368585b9dd197dc Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/Kconfig | 4 ++++ src/lib/Makefile.inc | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 14e7801..f65c8e3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -244,6 +244,10 @@ config HAVE_ARCH_MEMCPY bool default n +config HAVE_ARCH_MEMMOVE + bool + default n + menu "Chipset" comment "CPU" diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d44f4a7..f1783ba 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -26,6 +26,9 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) bootblock-y += memcpy.c endif bootblock-y += memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) +bootblock-y += memmove.c +endif ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c @@ -56,7 +59,9 @@ romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c endif romstage-y += compute_ip_checksum.c +ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) romstage-y += memmove.c +endif romstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += hardwaremain.c @@ -70,7 +75,9 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c endif ramstage-y += memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) ramstage-y += memmove.c +endif ramstage-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += delay.c

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New patch to review for coreboot: 01cd968 Move the HAVE_ARCH_* config options from src/arch/x86 to src/.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3760 -gerrit commit 01cd9684034c03671c421b02369e6263f65cf8a8 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 13:52:37 2013 -0700 Move the HAVE_ARCH_* config options from src/arch/x86 to src/. The options that keep track of whether there are arch versions of the standard string functions shouldn't be in the arch/x86 directory since they apply to all architectures. Move them into the higher level, shared Kconfig defaulting to off. Then, in each applicable arch (currently all of them) they can be selected to on. Change-Id: I7ea64a583230fdc28773f17fd7cc23e0f0a5f3d6 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/Kconfig | 8 ++++++++ src/arch/armv7/Kconfig | 7 +++++++ src/arch/x86/Kconfig | 14 ++++++-------- 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index fdf40e5..14e7801 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -236,6 +236,14 @@ if ARCH_ARMV7 source src/arch/armv7/Kconfig endif +config HAVE_ARCH_MEMSET + bool + default n + +config HAVE_ARCH_MEMCPY + bool + default n + menu "Chipset" comment "CPU" diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 633c5ef..048f069 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -1,5 +1,12 @@ menu "Architecture (armv7)" + +config ARM_ARCH_OPTIONS + bool + default y + select HAVE_ARCH_MEMSET + select HAVE_ARCH_MEMCPY + # Maximum reboot count # TODO: Improve description. config MAX_REBOOT_CNT diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 95fc172..287e2bc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,5 +1,11 @@ menu "Architecture (x86)" +config X86_ARCH_OPTIONS + bool + default y + select HAVE_ARCH_MEMSET + select HAVE_ARCH_MEMCPY + config MARK_GRAPHICS_MEM_WRCOMB bool "Mark graphics memory as write-combining." default n @@ -95,14 +101,6 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string -config HAVE_ARCH_MEMSET - bool - default y - -config HAVE_ARCH_MEMCPY - bool - default y - config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS

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New patch to review for coreboot: 3501f5f arm: Add a W() macro for use in kernel assembler.
by Gabe Black 11 Jul '13

11 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3759 -gerrit commit 3501f5f6213249ada283d9b3fecc6dfc10a3c12c Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 13:35:37 2013 -0700 arm: Add a W() macro for use in kernel assembler. Some kernel assembly code uses a W macro to optionally add a .w to instructions that need to be 32 bit thumb. The gnu assembler doesn't seem to need the .w and won't assemble if it's provided. Change-Id: I0a288177788b5c61810ee7bd3d2debea66835de2 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/include/assembler.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h index 7acf0f4..10363c4 100644 --- a/src/arch/armv7/include/assembler.h +++ b/src/arch/armv7/include/assembler.h @@ -58,3 +58,5 @@ * Cache aligned */ #define CALGN(code...) code + +#define W(instr) instr

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coreboot-gerrit July 2013