coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c809210 util/cbfstool/cbfs_image.c: Store next entry in `next` so difference is not 0
by Paul Menzel 14 Jul '13

14 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3770 -gerrit commit c80921039dc145550e05325cc0be276ffd88ee1b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 10:37:10 2013 +0200 util/cbfstool/cbfs_image.c: Store next entry in `next` so difference is not 0 Currently `entry` is overwritten causing the difference to vanish and resulting in a segmentation fault. Change-Id: Ib563e0ba89f437c5f01c2bf8ed844735a528d2d2 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/cbfs_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index eb9d574..ae4d69f 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -396,7 +396,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, // setup new entry DEBUG("Setting new empty entry.\n"); - entry = cbfs_find_next_entry(image, entry); + next = cbfs_find_next_entry(image, entry); new_size = (cbfs_get_entry_addr(image, next) - cbfs_get_entry_addr(image, entry)); new_size -= cbfs_calculate_file_header_size("");

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New patch to review for coreboot: 4d37f27 Correct spelling of »*setting« in output
by Paul Menzel 14 Jul '13

14 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3769 -gerrit commit 4d37f27be9fad804cefe8c77c38e27c915a24198 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 09:28:24 2013 +0200 Correct spelling of »*setting« in output The following command was used to fix the spelling. $ git grep -i -l seting | xargs sed -i 's/eting/etting/' Change-Id: I59ceaa1b370d0ddc1397d855ff6c5e53aa5a0895 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/via/vx800/examples/romstage.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- util/cbfstool/cbfs_image.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 7c3fb7a..2814cb3 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -431,7 +431,7 @@ g) Rx73h = 32h if (boot_mode == 3) { /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ - /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ + /* setting mtrr before back memoy save s3 resume time about 0.14 seconds */ /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 4ab7212..5352705 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -52,7 +52,7 @@ static void nic_init(struct device *dev) mmio = resource->base; /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Reseting PHY... "); + printk(BIOS_DEBUG, "Resetting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 10fa52d..cb3b486 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -101,7 +101,7 @@ static void log_msg(const char *fmt, va_list args) static void fatal_error(void) { - printk(BIOS_ERR, "vboot encountered fatal error. Reseting.\n"); + printk(BIOS_ERR, "vboot encountered fatal error. Resetting.\n"); hard_reset(); } diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 44a9fe8..eb9d574 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -395,7 +395,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, cbfs_print_entry_info(image, entry, stderr); // setup new entry - DEBUG("Seting new empty entry.\n"); + DEBUG("Setting new empty entry.\n"); entry = cbfs_find_next_entry(image, entry); new_size = (cbfs_get_entry_addr(image, next) - cbfs_get_entry_addr(image, entry));

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New patch to review for coreboot: 0fa4de9 AMD boards: `dsdt.asl`: Correct spelling of »shadow« in comment
by Paul Menzel 14 Jul '13

14 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3768 -gerrit commit 0fa4de9851e2353429d92b7a3cfdd250d19eedd3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 00:24:31 2013 +0200 AMD boards: `dsdt.asl`: Correct spelling of »shadow« in comment The following command was used to correct the spelling. $ git grep -l shaow | xargs sed -i 's/shaow/shadow/' Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/dsdt.asl | 2 +- src/mainboard/amd/bimini_fam10/dsdt.asl | 2 +- src/mainboard/amd/dbm690t/dsdt.asl | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 2 +- src/mainboard/amd/pistachio/dsdt.asl | 2 +- src/mainboard/amd/tilapia_fam10/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/acpi/smbus.asl | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 2 +- src/mainboard/asus/m5a88-v/dsdt.asl | 2 +- src/mainboard/avalue/eax-785e/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 2 +- src/mainboard/gigabyte/ma78gm/dsdt.asl | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 2 +- src/mainboard/kontron/kt690/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/lippert/toucan-af/dsdt.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 2 +- src/mainboard/tyan/s8226/dsdt.asl | 2 +- src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 2 +- 29 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 7f83bf1..94757b5 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 6642680..03a00e0 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index d5eddfc..32df673 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 8de013f..01cb8dd 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -1653,7 +1653,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 94e1635..f55480d 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 060b6e3..3e5ba54 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -1565,7 +1565,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index ed0c4c2..e6816b0 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -1716,7 +1716,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asrock/e350m1/acpi/smbus.asl b/src/mainboard/asrock/e350m1/acpi/smbus.asl index e4ccfe3..ebf7ddb 100644 --- a/src/mainboard/asrock/e350m1/acpi/smbus.asl +++ b/src/mainboard/asrock/e350m1/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index c0835c4..5449d01 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -1618,7 +1618,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 11684c4..6e1ccd1 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 672af6f..dd766f7 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 26c9024..923a828 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index edbd2e5..848d43e 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 89d8e29..c221e0a 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index b393a61..a02366e 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1685,7 +1685,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 7f6dec3..53e12af 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1684,7 +1684,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 9d64e89..7890df7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -1222,7 +1222,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8, /* SMBUS slave data */ SMK1, 8, diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index aa889a3..c854067 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1638,7 +1638,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 4aef6a2..5e18375 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -1649,7 +1649,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index 6184bde..13e5620 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -1751,7 +1751,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 598dca0..20fe2d7 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index d24c379..53be887 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index 1efb3b5..79bc096 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -1639,7 +1639,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index 19ae92b..4055174 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ }

1 0

New patch to review for coreboot: e7b74ae cpu/amd/agesa/Kconfig: Add MMCONF_SUPPORT_DEFAULT
by Paul Menzel 14 Jul '13

14 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3767 -gerrit commit e7b74ae9730ec19f3732e3d8397e7ed2cde632f6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jul 13 21:00:36 2013 +0200 cpu/amd/agesa/Kconfig: Add MMCONF_SUPPORT_DEFAULT Tested on ASRock E350M1. Change-Id: I6dfd9809a74eb498182511c76434512c655c173f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index c660470..baf8e02 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -28,6 +28,7 @@ config CPU_AMD_AGESA select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER + select MMCONF_SUPPORT_DEFAULT if CPU_AMD_AGESA

1 0

Patch set updated for coreboot: 88a9fb9 usbdebug: Split endpoint buffers
by Kyösti Mälkki 14 Jul '13

14 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3726 -gerrit commit 88a9fb906dd4f23e5f2b48a820bdb6b77e5a6c40 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 8 18:11:44 2013 +0300 usbdebug: Split endpoint buffers Refactor the structure to better support receive and another set of endpoints over usbdebug. Change-Id: Ib0f76afdf4e638363ff30c67010920142c58f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/usbdebug.h | 31 +++++----------- src/lib/usbdebug.c | 95 +++++++++++++++++++++++++++++++++----------------- 2 files changed, 72 insertions(+), 54 deletions(-) diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 16077b0..2728be0 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -40,31 +40,18 @@ void pci_ehci_read_resources(struct device *dev); #endif #endif -struct ehci_debug_info { - void *ehci_caps; - void *ehci_regs; - void *ehci_debug; - u32 devnum; - u32 endpoint_out; - u32 endpoint_in; - char buf[8]; - u8 bufidx; - u8 status; -}; - -#define DBGP_EP_VALID (1<<0) -#define DBGP_EP_ENABLED (1<<1) -#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) +struct dbgp_pipe; void enable_usbdebug(unsigned int port); -int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); -int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); void set_debug_port(unsigned port); int usbdebug_init(void); -struct ehci_debug_info *dbgp_console_output(void); -struct ehci_debug_info *dbgp_console_input(void); -int dbgp_ep_is_active(struct ehci_debug_info *dbg_info); -void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); -void usbdebug_tx_flush(struct ehci_debug_info *info); + +struct dbgp_pipe *dbgp_console_output(void); +struct dbgp_pipe *dbgp_console_input(void); +int dbgp_ep_is_active(struct dbgp_pipe *pipe); +int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size); +int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size); +void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data); +void usbdebug_tx_flush(struct dbgp_pipe *pipe); #endif diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index b6c7f10..77bfd97 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -29,6 +29,33 @@ #include <ehci.h> #include <usbdebug.h> + +#define DBGP_EP_VALID (1<<0) +#define DBGP_EP_ENABLED (1<<1) +#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) + +struct dbgp_pipe +{ + u8 endpoint; + u8 status; + u8 bufidx; + char buf[8]; +}; + +#define DBGP_MAX_ENDPOINTS 4 +#define DBGP_CONSOLE_EPOUT 0 +#define DBGP_CONSOLE_EPIN 1 + +struct ehci_debug_info { + u8 devnum; + + void *ehci_caps; + void *ehci_regs; + void *ehci_debug; + + struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; +}; + /* Set this to 1 to debug the start-up of EHCI debug port hardware. You need * to modify console_init() to initialise some other console before usbdebug * to receive the printk lines from here. @@ -215,10 +242,11 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, return ret; } -int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size) +int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size) { + struct ehci_debug_info *dbg_info = dbgp_ehci_info(); return dbgp_bulk_write(dbg_info->ehci_debug, dbg_info->devnum, - dbg_info->endpoint_out, bytes, size); + pipe->endpoint, bytes, size); } static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, @@ -252,10 +280,11 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, return ret; } -int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size) +int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size) { + struct ehci_debug_info *dbg_info = dbgp_ehci_info(); return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, - dbg_info->endpoint_in, data, size, DBGP_LOOPS); + pipe->endpoint, data, size, DBGP_LOOPS); } static void dbgp_mdelay(int ms) @@ -379,8 +408,6 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ struct ehci_caps *ehci_caps; struct ehci_regs *ehci_regs; struct ehci_dbg_port *ehci_debug; - unsigned dbgp_endpoint_out; - unsigned dbgp_endpoint_in; struct usb_debug_descriptor dbgp_desc; u32 cmd, ctrl, status, portsc, hcs_params; @@ -396,8 +423,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; - info->bufidx = 0; - info->status = 0; + + memset(&info->ep_pipe, 0, sizeof (info->ep_pipe)); try_next_time: port_map_tried = 0; @@ -516,8 +543,6 @@ try_next_port: ret = -6; goto err; } - dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint; - dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint; /* Move the device to 127 if it isn't already there */ if (devnum != USB_DEBUG_DEVNUM) { @@ -546,7 +571,7 @@ try_next_port: dbgp_printk("EHCI debug interface enabled.\n"); /* Perform a small write to get the even/odd data state in sync */ - ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_endpoint_out, "USB\r\n",5); + ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_desc.bDebugOutEndpoint, "USB\r\n",5); if (ret < 0) { dbgp_printk("dbgp_bulk_write failed: %d\n", ret); ret = -9; @@ -558,10 +583,11 @@ try_next_port: info->ehci_regs = ehci_regs; info->ehci_debug = ehci_debug; info->devnum = devnum; - info->endpoint_out = dbgp_endpoint_out; - info->endpoint_in = dbgp_endpoint_in; - info->status |= DBGP_EP_ENABLED | DBGP_EP_VALID; + info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint; + info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint; + info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; + info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; return 0; err: /* Things didn't work so remove my claim */ @@ -586,22 +612,22 @@ next_debug_port: return -10; } -void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) +void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data) { - if (dbgp_is_ep_active(dbg_info)) { - dbg_info->buf[dbg_info->bufidx++] = data; - if (dbg_info->bufidx >= 8) { - dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); - dbg_info->bufidx = 0; + if (dbgp_ep_is_active(pipe)) { + pipe->buf[pipe->bufidx++] = data; + if (pipe->bufidx >= 8) { + dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); + pipe->bufidx = 0; } } } -void usbdebug_tx_flush(struct ehci_debug_info *dbg_info) +void usbdebug_tx_flush(struct dbgp_pipe *pipe) { - if (dbgp_is_ep_active(dbg_info) && dbg_info->bufidx > 0) { - dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); - dbg_info->bufidx = 0; + if (dbgp_ep_is_active(pipe) && pipe->bufidx > 0) { + dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); + pipe->bufidx = 0; } } @@ -610,6 +636,7 @@ static void usbdebug_re_enable(unsigned ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); unsigned diff; + int i; if (!dbg_info->ehci_debug) return; @@ -618,13 +645,17 @@ static void usbdebug_re_enable(unsigned ehci_base) dbg_info->ehci_regs -= diff; dbg_info->ehci_debug -= diff; dbg_info->ehci_caps = (void*)ehci_base; - dbg_info->status |= DBGP_EP_ENABLED; + + for (i=0; i<DBGP_MAX_ENDPOINTS; i++) + dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED; } static void usbdebug_disable(void) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - dbg_info->status &= ~DBGP_EP_ENABLED; + int i; + for (i=0; i<DBGP_MAX_ENDPOINTS; i++) + dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED; } static void pci_ehci_set_resources(struct device *dev) @@ -661,19 +692,19 @@ void pci_ehci_read_resources(struct device *dev) } #endif -int dbgp_ep_is_active(struct ehci_debug_info *dbg_info) +int dbgp_ep_is_active(struct dbgp_pipe *pipe) { - return (dbg_info->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); + return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); } -struct ehci_debug_info *dbgp_console_input(void) +struct dbgp_pipe *dbgp_console_output(void) { - return dbgp_ehci_info(); + return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPOUT]; } -struct ehci_debug_info *dbgp_console_input(void) +struct dbgp_pipe *dbgp_console_input(void) { - return dbgp_ehci_info(); + return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN]; } int usbdebug_init(void)

1 0

Patch merged into coreboot/master: eac9916 lenovo/x60: Move mainboard_enable() code into a mainboard_init()
by gerrit＠coreboot.org 13 Jul '13

13 Jul '13

the following patch was just integrated into master: commit eac991629f40bdb0d0d80319249dd378a295e6fa Author: Peter Stuge <peter(a)stuge.se> Date: Sat Jul 6 20:05:13 2013 +0200 lenovo/x60: Move mainboard_enable() code into a mainboard_init() mainboard_enable() is now modelled after google/parrot where the enable function only sets dev->ops->init for the root device to point to a mainboard_init() function, which in turn is called in a later pass over the device tree to do the actual initialization. Change-Id: Iaf9187532a1e432b991260201b95dda85cc312c5 Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/3619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3619 for details. -gerrit

1 0

Patch merged into coreboot/master: 9478297 src/southbridge/intel/{lynxpoint, bd82x6x}/spi.c: correct spelling of attempted
by gerrit＠coreboot.org 12 Jul '13

12 Jul '13

the following patch was just integrated into master: commit 9478297afb0bad081798e716edf29a00f1ef71a1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 29 11:41:27 2013 +0200 src/southbridge/intel/{lynxpoint,bd82x6x}/spi.c: correct spelling of attempted Change-Id: Ic6f6af6298fed2f41f140a7aa62dccf98bf60927 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3572 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3572 for details. -gerrit

1 0

Patch merged into coreboot/master: 4c3ab73 cpu: Fix spelling
by gerrit＠coreboot.org 12 Jul '13

12 Jul '13

the following patch was just integrated into master: commit 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 8 16:23:54 2013 -0600 cpu: Fix spelling Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3729 for details. -gerrit

1 0

Patch merged into coreboot/master: 0cb07e3 include: Fix spelling
by gerrit＠coreboot.org 12 Jul '13

12 Jul '13

the following patch was just integrated into master: commit 0cb07e3476d9408d0935253f9f26c0a8ddc28401 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Jul 9 21:46:01 2013 -0600 include: Fix spelling Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3755 for details. -gerrit

1 0

Patch set updated for coreboot: 48ab8b0 include: Fix spelling
by Stefan Reinauer 12 Jul '13

12 Jul '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3755 -gerrit commit 48ab8b077550e93cf9d9b7264c7f47811e40f4a1 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Jul 9 21:46:01 2013 -0600 include: Fix spelling Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/include/boot/coreboot_tables.h | 6 +++--- src/include/bootstate.h | 2 +- src/include/cbfs_core.h | 2 +- src/include/cbmem.h | 4 ++-- src/include/console/console.h | 2 +- src/include/console/post_codes.h | 12 ++++++------ src/include/cpu/amd/amdfam10_sysconf.h | 2 +- src/include/cpu/amd/amdk8_sysconf.h | 2 +- src/include/cpu/amd/gx2def.h | 12 ++++++------ src/include/cpu/amd/lxdef.h | 12 ++++++------ src/include/cpu/x86/mtrr.h | 4 ++-- src/include/cpu/x86/smm.h | 4 ++-- src/include/device/dram/ddr3.h | 2 +- src/include/device/pci_def.h | 6 +++--- src/include/ehci.h | 2 +- src/include/pc80/mc146818rtc.h | 2 +- src/include/rmodule.h | 6 +++--- src/include/romstage_handoff.h | 6 +++--- src/include/swab.h | 2 +- src/include/thread.h | 4 ++-- src/include/timer.h | 6 +++--- src/include/uart8250.h | 2 +- 22 files changed, 51 insertions(+), 51 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index ee1c29f..87819ce 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -6,11 +6,11 @@ /* The coreboot table information is for conveying information * from the firmware to the loaded OS image. Primarily this * is expected to be information that cannot be discovered by - * other means, such as quering the hardware directly. + * other means, such as querying the hardware directly. * * All of the information should be Position Independent Data. * That is it should be safe to relocated any of the information - * without it's meaning/correctnes changing. For table that + * without it's meaning/correctness changing. For table that * can reasonably be used on multiple architectures the data * size should be fixed. This should ease the transition between * 32 bit and 64 bit architectures etc. @@ -27,7 +27,7 @@ * table entry is required or not. This should remove much of the * long term compatibility burden as table entries which are * irrelevant or have been replaced by better alternatives may be - * dropped. Of course it is polite and expidite to include extra + * dropped. Of course it is polite and expedite to include extra * table entries and be backwards compatible, but it is not required. */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index af18989..46662d5 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -148,7 +148,7 @@ struct boot_state_callback { bscb_->arg = arg_ /* The following 2 functions schedule a callback to be called on entry/exit - * to a given state. Note that thare are no ordering guarantees between the + * to a given state. Note that there are no ordering guarantees between the * individual callbacks on a given state. 0 is returned on success < 0 on * error. */ int boot_state_sched_on_entry(struct boot_state_callback *bscb, diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 20636e2..54e2f60 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -56,7 +56,7 @@ #include <stdint.h> /** These are standard values for the known compression - alogrithms that coreboot knows about for stages and + algorithms that coreboot knows about for stages and payloads. Of course, other CBFS users can use whatever values they want, as long as they understand them. */ diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efb0f90..982a6d8 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -86,7 +86,7 @@ struct cbmem_entry; * implemented by the board or chipset to define the upper address where * cbmem lives. This address is required to be a 32-bit address. Additionally, * the address needs to be consistent in both romstage and ramstage. The - * dynamic cbmem infrasturue allocates new regions below the last allocated + * dynamic cbmem infrastructure allocates new regions below the last allocated * region. Regions are defined by a cbmem_entry struct that is opaque. Regions * may be removed, but the last one added is the only that can be removed. * @@ -100,7 +100,7 @@ struct cbmem_entry; #define DYN_CBMEM_ALIGN_SIZE (4096) -/* Initialze cbmem to be empty. */ +/* Initialize cbmem to be empty. */ void cbmem_initialize_empty(void); /* Return the top address for dynamic cbmem. The address returned needs to diff --git a/src/include/console/console.h b/src/include/console/console.h index 2f5f18e..7a55ae1 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -60,7 +60,7 @@ extern struct console_driver econsole_drivers[]; extern int console_loglevel; #else /* __PRE_RAM__ */ -/* Using a global varible can cause problems when we reset the stack +/* Using a global variable can cause problems when we reset the stack * from cache as ram to ram. If we make this a define USE_SHARED_STACK * we could use the same code on all architectures. */ diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ba6c916..4dc3d37 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -24,7 +24,7 @@ * This aims to be a central point for POST codes used throughout coreboot. * All POST codes should be declared here as macros, and post_code() should * be used with the macros instead of hardcoded values. This allows us to - * quicly reference POST codes when nothing is working + * quickly reference POST codes when nothing is working * * The format for a POST code macro is * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED @@ -92,8 +92,8 @@ /** * \brief Entry into coreboot in ram stage main() * - * This is the first call in ram stage main(). If this code is POSTed, then - * ramstage has succesfully loaded and started executing. + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. */ #define POST_ENTRY_RAMSTAGE 0x80 @@ -107,7 +107,7 @@ /** * \brief Console boot message succeeded * - * First console message has been succesfully sent through the console backend + * First console message has been successfully sent through the console backend * driver. */ #define POST_CONSOLE_BOOT_MSG 0x40 @@ -129,7 +129,7 @@ /** * \brief Devices have been configured * - * Device confgration has completed. + * Device configuration has completed. */ #define POST_DEVICE_CONFIGURATION_COMPLETE 0x88 @@ -207,7 +207,7 @@ /* * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h * They overlap with previous codes, and most are not even used - * Some maiboards still require them, but they are deprecated. We want to consolidate + * Some mainboards still require them, but they are deprecated. We want to consolidate * our own POST code structure with the codes above. * * standard AMD post definitions for the AMD Geode diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h index 2f08fd8..baba6ce 100644 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ b/src/include/cpu/amd/amdfam10_sysconf.h @@ -64,7 +64,7 @@ struct amdfam10_sysconf_t { unsigned lift_bsp_apicid; int apicid_offset; - void *mb; // pointer for mb releated struct + void *mb; // pointer for mb related struct }; diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h index 3ae35fd..87bd4d5 100644 --- a/src/include/cpu/amd/amdk8_sysconf.h +++ b/src/include/cpu/amd/amdk8_sysconf.h @@ -19,7 +19,7 @@ struct amdk8_sysconf_t { unsigned lift_bsp_apicid; int apicid_offset; - void *mb; // pointer for mb releated struct + void *mb; // pointer for mb related struct }; diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index ee55c2f..beb4c65 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -399,12 +399,12 @@ #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ #define BMIO 6 /* Base Mask IO */ #define SCIO 7 /* Swiss 0xCeese IO */ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */ -#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */ -#define BMO_SMM 10 /* Specail marker for SMM */ -#define BM_SMM 11 /* Specail marker for SMM */ -#define BMO_DMM 12 /* Specail marker for DMM */ -#define BM_DMM 13 /* Specail marker for DMM */ +#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */ +#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */ +#define BMO_SMM 10 /* Special marker for SMM */ +#define BM_SMM 11 /* Special marker for SMM */ +#define BMO_DMM 12 /* Special marker for DMM */ +#define BM_DMM 13 /* Special marker for DMM */ #define RO_FB 14 /* special for Frame buffer. */ #define R_FB 15 /* special for FB. */ #define OTHER 0x0FE /* Special marker for other */ diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 4eee156..da26895 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -533,12 +533,12 @@ #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ #define BMIO 6 /* Base Mask IO*/ #define SCIO 7 /* Swiss 0xCeese IO*/ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/ -#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/ -#define BMO_SMM 10 /* Specail marker for SMM*/ -#define BM_SMM 11 /* Specail marker for SMM*/ -#define BMO_DMM 12 /* Specail marker for DMM*/ -#define BM_DMM 13 /* Specail marker for DMM*/ +#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/ +#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/ +#define BMO_SMM 10 /* Special marker for SMM*/ +#define BM_SMM 11 /* Special marker for SMM*/ +#define BMO_DMM 12 /* Special marker for DMM*/ +#define BM_DMM 13 /* Special marker for DMM*/ #define RO_FB 14 /* special for Frame buffer.*/ #define R_FB 15 /* special for FB.*/ #define OTHER 0x0FE /* Special marker for other*/ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 38c3f7c..017a77e 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -47,14 +47,14 @@ * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers * want to call the components of x86_setup_mtrrs() because of other - * rquirements the ordering should still preserved. + * requirements the ordering should still preserved. * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsiblity of the caller to enable it by calling + * is the responsibility of the caller to enable it by calling * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index df7e3de..cacbff0 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -423,7 +423,7 @@ struct smm_runtime { u32 save_state_size; /* The apic_id_to_cpu provides a mapping from APIC id to cpu number. * The cpu number is indicated by the index into the array by matching - * the deafult APIC id and value at the index. The stub loader + * the default APIC id and value at the index. The stub loader * initializes this array with a 1:1 mapping. If the APIC ids are not * contiguous like the 1:1 mapping it is up to the caller of the stub * loader to adjust this mapping. */ @@ -446,7 +446,7 @@ void *smm_get_save_state(int cpu); #else /* SMM Module Loading API */ -/* Ths smm_loader_params structure provides direction to the SMM loader: +/* The smm_loader_params structure provides direction to the SMM loader: * - stack_top - optional external stack provided to loader. It must be at * least per_cpu_stack_size * num_concurrent_stacks in size. * - per_cpu_stack_size - stack size per cpu for smm modules. diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 69c072b..53a42ee 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -63,7 +63,7 @@ /* * Module type (byte 3, bits 3:0) of SPD - * This definition is specific to DDR3. DDR2 SPDs have a diferent structure. + * This definition is specific to DDR3. DDR2 SPDs have a different structure. */ enum spd_dimm_type { SPD_DIMM_TYPE_UNDEFINED = 0x00, diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 58a7321..ac20659 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -177,7 +177,7 @@ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ -#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ @@ -208,7 +208,7 @@ #define PCI_PM_PMC 2 /* PM Capabilities Register */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ -#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ +#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ @@ -255,7 +255,7 @@ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ -/* Message Signalled Interrupts registers */ +/* Message Signaled Interrupts registers */ #define PCI_MSI_FLAGS 2 /* Various flags */ #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ diff --git a/src/include/ehci.h b/src/include/ehci.h index b096f42..f920352 100644 --- a/src/include/ehci.h +++ b/src/include/ehci.h @@ -161,7 +161,7 @@ struct ehci_regs { #define USBMODE_CM_IDLE (0<<0) /* idle state */ /* Moorestown has some non-standard registers, partially due to the fact that - * its EHCI controller has both TT and LPM support. HOSTPCx are extentions to + * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to * PORTSCx */ #define HOSTPC0 0x84 /* HOSTPC extension */ diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 29e0348..170a433 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -22,7 +22,7 @@ /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, - * totalling to a max high interval of 2.228 ms. + * totaling to a max high interval of 2.228 ms. */ # define RTC_UIP 0x80 # define RTC_DIV_CTL 0x70 diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 35a82c1..247711a 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -95,18 +95,18 @@ struct rmodule_header { u32 relocations_begin_offset; u32 relocations_end_offset; /* The starting address of the linked program. This address is vital - * for determining relocation offsets as the reloction info and other + * for determining relocation offsets as the relocation info and other * symbols (bss, entry point) need this value as a basis to calculate * the offsets. */ u32 module_link_start_address; /* The module_program_size is the size of memory used while running - * the program. The program is assumed to consume a contiguos amount + * the program. The program is assumed to consume a contiguous amount * of memory. */ u32 module_program_size; /* This is program's execution entry point. */ u32 module_entry_point; - /* Optional paramter structure that can be used to pass data into + /* Optional parameter structure that can be used to pass data into * the module. */ u32 parameters_begin; u32 parameters_end; diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 3152fb2..699838a 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -23,12 +23,12 @@ #include <string.h> #include <cbmem.h> -/* It is the chipset's responsbility for maintaining the integrity of this +/* It is the chipset's responsibility for maintaining the integrity of this * structure in CBMEM. For instance, if chipset code adds this structure * using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber * fields it doesn't own. */ struct romstage_handoff { - /* Inidicate if the current boot is an S3 resume. If + /* Indicate if the current boot is an S3 resume. If * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is * responsible for initializing this variable. Otherwise, ramstage * will be re-loaded from cbfs (which can be slower since it lives @@ -42,7 +42,7 @@ struct romstage_handoff { #if defined(__PRE_RAM__) /* The romstage_handoff_find_or_add() function provides the necessary logic - * for initializng the romstage_handoff structure in cbmem. Different components + * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore * that same logic flow should be used for allocating and initializing the * structure. A newly allocated structure will be memset to 0. */ diff --git a/src/include/swab.h b/src/include/swab.h index c5e4370..8a7daba 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -10,7 +10,7 @@ * separated swab functions from cpu_to_XX, * to clean up support for bizarre-endian architectures. * - * See asm-i386/byteorder.h and suches for examples of how to provide + * See asm-i386/byteorder.h and such for examples of how to provide * architecture-dependent optimized versions * */ diff --git a/src/include/thread.h b/src/include/thread.h index 148c448..0522337 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -43,7 +43,7 @@ void threads_initialize(void); * current state in the boot state machine until it is complete. */ int thread_run(void (*func)(void *), void *arg); /* thread_run_until is the same as thread_run() except that it blocks state - * transitions from occuring in the (state, seq) pair of the boot state + * transitions from occurring in the (state, seq) pair of the boot state * machine. */ int thread_run_until(void (*func)(void *), void *arg, boot_state_t state, boot_state_sequence_t seq); @@ -52,7 +52,7 @@ int thread_run_until(void (*func)(void *), void *arg, int thread_yield_microseconds(unsigned microsecs); /* Allow and prevent thread cooperation on current running thread. By default - * all threads are marked to be cooperative. That means a thread can yeild + * all threads are marked to be cooperative. That means a thread can yield * to another thread at a pre-determined switch point. Current there is * only a single place where switching may occur: a call to udelay(). */ void thread_cooperate(void); diff --git a/src/include/timer.h b/src/include/timer.h index 40ac367..06128ce 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -67,13 +67,13 @@ int timers_run(void); * 0 returned on success, < 0 on error. */ int timer_sched_callback(struct timeout_callback *tocb, unsigned long us); -/* Add microseconds to an absoute time. */ +/* Add microseconds to an absolute time. */ static inline void mono_time_add_usecs(struct mono_time *mt, long us) { mt->microseconds += us; } -/* Add milliseconds to an absoute time. */ +/* Add milliseconds to an absolute time. */ static inline void mono_time_add_msecs(struct mono_time *mt, long ms) { mono_time_add_usecs(mt, ms * USECS_PER_MSEC); @@ -85,7 +85,7 @@ static inline void mono_time_add_rela_time(struct mono_time *mt, mono_time_add_usecs(mt, t->microseconds); } -/* Compare two absoluted times: Return -1, 0, or 1 if t1 is <, =, or > t2, +/* Compare two absolute times: Return -1, 0, or 1 if t1 is <, =, or > t2, * respectively. */ static inline int mono_time_cmp(const struct mono_time *t1, const struct mono_time *t2) diff --git a/src/include/uart8250.h b/src/include/uart8250.h index d42e822..e6a318a 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -63,7 +63,7 @@ #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ #define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_PEN 0x08 /* Parity enable */ #define UART_LCR_EPS 0x10 /* Even Parity Select */ #define UART_LCR_STKP 0x20 /* Stick Parity */ #define UART_LCR_SBRK 0x40 /* Set Break */

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coreboot-gerrit July 2013