coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: c0b322e am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig.
by Gabe Black 15 Jul '13

15 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3582 -gerrit commit c0b322e1f98fb7bffa8327962eca6339cce69bff Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:16:19 2013 -0700 am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig. This variable wasn't being defined and was defaulting to zero when used in the ROM stage's linker script. This change defines it as a variable, and gives it a value which is slightly beyond the end of the bootblock. By making the ROM stage request to be loaded slightly farther into memory than it was loaded by the SOC's masked ROM, we ensure that it's moved away from the stage's metadata instead of on top of it. When it moves the other way, it clobbers important values like the entry point vefore the bootblock has had a chance to use them. Change-Id: I027a1365d05f1d79d7fc1e1349965ccb7d4e81b9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Kconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 472fbe7..0c37eef 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -10,6 +10,17 @@ config BOOTBLOCK_BASE hex default 0x402f0400 +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + default 0x4c00 + +# We need to leave a gap between the bootblock and the ROM stage so that when +# it is "loaded" to a slightly different place in on chip memory, it doesn't +# clobber the metadata needed to actually enter it. +config ROMSTAGE_BASE + hex + default 0x402f5400 + # Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. # @@ -27,11 +38,6 @@ config STACK_SIZE hex default 0x1000 -config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - hex "offset of CBFS data in ROM" - default 0x2800 - ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. config CBFS_HEADER_ROM_OFFSET

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Patch set updated for coreboot: 577dc15 beaglebone: Put some code in romstage.c so we can tell if it ran.
by Gabe Black 15 Jul '13

15 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3581 -gerrit commit 577dc1595aa0c7a7247dee7589ab2046d7261e52 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:12:40 2013 -0700 beaglebone: Put some code in romstage.c so we can tell if it ran. The placeholder code in beaglebone's romstage.c didn't do anything, it just immediately tried to load the RAM stage and jump into it. That doesn't currently work, and there's no indication whether you actually successfully got into the ROM stage or not. This change adds a few lines which initialize the console and say "Hi" so that we can tell that the ROM stage is running. Change-Id: I45a0908c3ac65b21e0e5020428696d2e54933d0e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c index 3b9cae8..e66a3dd 100644 --- a/src/mainboard/ti/beaglebone/romstage.c +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -29,6 +29,9 @@ void main(void) { void *entry; + console_init(); + printk(BIOS_INFO, "Hello from romstage.\n"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

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Patch set updated for coreboot: 4e0f3ce ARM: Define custom ELF headers for ARM.
by Gabe Black 15 Jul '13

15 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3580 -gerrit commit 4e0f3ce6a31e831870b590d62c1bf23eb5bac0e4 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:03:47 2013 -0700 ARM: Define custom ELF headers for ARM. At least when building with the gnu toolchain, the headers the linker automatically generate save space for the actual ELF headers in one of the loadable segments. This creates two problems. First, the data you intended to be at the start of the image doesn't actually show up there, it's actually the ELF headers. Second, the ELF headers are essentially useless for firmware since there's currently nothing to tell you where they are, and even if there was, there isn't much of a reason to look at them. They're useful in userspace for, for instance, the dynamic linker, but not really in firmware. This change adds a PHDRS construct to each of the linker scripts used on ARM which define a single segment called to_load which does not have the flag set which would tell the linker to put headers in it. The first section defined in the script has ": to_load" to tell the linker which segment to put it in, and from that point on the other sections go in there by default. Change-Id: I24b721eb436d17afd234002ae82f9166d2fcf65d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/bootblock.lds | 7 ++++++- src/arch/armv7/coreboot_ram.ld | 7 ++++++- src/arch/armv7/romstage.ld | 7 ++++++- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds index 8370396..f16e72b 100644 --- a/src/arch/armv7/bootblock.lds +++ b/src/arch/armv7/bootblock.lds @@ -22,6 +22,11 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) +PHDRS +{ + to_load PT_LOAD; +} + TARGET(binary) SECTIONS { @@ -39,7 +44,7 @@ SECTIONS *(.rom.data.*); *(.rodata.*); _erom = .; - } = 0xff + } : to_load = 0xff /DISCARD/ : { *(.comment) diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 487f610..38eaca3 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -24,6 +24,11 @@ INCLUDE ldoptions ENTRY(stage_entry) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { . = CONFIG_SYS_SDRAM_BASE; @@ -38,7 +43,7 @@ SECTIONS *(.text.*); . = ALIGN(16); _etext = .; - } + } : to_load .ctors : { . = ALIGN(0x100); diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 568ac1a..0555fc4 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -30,6 +30,11 @@ OUTPUT_ARCH(arm) ENTRY(stage_entry) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { /* TODO make this a configurable option (per chipset). */ @@ -41,7 +46,7 @@ SECTIONS *(.text.stage_entry.armv7); *(.text.startup); *(.text); - } + } : to_load .romdata . : { *(.rodata);

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Patch set updated for coreboot: 1a95cb1 CBFS: Change the signature of cbfs_decompress.
by Stefan Reinauer 15 Jul '13

15 Jul '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3578 -gerrit commit 1a95cb1000ee1d0da7d345708d4e3a4958b087f0 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 04:57:37 2013 -0700 CBFS: Change the signature of cbfs_decompress. Instead of returning 0 on success and -1 on error, return the decompressed size of the data on success and 0 on error. The decompressed size is useful information to have that was being thrown away in that function. Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/include/cbfs_core.h | 2 +- payloads/libpayload/libcbfs/cbfs.c | 4 ++-- payloads/libpayload/libcbfs/cbfs_core.c | 9 +++------ src/include/cbfs_core.h | 2 +- src/lib/cbfs.c | 18 ++++++++++-------- src/lib/cbfs_core.c | 9 +++------ src/vendorcode/google/chromeos/vboot_loader.c | 8 ++++---- 7 files changed, 24 insertions(+), 28 deletions(-) diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 2dc1992..8be7212 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -217,7 +217,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type); -/* returns 0 on success, -1 on failure */ +/* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 2fb91bf..6243473 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -120,7 +120,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, if (! dest) return src; - if (cbfs_decompress(ntohl(orom->compression), + if (!cbfs_decompress(ntohl(orom->compression), src, dest, ntohl(orom->len))) @@ -146,7 +146,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) stage->entry); memset((void *) (uint32_t) stage->load, 0, stage->memlen); - if (cbfs_decompress(stage->compression, + if (!cbfs_decompress(stage->compression, ((unsigned char *) stage) + sizeof(struct cbfs_stage), (void *) (uint32_t) stage->load, diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 48a4b3a..1945813 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -196,19 +196,16 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) switch (algo) { case CBFS_COMPRESS_NONE: memcpy(dst, src, len); - return 0; + return len; #ifdef CBFS_CORE_WITH_LZMA case CBFS_COMPRESS_LZMA: - if (ulzma(src, dst) != 0) { - return 0; - } - return -1; + return ulzma(src, dst); #endif default: ERROR("tried to decompress %d bytes with algorithm #%x," "but that algorithm id is unsupported.\n", len, algo); - return -1; + return 0; } } diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 20636e2..b938427 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -218,7 +218,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type); -/* returns 0 on success, -1 on failure */ +/* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aba1bcc..400b8a5 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -112,7 +112,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, if (! dest) return src; - if (cbfs_decompress(ntohl(orom->compression), + if (!cbfs_decompress(ntohl(orom->compression), src, dest, ntohl(orom->len))) @@ -204,8 +204,8 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, LOG("Decompressing stage %s @ 0x%p (%d bytes)\n", name, &ramstage_region[rmodule_offset], stage->memlen); - if (cbfs_decompress(stage->compression, &stage[1], - &ramstage_region[rmodule_offset], stage->len)) + if (!cbfs_decompress(stage->compression, &stage[1], + &ramstage_region[rmodule_offset], stage->len)) return (void *) -1; if (rmodule_parse(&ramstage_region[rmodule_offset], &ramstage)) @@ -259,6 +259,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; + uint32_t final_size; if (stage == NULL) return (void *) -1; @@ -270,11 +271,12 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) /* Stages rely the below clearing so that the bss is initialized. */ memset((void *) (uint32_t) stage->load, 0, stage->memlen); - if (cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len)) + final_size = cbfs_decompress(stage->compression, + ((unsigned char *) stage) + + sizeof(struct cbfs_stage), + (void *) (uint32_t) stage->load, + stage->len); + if (!final_size) return (void *) -1; DEBUG("stage loaded.\n"); diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 39c1ff6..612fef2 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -196,19 +196,16 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) switch (algo) { case CBFS_COMPRESS_NONE: memmove(dst, src, len); - return 0; + return len; #ifdef CBFS_CORE_WITH_LZMA case CBFS_COMPRESS_LZMA: - if (ulzma(src, dst) != 0) { - return 0; - } - return -1; + return ulzma(src, dst); #endif default: ERROR("tried to decompress %d bytes with algorithm #%x," "but that algorithm id is unsupported.\n", len, algo); - return -1; + return 0; } } diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 10fa52d..b627af6 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -66,8 +66,8 @@ static void vboot_run_stub(struct vboot_context *context) vboot_region = cbmem_entry_start(vboot_entry); - if (cbfs_decompress(stage->compression, &stage[1], - &vboot_region[rmodule_offset], stage->len)) { + if (!cbfs_decompress(stage->compression, &stage[1], + &vboot_region[rmodule_offset], stage->len)) { printk(BIOS_DEBUG, "Couldn't decompress vboot stub.\n"); goto out; } @@ -221,8 +221,8 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, printk(BIOS_DEBUG, "Decompressing ramstage @ 0x%p (%d bytes)\n", &ramstage_region[rmodule_offset], stage->memlen); - if (cbfs_decompress(stage->compression, &stage[1], - &ramstage_region[rmodule_offset], stage->len)) + if (!cbfs_decompress(stage->compression, &stage[1], + &ramstage_region[rmodule_offset], stage->len)) return; if (rmodule_parse(&ramstage_region[rmodule_offset], &ramstage))

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Patch merged into coreboot/master: 4e7385b SMBIOS: Allow overriding default Manufacturer and Product names
by gerrit＠coreboot.org 14 Jul '13

14 Jul '13

the following patch was just integrated into master: commit 4e7385b58fcff0f59db6f0c4852a57e74f0d3b00 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:18:13 2012 +0200 SMBIOS: Allow overriding default Manufacturer and Product names The vendor and part name from coreboot is normally stored in these SMBIOS structure fields, but it can be useful to override them. On Lenovo ThinkPads an override is e.g. needed to convince the Linux thinkpad_acpi.c driver that it is actually running on a ThinkPad. Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/1556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> See http://review.coreboot.org/1556 for details. -gerrit

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Patch set updated for coreboot: 035c3ef Correct spelling of »shadow«, »setting« and »memory«
by Paul Menzel 14 Jul '13

14 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3768 -gerrit commit 035c3efe2aaf0488a253975eb31ad59547146b0c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 00:24:31 2013 +0200 Correct spelling of »shadow«, »setting« and »memory« The following commands were used to correct the spelling. $ git grep -l shaow | xargs sed -i 's/shaow/shadow/' $ git grep -i -l seting | xargs sed -i 's/eting/etting/' $ git grep -l memoy | xargs sed -i 's/memoy/memory/' Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/dsdt.asl | 2 +- src/mainboard/amd/bimini_fam10/dsdt.asl | 2 +- src/mainboard/amd/dbm690t/dsdt.asl | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 2 +- src/mainboard/amd/pistachio/dsdt.asl | 2 +- src/mainboard/amd/tilapia_fam10/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/acpi/smbus.asl | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 2 +- src/mainboard/asus/m5a88-v/dsdt.asl | 2 +- src/mainboard/avalue/eax-785e/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 2 +- src/mainboard/gigabyte/ma78gm/dsdt.asl | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 2 +- src/mainboard/kontron/kt690/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/lippert/toucan-af/dsdt.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 2 +- src/mainboard/tyan/s8226/dsdt.asl | 2 +- src/northbridge/via/vx800/examples/romstage.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- util/cbfstool/cbfs_image.c | 2 +- 33 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 7f83bf1..94757b5 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 6642680..03a00e0 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index d5eddfc..32df673 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 8de013f..01cb8dd 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -1653,7 +1653,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 94e1635..f55480d 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 060b6e3..3e5ba54 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -1565,7 +1565,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index ed0c4c2..e6816b0 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -1716,7 +1716,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asrock/e350m1/acpi/smbus.asl b/src/mainboard/asrock/e350m1/acpi/smbus.asl index e4ccfe3..ebf7ddb 100644 --- a/src/mainboard/asrock/e350m1/acpi/smbus.asl +++ b/src/mainboard/asrock/e350m1/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index c0835c4..5449d01 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -1618,7 +1618,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 11684c4..6e1ccd1 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 672af6f..dd766f7 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 26c9024..923a828 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index edbd2e5..848d43e 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 89d8e29..c221e0a 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index b393a61..a02366e 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1685,7 +1685,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 7f6dec3..53e12af 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1684,7 +1684,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 9d64e89..7890df7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -1222,7 +1222,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8, /* SMBUS slave data */ SMK1, 8, diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index aa889a3..c854067 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1638,7 +1638,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 4aef6a2..5e18375 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -1649,7 +1649,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index 6184bde..13e5620 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -1751,7 +1751,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 598dca0..20fe2d7 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index d24c379..53be887 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index 1efb3b5..79bc096 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -1639,7 +1639,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 7c3fb7a..b629137 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -431,7 +431,7 @@ g) Rx73h = 32h if (boot_mode == 3) { /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ - /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ + /* setting mtrr before back memory save s3 resume time about 0.14 seconds */ /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 4ab7212..5352705 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -52,7 +52,7 @@ static void nic_init(struct device *dev) mmio = resource->base; /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Reseting PHY... "); + printk(BIOS_DEBUG, "Resetting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index 19ae92b..4055174 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 10fa52d..cb3b486 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -101,7 +101,7 @@ static void log_msg(const char *fmt, va_list args) static void fatal_error(void) { - printk(BIOS_ERR, "vboot encountered fatal error. Reseting.\n"); + printk(BIOS_ERR, "vboot encountered fatal error. Resetting.\n"); hard_reset(); } diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 44a9fe8..eb9d574 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -395,7 +395,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, cbfs_print_entry_info(image, entry, stderr); // setup new entry - DEBUG("Seting new empty entry.\n"); + DEBUG("Setting new empty entry.\n"); entry = cbfs_find_next_entry(image, entry); new_size = (cbfs_get_entry_addr(image, next) - cbfs_get_entry_addr(image, entry));

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Patch merged into coreboot/master: d98cef1 lenovo/t60 lenovo/x60: Override SMBIOS Manufacturer to be LENOVO
by gerrit＠coreboot.org 14 Jul '13

14 Jul '13

the following patch was just integrated into master: commit d98cef1956aefecdfeba652085f301ea07118147 Author: Peter Stuge <peter(a)stuge.se> Date: Tue Jul 9 20:44:52 2013 +0200 lenovo/t60 lenovo/x60: Override SMBIOS Manufacturer to be LENOVO This is needed for the Linux thinkpad_acpi.c driver to load. Change-Id: I3d9549395556ffb0abfc3cb52b3d01386c34caa5 Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/3731 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3731 for details. -gerrit

1 0

Patch merged into coreboot/master: 7a6651c arm: Add and enable an arch specific version of memmove.
by gerrit＠coreboot.org 14 Jul '13

14 Jul '13

the following patch was just integrated into master: commit 7a6651ceb3ede6b35053ad65358d6994facc217e Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:15:22 2013 -0700 arm: Add and enable an arch specific version of memmove. This version is taken from arch/arm/lib/memmove.S in the Linux kernel. Change-Id: Ic875d0cf5b1cb407606530b7f465c406b134f0fa Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3763 for details. -gerrit

1 0

Patch merged into coreboot/master: ccdc005 x86: Add and enable an arch verson of memmove.
by gerrit＠coreboot.org 14 Jul '13

14 Jul '13

the following patch was just integrated into master: commit ccdc005b015f4211d0fa0d45393c5e4104620c53 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:08:30 2013 -0700 x86: Add and enable an arch verson of memmove. This is from memcpy_32.c in the Linux kernel. There was no copyright header in the original file either. Change-Id: Ifd259cb8a87615dce79ed1e551cc4bacb0414b4f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3762 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3762 for details. -gerrit

1 0

Patch merged into coreboot/master: 545c0ca Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.
by gerrit＠coreboot.org 14 Jul '13

14 Jul '13

the following patch was just integrated into master: commit 545c0caac8ff5cc5c8cc80b1c4d6dce5a2e17032 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jul 7 14:04:26 2013 -0700 Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove. Change-Id: I4b6a57e7d8e7e685c609b1d85368585b9dd197dc Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3761 for details. -gerrit

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coreboot-gerrit July 2013