coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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1377 discussions

Patch set updated for coreboot: 4055697 Drop obsolete CONSOLE_LOGBUF
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4256 -gerrit commit 40556974c47ea5883e69dccaca27c4831dcb89cc Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 13:47:46 2013 -0700 Drop obsolete CONSOLE_LOGBUF This was used by Ron 13ys ago and was never used again ever since. Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59320 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- payloads/libpayload/include/coreboot_tables.h | 2 +- src/console/Kconfig | 4 ---- src/console/Makefile.inc | 1 - src/console/logbuf_console.c | 21 --------------------- src/include/boot/coreboot_tables.h | 2 +- src/lib/coreboot_table.c | 6 ++---- 6 files changed, 4 insertions(+), 32 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 375d33b..26838e8 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -133,7 +133,7 @@ struct cb_console { #define CB_TAG_CONSOLE_SERIAL8250 0 #define CB_TAG_CONSOLE_VGA 1 // OBSOLETE #define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE -#define CB_TAG_CONSOLE_LOGBUF 3 +#define CB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE #define CB_TAG_CONSOLE_SROM 4 // OBSOLETE #define CB_TAG_CONSOLE_EHCI 5 diff --git a/src/console/Kconfig b/src/console/Kconfig index c23f862..12b942d 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -377,10 +377,6 @@ config DEFAULT_CONSOLE_LOGLEVEL help Map the log level config names to an integer. -config CONSOLE_LOGBUF - bool - default n - config NO_POST bool "Don't show any POST codes" default n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 9edec3c..62be1d2 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c -ramstage-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c diff --git a/src/console/logbuf_console.c b/src/console/logbuf_console.c deleted file mode 100644 index a76791d..0000000 --- a/src/console/logbuf_console.c +++ /dev/null @@ -1,21 +0,0 @@ -#include <console/console.h> - -#define LOGBUF_SIZE 1024 - -// KEEP THIS GLOBAL. -// I need the address so I can watch it with the ARIUM hardware. RGM. -char logbuf[LOGBUF_SIZE]; -int logbuf_offset = 0; - -static void logbuf_tx_byte(unsigned char byte) -{ - logbuf[logbuf_offset] = byte; - logbuf_offset = (logbuf_offset +1) % LOGBUF_SIZE; -} - -static const struct console_driver __console = { - .init = 0, - .tx_byte = logbuf_tx_byte, - .rx_byte = 0, - .tst_byte = 0, -};} diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 87819ce..aa8409a 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -163,7 +163,7 @@ struct lb_console { #define LB_TAG_CONSOLE_SERIAL8250 0 #define LB_TAG_CONSOLE_VGA 1 // OBSOLETE #define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE -#define LB_TAG_CONSOLE_LOGBUF 3 +#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE #define LB_TAG_CONSOLE_SROM 4 // OBSOLETE #define LB_TAG_CONSOLE_EHCI 5 #define LB_TAG_CONSOLE_SERIAL8250MEM 6 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index a0a806d..772729a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -137,7 +137,8 @@ static struct lb_serial *lb_serial(struct lb_header *header) #endif } -#if CONFIG_CONSOLE_SERIAL || CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ + CONFIG_CONSOLE_SERIAL_UART || CONFIG_USBDEBUG static void add_console(struct lb_header *header, u16 consoletype) { struct lb_console *console; @@ -157,9 +158,6 @@ static void lb_console(struct lb_header *header) #if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); #endif -#if CONFIG_CONSOLE_LOGBUF - add_console(header, LB_TAG_CONSOLE_LOGBUF); -#endif #if CONFIG_USBDEBUG add_console(header, LB_TAG_CONSOLE_EHCI); #endif

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Patch set updated for coreboot: 5f6afca libpayload: ARM: Don't leave alignment checking on after the exception test
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4255 -gerrit commit 5f6afca48cc72055a81a5c2230101616c5f14db2 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 20:48:06 2013 -0700 libpayload: ARM: Don't leave alignment checking on after the exception test Currently, the exception handling code on ARM in libpayload turns on alignment checks as an easy way to generate an exception for testing purposes. It was leaving it on which disabled unaligned accesses for other, unlreated code running later. This change adjusts the code so the original value of the alignment bit is restored after the test exception. Built and booted into depthcharge on pit with an unaligned accesses added after the call to exception_init in the depthcharge's main. Before this change, the access caused an exception. After this change, the access completed successfully. Change-Id: If92cab3cc8eabca7c5b0560ce88a8796a27fe3b2 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59372 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/exception.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/armv7/exception.c b/payloads/libpayload/arch/armv7/exception.c index 5e4e23d..9efc312 100644 --- a/payloads/libpayload/arch/armv7/exception.c +++ b/payloads/libpayload/arch/armv7/exception.c @@ -143,9 +143,8 @@ void exception_init(void) sctlr &= ~sctlr_te; /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ sctlr &= ~sctlr_v; - /* Enforce alignment. */ - sctlr |= sctlr_a; - set_sctlr(sctlr); + /* Enforce alignment temporarily. */ + set_sctlr(sctlr | sctlr_a); extern uint32_t exception_table[]; set_vbar((uintptr_t)exception_table); @@ -153,4 +152,7 @@ void exception_init(void) test_abort = 1; exception_test(); test_abort = 0; + + /* Restore alignment settings. */ + set_sctlr(sctlr); }

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Patch set updated for coreboot: 5031909 libpayload: Make the region to scan for the cb tables configurable.
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4254 -gerrit commit 50319097fc5df130a5060cf1cd5bbaa0eb71eac0 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 04:54:38 2013 -0700 libpayload: Make the region to scan for the cb tables configurable. The address range to scan for the coreboot tables varies from machine to machine based on the range memory occupies on the SOC being booted and on the amount of memory installed on the machine. To make libpayload work on different ARM systems with different needs, this change makes the region to scan configurable. In the future, we might want to come up with a more automatic mechanism like on x86, although there's less consistency on ARM as far as what ranges are even memory in the first place. Change-Id: Ib50efe25a6152171b0fbd0e324dbc5e89c527d6e Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59242 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/Config.in | 8 ++++++++ payloads/libpayload/arch/armv7/coreboot.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/Config.in b/payloads/libpayload/arch/armv7/Config.in index 6c1bf44..79cd676 100644 --- a/payloads/libpayload/arch/armv7/Config.in +++ b/payloads/libpayload/arch/armv7/Config.in @@ -33,4 +33,12 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config COREBOOT_INFO_RANGE_BASE + hex "Base of the range to search for the coreboot tables" + +config COREBOOT_INFO_RANGE_SIZE + hex "Size of the range to search for the coreboot tables" + default 0x4000000 + + endif diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index b6178f7..bc9b47e 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -284,7 +284,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0xbc000000), 0x4000000, info); + int ret = cb_parse_header(phys_to_virt(CONFIG_COREBOOT_INFO_RANGE_BASE), + CONFIG_COREBOOT_INFO_RANGE_SIZE, info); return (ret == 1) ? 0 : -1; }

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Patch set updated for coreboot: 24c773c lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4253 -gerrit commit 24c773c6e93965886eb0491b7a1b38c8b5a2aeec Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 19 10:49:29 2013 -0700 lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects LynxPoint-LP has a lot of GPEs and the "default" set has been moved to register 4 starting at bit offset 96. This means that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP but still bit 13 in LPT-H. suspend on falco and wake from usb 4 | 2013-06-19 10:49:17 | ACPI Enter | S3 5 | 2013-06-19 10:49:22 | ACPI Wake | S3 6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0 Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59265 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/audio.asl | 15 ++++++++++----- src/southbridge/intel/lynxpoint/acpi/usb.asl | 22 ++++++++++++++++++++-- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index a455328..2bc1168 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -27,10 +27,15 @@ Device (HDEF) { Name (_ADR, 0x001b0000) - // Power Resources for Wake - Name (_PRW, Package(){ - 13, // Bit 13 of GPE - 4 // Can wake from S4 state. - }) + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } } diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 5c1f6a5..6583cb3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -27,7 +27,16 @@ Device (EHCI) { Name(_ADR, 0x001d0000) - Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } // Leave USB ports on for to allow Wake from USB @@ -61,7 +70,16 @@ Device (XHCI) { Name(_ADR, 0x00140000) - Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } // Leave USB ports on for to allow Wake from USB

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Patch set updated for coreboot: 15449fb libpayload: Add missing break statement in coreboot table parsing
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4252 -gerrit commit 15449fbf19e2424a2e801e73ce64b55836588d89 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 12:06:50 2013 -0700 libpayload: Add missing break statement in coreboot table parsing Otherwise the code would try to parse GPIOs when encountering a mainboard entry in the coreboot table. This never caused any problems because the mainboard entry is parsed before the GPIO entry. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I1443bda8585a990a39115743d48304ec4b54bccb Reviewed-on: https://gerrit.chromium.org/gerrit/59292 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/arch/armv7/coreboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index 414b7fa..b6178f7 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -250,6 +250,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) #endif case CB_TAG_MAINBOARD: info->mainboard = (struct cb_mainboard *)ptr; + break; #ifdef CONFIG_CHROMEOS case CB_TAG_GPIO: cb_parse_gpios(ptr, info);

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Patch merged into coreboot/master: ef7a932 global: Fix usage of get_option() to make use of CB_CMOS_ codes
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit ef7a932b03668b2bbf51b3a6ada8260e1c297072 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Nov 23 19:22:53 2013 -0600 global: Fix usage of get_option() to make use of CB_CMOS_ codes Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4266 for details. -gerrit

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Patch set updated for coreboot: 51d2f86 vboot: use out_flags to indicate recovery mode
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4223 -gerrit commit 51d2f8695fc0cfde0bea034d6136a00587a95076 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:14:42 2013 -0700 vboot: use out_flags to indicate recovery mode In order to make the proper decision on loading the option rom or not the recovery mode setting needs to be known. Normally this is detected by asking the EC, but if recovery is requested with crossystem then the EC does not know about it. Instead we need to check the output flags from VbInit(). Change-Id: I09358e6fd979b4af6b37a13115ac34db3d98b09d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57474 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index c2cc0e1..828cfd2 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -41,8 +41,21 @@ static int vboot_enable_developer(void) return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); } + +static int vboot_enable_recovery(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) + return 0; + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); +} #else static inline int vboot_enable_developer(void) { return 0; } +static inline int vboot_enable_recovery(void) { return 0; } #endif int developer_mode_enabled(void) @@ -52,11 +65,20 @@ int developer_mode_enabled(void) int recovery_mode_enabled(void) { - /* TODO(reinauer): get information from VbInit. - * the recovery mode switch is not the only reason to go - * to recovery mode. + /* + * This is called in multiple places and has to detect + * recovery mode triggered from the EC and via shared + * recovery reason set with crossystem. + * + * If shared recovery reason is set: + * - before VbInit then get_recovery_mode_from_vbnv() is true + * - after VbInit then vboot_enable_recovery() is true + * + * Otherwise the mainboard handler for get_recovery_mode_switch() + * will detect recovery mode initiated by the EC. */ - return get_recovery_mode_switch() || get_recovery_mode_from_vbnv(); + return get_recovery_mode_switch() || get_recovery_mode_from_vbnv() || + vboot_enable_recovery(); } #if CONFIG_VBOOT_VERIFY_FIRMWARE

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Patch set updated for coreboot: 5220de2 vboot: Do not pass OPROM_MATTERS flag to VbInit
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4222 -gerrit commit 5220de2485711f619e44ed323cf66c628d29d3f7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:08:54 2013 -0700 vboot: Do not pass OPROM_MATTERS flag to VbInit Since we are using VBNV to determine if developer mode is active we do not need the messy OPROM hook magic any longer. Change-Id: I1b9effef3ef2aa84e916060d8e61ee42515a2b7c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57473 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/gnvs.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index ba1588d..5ee3665 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -49,15 +49,9 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - if (vboot_handoff != NULL) { - vboot_handoff->init_params.flags |= VB_INIT_FLAG_OPROM_MATTERS; - if (oprom_is_loaded) - vboot_handoff->init_params.flags |= - VB_INIT_FLAG_OPROM_LOADED; - + if (vboot_handoff != NULL) memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], ARRAY_SIZE(chromeos->vdat)); - } #endif #if CONFIG_ELOG

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Patch set updated for coreboot: c0b10a1 slippy/falco/peppy: Fix Chrome OS GPIO export in ACPI
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4221 -gerrit commit c0b10a127c0f3e5278c40e6382cce117fca20848 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:06:25 2013 -0700 slippy/falco/peppy: Fix Chrome OS GPIO export in ACPI The OIPG package needs to have >1 member to make the chromeos_acpi kernel driver do the right automagic sysfs topology creation. Additionally an "unimplemented" GPIO should be reported as 0xFF because 0 is a valid GPIO number. verify crossystem on slippy $ sudo crossystem | grep -e recoverysw_cur -e wpsw_cur recoverysw_cur = (error) wpsw_cur = 1 Change-Id: I06dff09152bde30a3ffe58b1defe9d299155472c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57471 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/acpi/chromeos.asl | 3 +-- src/mainboard/google/peppy/acpi/chromeos.asl | 3 +-- src/mainboard/google/slippy/acpi/chromeos.asl | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/falco/acpi/chromeos.asl b/src/mainboard/google/falco/acpi/chromeos.asl index e427821..4e9035b 100644 --- a/src/mainboard/google/falco/acpi/chromeos.asl +++ b/src/mainboard/google/falco/acpi/chromeos.asl @@ -18,7 +18,6 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect }) diff --git a/src/mainboard/google/peppy/acpi/chromeos.asl b/src/mainboard/google/peppy/acpi/chromeos.asl index e427821..4e9035b 100644 --- a/src/mainboard/google/peppy/acpi/chromeos.asl +++ b/src/mainboard/google/peppy/acpi/chromeos.asl @@ -18,7 +18,6 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect }) diff --git a/src/mainboard/google/slippy/acpi/chromeos.asl b/src/mainboard/google/slippy/acpi/chromeos.asl index e427821..4e9035b 100644 --- a/src/mainboard/google/slippy/acpi/chromeos.asl +++ b/src/mainboard/google/slippy/acpi/chromeos.asl @@ -18,7 +18,6 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect })

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Patch set updated for coreboot: 40be588 haswell boards: Enable VIRTUAL_DEV_SWITCH
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4220 -gerrit commit 40be588a90a724a0c76af1eb00bc22e3e49769c8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 3 10:45:08 2013 -0700 haswell boards: Enable VIRTUAL_DEV_SWITCH This config option was not enabled which was preventing the user from enabling developer mode from recovery mode. With this enabled we can disable the "dev mode by default" behavior and let people enable it by entering recovery mode. This will make the firmware behave like a typical chromeos device. Peppy is left in "default dev mode" until after bringup. 1) boot slippy in normal mode by default 2) enter recovery mode with servo button 3) Ctrl+D on USB keyboard to enter developer mode 4) boot slippy in developer mode Change-Id: I414c0d10dd0489e3c89798f75a2872a43297c8d8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57350 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/falco/chromeos.c | 2 +- src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/google/slippy/chromeos.c | 2 +- 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 3a08086..3c0c576 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 1b70fde..51d625b 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* The dev-switch is virtual */ int get_developer_mode_switch(void) { - return 1; + return 0; } /* There are actually two recovery switches. One is the magic keyboard chord, diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 5eb8b95..74a04fb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index a53ac00..aaea947 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 1b70fde..51d625b 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* The dev-switch is virtual */ int get_developer_mode_switch(void) { - return 1; + return 0; } /* There are actually two recovery switches. One is the magic keyboard chord,

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coreboot-gerrit December 2013