coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

1 participants
1377 discussions

New patch to review for coreboot: 753ee18 AMD hudson: add IMC fan control support
by WANG Siyuan 02 Dec '13

02 Dec '13

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4300 -gerrit commit 753ee1862dba469801ea68b66388057dd5432463 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Dec 2 10:18:04 2013 +0800 AMD hudson: add IMC fan control support imc_reg_init: init fan control related registers. enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable it here. Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 3 ++ src/southbridge/amd/agesa/hudson/imc.c | 70 +++++++++++++++++++++++++++ src/southbridge/amd/agesa/hudson/imc.h | 7 +++ 3 files changed, 80 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 6a097fc..54a93d2 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -19,6 +19,9 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c +romstage-y += imc.c +ramstage-y += imc.c + # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c new file mode 100644 index 0000000..19fa840 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -0,0 +1,70 @@ +#include "imc.h" +#include <arch/io.h> +#include <delay.h> +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "Fch.h" +#include "FchCommonCfg.h" +#include "FchPlatform.h" + +void imc_reg_init(void) +{ + /* Init Power Management Block 2 (PM2) Registers. + * Check BKDG for AMD Family 16h for details. */ + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff); + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff); +#endif + +#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + UINT8 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); + PciData &= (UINT8)0x8F; + PciData |= 0x10; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); +#endif +} + +#ifndef __PRE_RAM__ +void enable_imc_thermal_zone(void) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT8 FunNum; + UINT8 regs[9]; + int i; + + regs[0] = 0; + regs[1] = 0; + FunNum = Fun_80; + for (i=0; i<=1; i++) + WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number + WaitForEcLDN9MailboxCmdAck(&StdHeader); + + for (i=2; i<=9; i++) { + ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + } + /* enable thermal zone 0 */ + regs[2] |= 1; + regs[0] = 0; + regs[1] = 0; + FunNum = Fun_81; + for (i=0; i<=9; i++) + WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number + WaitForEcLDN9MailboxCmdAck(&StdHeader); +} +#endif diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h new file mode 100644 index 0000000..f117ea4 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/imc.h @@ -0,0 +1,7 @@ +#ifndef HUDSON_IMC_H +#define HUDSON_IMC_H + +void imc_reg_init(void); +void enable_imc_thermal_zone(void); + +#endif

1 0

Patch merged into coreboot/master: 595f87e slippy/falco/peppy: Fix SPD GPIO initialization.
by gerrit＠coreboot.org 01 Dec '13

01 Dec '13

the following patch was just integrated into master: commit 595f87e0ecef610601b28aaf7ccf9c73fde76aae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jun 13 17:29:36 2013 -0700 slippy/falco/peppy: Fix SPD GPIO initialization. SPD GPIOs were being read prior to initialization in romstage_common. To fix, pass the copy_spd function to romstage_common, to be called at the appropriate time (after PCH init, before DRAM init). Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58608 See http://review.coreboot.org/4237 for details. -gerrit

1 0

Patch merged into coreboot/master: 908279e Butterfly: Force DDR refresh rate to 2x.
by gerrit＠coreboot.org 01 Dec '13

01 Dec '13

the following patch was just integrated into master: commit 908279e86b83d464d351b4a9900569ad907cd1ba Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Wed May 8 11:45:23 2013 -0700 Butterfly: Force DDR refresh rate to 2x. Due to OEM request, always set DDR refresh rate at 2x. Change-Id: I81a4f57aca6388551dca6effbd9a4ac1a97e4f5a Reviewed-on: https://gerrit.chromium.org/gerrit/50477 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4214 for details. -gerrit

1 0

Patch merged into coreboot/master: 62ee959 Add DDR refresh config to pei data structure.
by gerrit＠coreboot.org 01 Dec '13

01 Dec '13

the following patch was just integrated into master: commit 62ee9597c5c34e2e3f51e22b6a094d574dd2f3cb Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Wed May 8 11:41:04 2013 -0700 Add DDR refresh config to pei data structure. Allow platform customized DDR config, including forcing refresh rate to 2x. Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2 Reviewed-on: https://gerrit.chromium.org/gerrit/50476 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4213 for details. -gerrit

1 0

Patch merged into coreboot/master: f96a70e Fix build with USE_OPTION_TABLE
by gerrit＠coreboot.org 01 Dec '13

01 Dec '13

the following patch was just integrated into master: commit f96a70ee0794c017c0ee7d100b1e32530283b6a1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Nov 30 21:06:18 2013 +0200 Fix build with USE_OPTION_TABLE Parallelized build might try to build SMM before option_table.h is created. Remove related redundant explicit rules. Change-Id: Ida8b5c408af05adcf3210ce7bfc8a1e5959194c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4299 for details. -gerrit

1 0

Patch merged into coreboot/master: 1f47914 H8: Move EC GPE declaration to mainboard
by gerrit＠coreboot.org 01 Dec '13

01 Dec '13

the following patch was just integrated into master: commit 1f47914c8c3e67878b259221bd325a115f0a9254 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 10:13:28 2013 +0100 H8: Move EC GPE declaration to mainboard Change-Id: Iefc481f09268dd15bbc3cbfa8bdd110d44383f6a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4281 for details. -gerrit

1 0

Patch merged into coreboot/master: 12f523f lynxpoint: Do not clear ACPI NVS region on resume
by gerrit＠coreboot.org 01 Dec '13

01 Dec '13

the following patch was just integrated into master: commit 12f523f839f36d70adfe989ccc24b28e4ae29811 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 07:49:55 2013 -0700 lynxpoint: Do not clear ACPI NVS region on resume There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4210 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2013