coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 7714801 elog: Get rid of elog_reinit_descriptor.
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 771480143ef4529e29b6af9399543ba931a8f0e2 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 24 17:36:53 2013 -0700 elog: Get rid of elog_reinit_descriptor. This function was just a wrapper around elog_init_descriptor, and all it did was pass the current backing store location and size back in so it would be reused. Those values, which never change, are now set in elog_setup_descriptors, eliminating those parameters to init and eliminating the need for _reinit_. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Change-Id: I133768aa798dfc10f32e14db95235a88666890c3 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49307 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4242 for details. -gerrit

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Patch merged into coreboot/master: 7900d42 elog: Eliminate the second in memory copy of the event log.
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 7900d42c1e762a37cc041fdce69af8c2e8f16391 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 24 04:11:40 2013 -0700 elog: Eliminate the second in memory copy of the event log. The event log driver keeps two copies of the event log in memory, one to take the place of the historically memory mapped image of flash which is now read and written manually, and one originally intended to be an in memory cache of flash. Since both are now just copies in memory, there's no value in having them both and keeping them in sync. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Cleared the log by echoing a 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list again. Change-Id: Ibed62a10c78884849726aa15ec795ab2914afc35 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49306 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4241 for details. -gerrit

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Patch merged into coreboot/master: ff906f4 Make elog_shrink not depend on having seperate memory/flash descriptors.
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit ff906f45d591fecf0a1e89e55004385ba7d0e889 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 24 03:16:21 2013 -0700 Make elog_shrink not depend on having seperate memory/flash descriptors. The way elog_shrink currently works is that it completely clears the data in the flash/flash descriptor and then recreates it using the part of the log it's going to keep as stored in the memory descriptor. That scheme depends on there being to independent copies of the log. This change reworks elog_shrink so that it moves the data it wants to keep within a single descriptor and then propogates it to the other and to flash intact. This way, when one of the descriptors goes away, all we have to do is remove the code that would update it. Built and booted into ChromeOS on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Echoed a 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list. BRANCH=None Change-Id: I50d77a4f00ea3c6b3e0ec8996dab1a3b31580205 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49305 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4240 for details. -gerrit

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Patch merged into coreboot/master: c270bc7 elog: Get rid of the staging_header variable.
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit c270bc7c7bb67bfc1204661a4c9af6c9419a6bf6 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Apr 23 19:36:01 2013 -0700 elog: Get rid of the staging_header variable. The header is at the start of the log. There's no reason to either keep a seperate pointer to it, or to keep a copy of it in some other bit of memory. Built and booted on Link and used 'mosys eventlog list' to list the contents of the log. Ran for x in $(seq 1 2000); do cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog; done And ran mosys eventlog list again to verify that the log had been shrunk correctly. Change-Id: I2afcd52c0ce5bbb662ac56f2895cdbea28d5c2ce Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49304 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4239 for details. -gerrit

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Patch merged into coreboot/master: ab61c8a lynxpoint: move all pcie device handling to pcie.c
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit ab61c8afa3191ae4a79fe42113bf9345d15275cf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:28:04 2013 -0500 lynxpoint: move all pcie device handling to pcie.c Some of the pcie logic was located in pch.c as well as pcie.c. Move all pcie logic to the same pcie.c file. This is a straight cut-and-paste (no logic changes) except for a rename from pch_pcie_enable() -> pch_pcie_enable_dev(). Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59277 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4251 for details. -gerrit

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Patch merged into coreboot/master: ca76001 lynxpoint: expose pch_disable_devfn()
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit ca76001770e74d327d30863987f0fe58ff1c8449 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:20:37 2013 -0500 lynxpoint: expose pch_disable_devfn() The function to disable devices was formerly named pch_hide_devfn(). This routine was doing more than hiding devices. It was disabling them, i.e. turning them off. Therefore, rename it to pch_disable_devfn(). Also, allow external callers to this function. Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59276 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4250 for details. -gerrit

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Patch merged into coreboot/master: f4ab711 lynxpoint: expose iobp functions
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit f4ab7116ed6cdde06686481dfb2a47e070c09929 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:12:48 2013 -0500 lynxpoint: expose iobp functions The iobp functions are useful to may of the southbridge devices as certain values need to be updated to properly initialize the devices. Therefore expose read, write, and updated iobp functions. Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59275 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4249 for details. -gerrit

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Patch merged into coreboot/master: 67eefdb Add description to MAINBOARD_VENDOR string so it can be overridden
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 67eefdb21791dbd8d9116fbde0866dcdc99e610e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 18 13:19:26 2013 -0700 Add description to MAINBOARD_VENDOR string so it can be overridden A quirk of the Kconfig used in coreboot is that config options cannot be overriden by local config changes unless they have a description string. 1) Add CONFIG_MAINBOARD_VENDOR="Custom" to local config 2) Build and flash coreboot 3) cat /sys/class/dmi/id/sys_vendor and look for "Custom" Change-Id: I1b5f2124cd4a22c056c025143ae5bcaafa6b03f0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59088 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4248 for details. -gerrit

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Patch merged into coreboot/master: 928f407 peppy: Add an inverted input GPIO type
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 928f407328fb7109a575eaf3895a0d97c70fe29e Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Tue Jun 11 20:30:09 2013 -0700 peppy: Add an inverted input GPIO type The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. Also sync pin states from Falco initial commit. Reference change: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Change-Id: I66e136d389d53a367436d816fa84dacdc8e86bad Reviewed-on: https://gerrit.chromium.org/gerrit/58334 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Dave Parker <dparker(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)google.com> See http://review.coreboot.org/4247 for details. -gerrit

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Patch set updated for coreboot: 4c6dccc vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.
by Andrew Wu 02 Dec '13

02 Dec '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976 -gerrit commit 4c6dccc1038eccee102ef8a0adf8a7c69d5f7068 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 31 20:12:09 2013 +0800 vortex86ex: Change PCI S/B resource reservation functions for more I/O devices. Originally, Vortex86EX PCI S/B internal resource reservation functions can only support one big legacy I/O device space (0-0xfff). Change function signature to support other non-legacy I/O device space in the future. Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 61dceea..5be8575 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -505,21 +505,21 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, u32 io_resv_size) +static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) { struct resource *res; - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = io_resv_size; + res = new_resource(dev, index); + res->base = base; + res->size = size; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; - res = new_resource(dev, 2); + res = new_resource(dev, index); res->base = 0x100000000LL - flash_size; res->size = flash_size; res->limit = 0xffffffffUL; @@ -542,11 +542,11 @@ static void vortex86_sb_read_resources(device_t dev) flash_size = 64 * 1024 * 1024; } - /* Reserve space for I/O */ - vortex86_sb_set_io_resv(dev, 0x1000UL); + /* Reserve space for legacy I/O */ + vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL); /* Reserve space for flash */ - vortex86_sb_set_spi_flash_size(dev, flash_size); + vortex86_sb_set_spi_flash_size(dev, 2, flash_size); } static void southbridge_init_func1(struct device *dev)

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coreboot-gerrit December 2013