coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 3457418 falco: Update panel power sequence timings
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 34574185335111c72c6585dfd10c8b79ac019eba Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 11 16:17:56 2013 -0700 falco: Update panel power sequence timings These are based on the datasheet and I included the timing values I used from the docs. Change-Id: Ib75b2c5e50ac09d1e4cf9dd22229bb0f0a8965a4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58540 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4234 for details. -gerrit

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Patch set updated for coreboot: f0c120f Fix builds with disabled ChromeOS
by Kyösti Mälkki 02 Dec '13

02 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4291 -gerrit commit f0c120f4ae544cffbf27f0774c09886f5d1393d4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Aug 18 18:08:40 2013 +0300 Fix builds with disabled ChromeOS Change-Id: I1a59405499deceed7df01a03834be72830e6578f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/samsung/lumpy/acpi_tables.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 13e9e0f..4aeccbc 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -30,7 +30,9 @@ #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <ec/acpi/ec.h> +#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> +#endif extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -98,9 +100,10 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; +#if CONFIG_CHROMEOS // TODO(reinauer) this could move elsewhere? chromeos_init_vboot(&(gnvs->chromeos)); - +#endif acpi_update_thermal_table(gnvs); gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO;

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Patch set updated for coreboot: f6c110b Build without ChromeOS
by Kyösti Mälkki 02 Dec '13

02 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3978 -gerrit commit f6c110bee9731af25bddf557aa3189997745c9eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:56 2013 +0300 Build without ChromeOS Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/google/chromeos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a564608..a707717 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -24,7 +24,7 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" - default y + default n select TPM help Enable ChromeOS specific features like the GPIO sub table in

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Patch set updated for coreboot: 7ff34ce Add option to disable ChromeOS
by Kyösti Mälkki 02 Dec '13

02 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3977 -gerrit commit 7ff34cec146b2c8653de1e86050cd9b45df5181c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:25 2013 +0300 Add option to disable ChromeOS Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/falco/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/peppy/Kconfig | 2 +- src/mainboard/google/pit/Kconfig | 2 +- src/mainboard/google/slippy/Kconfig | 2 +- src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/intel/wtm2/Kconfig | 2 +- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 2 +- src/vendorcode/google/chromeos/Kconfig | 20 ++++++++++++-------- 15 files changed, 26 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index e9ad6ef..78c998a 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 3a08086..3eb67ac 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select MMCONF_SUPPORT select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index b74c604..d1e809e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 191e856..d8a4e7a 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 5eb8b95..1913ef0 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select MMCONF_SUPPORT select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index 89ffb5b..ae6e693 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select BOARD_ROMSIZE_KB_4096 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_INIT_TIMER diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index a53ac00..7ca737d 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select MMCONF_SUPPORT select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 91bd66d..279132d 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_I2C select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select DRIVER_TI_TPS65090 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index a316277..7ee8fd4 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 23f2ebe..710094e 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select LAPIC_MONOTONIC_TIMER config MAINBOARD_DIR diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index fd98485..01082d4 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select GFXUMA - #select CHROMEOS + #select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT config MAINBOARD_DIR diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index d5b55d8..99ed53c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 91dc3b6..032b4b5 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select BOARD_ROMSIZE_KB_8192 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 select GFXUMA diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index f4f8e4d..e1e0cfa 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select BOARD_ROMSIZE_KB_8192 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 select GFXUMA select HAVE_ACPI_RESUME diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index d5ca212..a564608 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -16,17 +16,22 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config MAINBOARD_HAS_CHROMEOS + def_bool n + +menu "ChromeOS" + depends on MAINBOARD_HAS_CHROMEOS + config CHROMEOS - bool - default n + bool "Build for ChromeOS" + default y select TPM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build. -menu "ChromeOS" - depends on CHROMEOS +if CHROMEOS config VBNV_OFFSET hex @@ -66,12 +71,9 @@ config FLASHMAP_OFFSET help Offset of flash map in firmware image -endmenu - config VBOOT_VERIFY_FIRMWARE bool "Verify firmware with vboot." default n - depends on CHROMEOS help Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage and boot loader. @@ -111,8 +113,10 @@ config VBOOT_RAMSTAGE_INDEX config NO_TPM_RESUME bool default n - depends on CHROMEOS help On some boards the TPM stays powered up in S3. On those boards, booting Windows will break if the TPM resume command is sent during an S3 resume. + +endif +endmenu

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Patch merged into coreboot/master: 735d212 peppy: Port updates from slippy/falco boards
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 735d212cdb15b64021356eae452ac839cccaf988 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 11 08:49:55 2013 -0700 peppy: Port updates from slippy/falco boards - Add HDA verb table - Add on-board device table - Add panel power sequencing values Change-Id: I1b3450c2740ec1d930f157a9b23550e1efc8668f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58197 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4233 for details. -gerrit

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Patch set updated for coreboot: 9119295 haswell: Update pei_data to match ref code
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4219 -gerrit commit 91192954ba0847f5ba94a10e5df5cbded9e57fdb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 3 10:41:12 2013 -0700 haswell: Update pei_data to match ref code - Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/romstage.c | 28 ++++++++++++------ src/mainboard/google/peppy/romstage.c | 26 +++++++++++------ src/mainboard/google/slippy/romstage.c | 26 +++++++++++------ src/mainboard/intel/baskingridge/romstage.c | 44 +++++++++++++++++++---------- src/mainboard/intel/wtm2/romstage.c | 24 ++++++++++------ src/northbridge/intel/haswell/pei_data.h | 19 ++++++++++++- 6 files changed, 116 insertions(+), 51 deletions(-) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 74ace9b..e284491 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -129,17 +129,27 @@ void mainboard_romstage_entry(unsigned long bist) // 3 = disable dimm 0+1 on channel dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, + // Enable 2x refresh mode + ddr_refresh_2x: 1, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Port A, CN8 */ - { 0x0040, 1, 0 }, /* P1: Port B, CN9 */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 1, 3 }, /* P7: USB2 Port */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN8 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Port B, CN9 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P7: USB2 Port */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 656f3bc..bb65f00 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -132,15 +132,23 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: USB 2.0 Port */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ + /* Length, Enable, OCn#, Location */ + { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, /* P4: Port B, CN6 */ + USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index d979203..a93196a 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -159,15 +159,23 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ + /* Length, Enable, OCn#, Location */ + { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, /* P4: Port B, CN6 */ + USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1dc4960..ee516d9 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -95,21 +95,35 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 0, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */ - { 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */ - { 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */ - { 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */ - { 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */ - { 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */ - { 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */ - { 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */ - { 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */ - { 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */ - { 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */ - { 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ + USB_PORT_DOCK }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 0a24e48..c4cce2e 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -101,14 +101,22 @@ void mainboard_romstage_entry(unsigned long bist) max_ddr3_freq: 1600, usb2_ports: { /* Length, Enable, OCn# */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */ - { 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */ + { 0x40, 1, USB_OC_PIN_SKIP, /* P0: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P1: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P2: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P3: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P4: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P5: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P6: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P7: */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 7311829..b7dc8cf 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,16 +31,31 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 12 +#define PEI_VERSION 13 #define MAX_USB2_PORTS 16 #define MAX_USB3_PORTS 16 #define USB_OC_PIN_SKIP 8 +enum usb2_port_location { + USB_PORT_BACK_PANEL = 0, + USB_PORT_FRONT_PANEL, + USB_PORT_DOCK, + USB_PORT_MINI_PCIE, + USB_PORT_FLEX, + USB_PORT_INTERNAL, + USB_PORT_SKIP +}; + +/* Usb Port Length: + * [16:4] = length in inches in octal format + * [3:0] = decimal point + */ struct usb2_port_setting { uint16_t length; uint8_t enable; uint8_t over_current_pin; + uint8_t location; } __attribute__((packed)); struct usb3_port_setting { @@ -75,6 +90,8 @@ struct pei_data // 3 = disable dimm 0+1 on channel int dimm_channel0_disabled; int dimm_channel1_disabled; + /* Enable 2x Refresh Mode */ + int ddr_refresh_2x; /* Data read from flash and passed into MRC */ unsigned char *mrc_input; unsigned int mrc_input_len;

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Patch merged into coreboot/master: 5cc5842 vboot: use out_flags to indicate dev mode
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit 5cc5842fbb11efd5baaca30febe925e024801499 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 4 08:57:54 2013 -0500 vboot: use out_flags to indicate dev mode In order to make the proper decision on loading the option rom or not the developer mode setting needs to be known. Under early firmware selection it is possible to know the state of developer mode by a flag in out flags. Use this flag when early firmware selection is being employed to determine if developer mode is enabled or not. Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57380 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4218 for details. -gerrit

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Patch merged into coreboot/master: d6a4468 lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
by gerrit＠coreboot.org 02 Dec '13

02 Dec '13

the following patch was just integrated into master: commit d6a446892724b77553c4372d38f59f451609cb1d Author: Peter Stuge <peter(a)stuge.se> Date: Sat Jul 6 20:10:36 2013 +0200 lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String The Linux thinkpad_acpi.c driver looks for this string while reading information about the system it is running on. This commit does not make the module load but it is one of several things that the module looks for on a ThinkPad. Change-Id: Ia48bbd85ba4d528063695345b0f968d264573341 Signed-off-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/3779 for details. -gerrit

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New patch to review for coreboot: 891e087 qemu/x86: make sure it still builds
by Ronald G. Minnich 02 Dec '13

02 Dec '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4303 -gerrit commit 891e087e79c86adb1cd6b9855c50aa59bb00c4c6 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Dec 2 09:14:33 2013 -0800 qemu/x86: make sure it still builds At some point, it appears that we must select GENERATE_ACPI_TABLES or it no longer builds. Since we seem to require ACPI now we might as well just lock it on. Change-Id: If1419cd06d099985b444bab9b31b8149425d1a42 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/mainboard/emulation/qemu-q35/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 0d4d07a..c36dded 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select GENERATE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index cd7024b..baa8b3b 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select GENERATE_ACPI_TABLES config MAINBOARD_DIR string

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Patch set updated for coreboot: 3457418 falco: Update panel power sequence timings
by Stefan Reinauer 02 Dec '13

02 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4234 -gerrit commit 34574185335111c72c6585dfd10c8b79ac019eba Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 11 16:17:56 2013 -0700 falco: Update panel power sequence timings These are based on the datasheet and I included the timing values I used from the docs. Change-Id: Ib75b2c5e50ac09d1e4cf9dd22229bb0f0a8965a4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58540 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/devicetree.cb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index b9bc47f..21858e7 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -15,11 +15,11 @@ chip northbridge/intel/haswell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) + register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) + register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) device cpu_cluster 0 on chip cpu/intel/socket_rPGA989

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coreboot-gerrit December 2013