coreboot-gerrit December 2013

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Patch set updated for coreboot: 0ceff74 AMD K8 (rev F): Move rev F0/F1 workaround to header
by Kyösti Mälkki 23 Dec '13

23 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4568 -gerrit commit 0ceff74cbef8e11897a4fa2182754a3d54fcaecf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 23 09:55:33 2013 +0200 AMD K8 (rev F): Move rev F0/F1 workaround to header Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/serengeti_cheetah/romstage.c | 4 ---- src/mainboard/asus/m2n-e/romstage.c | 4 ---- src/mainboard/asus/m2v-mx_se/romstage.c | 4 ---- src/mainboard/asus/m2v/romstage.c | 4 ---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 4 ---- src/mainboard/gigabyte/m57sli/romstage.c | 4 ---- src/mainboard/hp/dl145_g3/romstage.c | 4 ---- src/mainboard/msi/ms7260/romstage.c | 4 ---- src/mainboard/nvidia/l1_2pvv/romstage.c | 4 ---- src/mainboard/supermicro/h8dme/romstage.c | 4 ---- src/mainboard/supermicro/h8dmr/romstage.c | 4 ---- src/mainboard/tyan/s2912/romstage.c | 4 ---- src/northbridge/amd/amdk8/amdk8.h | 3 +++ src/northbridge/amd/amdk8/raminit_f_dqs.c | 3 --- 14 files changed, 3 insertions(+), 51 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 20fe0f3..8828316 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 62891ff..fbda03a 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -20,10 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index dc60a6e..e487aca 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -24,10 +24,6 @@ unsigned int get_sbdn(unsigned bus); -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 509df90..f191859 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -24,10 +24,6 @@ unsigned int get_sbdn(unsigned bus); -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 09e9857..795d39c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -21,10 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 3004f7f..4f6e07c 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 4b31bb7..1b24d5e 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -25,10 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 0252402..7331bbf 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -20,10 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 5530579..798d6f6 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d92c348..a620fc5 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -16,10 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 268f120..4a596b1 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 2345a84..1364aa6 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index e001706..05117f7 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -3,6 +3,9 @@ #define AMDK8_H #if CONFIG_K8_REV_F_SUPPORT + +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 + #include "f.h" #else #include "pre_f.h" diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 95987b2..0781c79 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -467,9 +467,6 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) } -#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 -#endif static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) {

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Patch set updated for coreboot: b039953 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
by Kyösti Mälkki 23 Dec '13

23 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4558 -gerrit commit b039953dcea6750ac4b454cd234591eff32c027c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 20:48:40 2013 +0200 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/model_fxx/init_cpus.c | 3 ++- src/cpu/amd/model_fxx/model_fxx_init.c | 2 ++ src/mainboard/asus/a8n_e/Kconfig | 4 ---- src/mainboard/msi/ms7135/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 8 ++++---- 5 files changed, 8 insertions(+), 13 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 7121642..6ba5025 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -293,11 +293,12 @@ static u32 init_cpus(u32 cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); +#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); #endif - +#endif STOP_CAR_AND_CPU(); } diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 4beecab..260e83e 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -31,11 +31,13 @@ #if CONFIG_WAIT_BEFORE_CPUS_INIT void cpus_ready_for_init(void) { +#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif +#endif } #endif diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index acb528b..ba2e5b1 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 14c0f49..76b6625 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -24,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7135" diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 294002e..ce2460e 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -37,10 +37,6 @@ config WAIT_BEFORE_CPUS_INIT bool default n -config MEM_TRAIN_SEQ - int - default 0 - # Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and # single DIMM is indeed unreliable without it). config K8_FORCE_2T_DRAM_TIMING @@ -99,6 +95,10 @@ if DIMM_DDR2 endif endif #DIMM_DDR2 +config MEM_TRAIN_SEQ + int + default 0 + endif #K8_REV_F_SUPPORT config IOMMU

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New patch to review for coreboot: 1e6c94e AMD K8 (rev F): Move rev F0/F1 workaround to header
by Kyösti Mälkki 23 Dec '13

23 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4568 -gerrit commit 1e6c94eeca57923b40c72236d7808abfb6809fde Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 23 09:55:33 2013 +0200 AMD K8 (rev F): Move rev F0/F1 workaround to header Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/serengeti_cheetah/romstage.c | 4 ---- src/mainboard/asus/m2n-e/romstage.c | 4 ---- src/mainboard/asus/m2v-mx_se/romstage.c | 4 ---- src/mainboard/asus/m2v/romstage.c | 4 ---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 4 ---- src/mainboard/gigabyte/m57sli/romstage.c | 4 ---- src/mainboard/hp/dl145_g3/romstage.c | 4 ---- src/mainboard/msi/ms7260/romstage.c | 4 ---- src/mainboard/nvidia/l1_2pvv/romstage.c | 4 ---- src/mainboard/supermicro/h8dme/romstage.c | 4 ---- src/mainboard/supermicro/h8dmr/romstage.c | 4 ---- src/mainboard/tyan/s2912/romstage.c | 4 ---- src/northbridge/amd/amdk8/amdk8.h | 3 +++ src/northbridge/amd/amdk8/raminit_f_dqs.c | 3 --- 14 files changed, 3 insertions(+), 51 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 20fe0f3..8828316 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 62891ff..fbda03a 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -20,10 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index dc60a6e..e487aca 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -24,10 +24,6 @@ unsigned int get_sbdn(unsigned bus); -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 509df90..f191859 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -24,10 +24,6 @@ unsigned int get_sbdn(unsigned bus); -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 09e9857..795d39c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -21,10 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 3004f7f..4f6e07c 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 4b31bb7..1b24d5e 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -25,10 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 0252402..7331bbf 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -20,10 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 5530579..798d6f6 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d92c348..a620fc5 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -16,10 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 268f120..4a596b1 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 2345a84..1364aa6 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index e001706..05117f7 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -3,6 +3,9 @@ #define AMDK8_H #if CONFIG_K8_REV_F_SUPPORT + +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 + #include "f.h" #else #include "pre_f.h" diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 95987b2..0781c79 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -467,9 +467,6 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) } -#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 -#endif static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) {

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New patch to review for coreboot: 2c36767 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
by Kyösti Mälkki 23 Dec '13

23 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4567 -gerrit commit 2c36767596dee7786b8415734dc0455ae43594cb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 23:14:27 2013 +0200 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/serengeti_cheetah/romstage.c | 2 -- src/mainboard/asus/m2n-e/romstage.c | 2 -- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 -- src/mainboard/gigabyte/m57sli/romstage.c | 2 -- src/mainboard/hp/dl145_g3/romstage.c | 2 -- src/mainboard/msi/ms7260/romstage.c | 2 -- src/mainboard/nvidia/l1_2pvv/romstage.c | 2 -- src/mainboard/supermicro/h8dme/romstage.c | 2 -- src/mainboard/supermicro/h8dmr/romstage.c | 2 -- src/mainboard/tyan/s2912/romstage.c | 2 -- src/northbridge/amd/amdk8/raminit_f_dqs.c | 5 +++-- 11 files changed, 3 insertions(+), 22 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 8d985b7..20fe0f3 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -137,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index b6d7625..62891ff 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -123,10 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid); -#if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); -#endif setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index e06cb5b..09e9857 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -147,9 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 469e195..3004f7f 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -150,9 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 3d2d3cd..4b31bb7 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -160,9 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); wait_all_core0_started(); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 96a0c1b..0252402 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -141,10 +141,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); -#endif setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 4497a37..5530579 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -139,9 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 9363c63..d92c348 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -207,9 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif /* dump_smbus_registers(); */ setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index daae389..268f120 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -134,9 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 511f902..2345a84 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -137,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 4438340..95987b2 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1793,6 +1793,7 @@ static void clear_mtrr_dqs(unsigned tom2_k) } } +#if CONFIG_MEM_TRAIN_SEQ == 1 static void set_htic_bit(unsigned i, unsigned val, unsigned bit) { uint32_t dword; @@ -1802,8 +1803,6 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit) pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword); } - -#if CONFIG_MEM_TRAIN_SEQ == 1 static unsigned get_htic_bit(unsigned i, unsigned bit) { uint32_t dword; @@ -1822,7 +1821,9 @@ static void wait_till_sysinfo_in_ram(void) static void set_sysinfo_in_ram(unsigned val) { +#if CONFIG_MEM_TRAIN_SEQ == 1 set_htic_bit(0, val, 9); +#endif } #if CONFIG_HAVE_ACPI_RESUME

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New patch to review for coreboot: 527066c AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT
by Kyösti Mälkki 23 Dec '13

23 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4566 -gerrit commit 527066c9398048cc2a5d3d571d882f83de599a50 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 23 09:56:36 2013 +0200 AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/hp/dl145_g1/romstage.c | 3 --- src/mainboard/iwill/dk8_htx/romstage.c | 7 ------- src/mainboard/iwill/dk8s2/romstage.c | 7 ------- src/mainboard/iwill/dk8x/romstage.c | 7 ------- src/northbridge/amd/amdk8/raminit.c | 4 ---- 5 files changed, 28 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 0ae744f..7185749 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -119,9 +119,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_dl145g1_resource_map(); //setup_default_resource_map(); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 6944df0..12c7d6c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -100,9 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 940e8a6..29f9265 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -101,9 +97,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index bab7760..d50e954 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -101,9 +97,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 4aaa1bb..3ff8f57 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2493,10 +2493,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } -static void set_sysinfo_in_ram(unsigned val) -{ -} - void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) {

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Patch set updated for coreboot: 525349c AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
by Kyösti Mälkki 23 Dec '13

23 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4558 -gerrit commit 525349ca9e486247ee31b78e154bb539b8eac030 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 20:48:40 2013 +0200 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/model_fxx/init_cpus.c | 3 ++- src/cpu/amd/model_fxx/model_fxx_init.c | 2 ++ src/mainboard/asus/a8n_e/Kconfig | 4 ---- src/mainboard/msi/ms7135/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 8 ++++---- 5 files changed, 8 insertions(+), 13 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 7121642..6ba5025 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -293,11 +293,12 @@ static u32 init_cpus(u32 cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); +#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); #endif - +#endif STOP_CAR_AND_CPU(); } diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 4beecab..260e83e 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -31,11 +31,13 @@ #if CONFIG_WAIT_BEFORE_CPUS_INIT void cpus_ready_for_init(void) { +#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif +#endif } #endif diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index acb528b..ba2e5b1 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 14c0f49..76b6625 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -24,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7135" diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 294002e..ce2460e 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -37,10 +37,6 @@ config WAIT_BEFORE_CPUS_INIT bool default n -config MEM_TRAIN_SEQ - int - default 0 - # Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and # single DIMM is indeed unreliable without it). config K8_FORCE_2T_DRAM_TIMING @@ -99,6 +95,10 @@ if DIMM_DDR2 endif endif #DIMM_DDR2 +config MEM_TRAIN_SEQ + int + default 0 + endif #K8_REV_F_SUPPORT config IOMMU

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Patch set updated for coreboot: 666d998 cpu/allwinner/a10: Refactor and document pinmux API
by Alexandru Gagniuc 23 Dec '13

23 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4565 -gerrit commit 666d998edf841a458c04fd6ab2daeffdf04d4f36 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 21:30:21 2013 -0500 cpu/allwinner/a10: Refactor and document pinmux API Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 3 +- src/cpu/allwinner/a10/pinmux.c | 51 +++++++++++++++++++++++++- src/mainboard/cubietech/cubieboard/bootblock.c | 7 ++-- 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index f285451..709f74b 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -46,6 +46,7 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); -void gpio_set_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func); #endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index 083f7ec..ae73009 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -11,7 +11,14 @@ static struct a10_gpio *gpio = (void *)GPIO_BASE; -void gpio_set_func(u8 port, u8 pin, u8 pad_func) +/** + * \brief Set the pad function of a single pin + * + * @param [in] port GPIO port of the pin (GPA -> GPS) + * @param [in] pin the pin number in the given port (1 -> 31) + * @param [in] pad_func The peripheral function to which to connect this pin + */ +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) { u8 reg, bit; u32 reg32; @@ -28,3 +35,45 @@ void gpio_set_func(u8 port, u8 pin, u8 pad_func) reg32 |= (pad_func & 0xf) << bit; write32(reg32, &gpio->port[port].cfg[reg]); } + +/** + * \brief Set the pad function of a group of pins + * + * Multiplex a group of pins to the same pad function. This is useful for + * peripherals that use the same function number for several pins. This function + * allows those pins to be set with a single call. + * + * Example: + * gpio_set_multipin_func(GPB, (1 << 23) | (1 << 22), 2); + * + * @param [in] port GPIO port of the pin (GPA -> GPS) + * @param [in] pin_mask 32-bit mask indicating which pins to re-multiplex. For + * each set bit, the corresponding pin will be multiplexed. + * @param [in] pad_func The peripheral function to which to connect the pins + */ +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) +{ + int j; + u8 reg, bit; + u32 reg32, mask_offset; + + if ((port > GPS)) + return; + + for (reg = 0; reg < 4; reg++) { + mask_offset = 8 * reg; + /* Don't run the inner loop if we're not touching any pins */ + if (!(pin_mask & (0xff << mask_offset))) + continue; + + reg32 = read32(&gpio->port[port].cfg[reg]); + for (j = 0; j < 8; j++) { + if (!(pin_mask & (1 << (j + mask_offset)))) + continue; + bit = j * 4; + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + } + write32(reg32, &gpio->port[port].cfg[reg]); + } +} diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 6e8b751..a91391c 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -18,8 +18,8 @@ | AHB_DIV_1 \ | AXI_DIV_1 -#define GPB22_UART0_TX_FUNC 2 -#define GPB23_UART0_RX_FUNC 2 +#define GPB_UART0_FUNC 2 +#define GPB_UART0_PINS ((1 << 22) | (1 << 23)) static void cubieboard_set_sys_clock(void) { @@ -57,8 +57,7 @@ static void cubieboard_setup_clocks(void) static void cubieboard_setup_gpios(void) { /* Mux UART pins */ - gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); - gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); + gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); } static void cubieboard_enable_uart(void)

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New patch to review for coreboot: 6d6baf1 cpu/allwinner/a10: Refactor and document pinmux API
by Alexandru Gagniuc 23 Dec '13

23 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4565 -gerrit commit 6d6baf1f1ca9e741d72050eb305f2b6bbff731a6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 21:30:21 2013 -0500 cpu/allwinner/a10: Refactor and document pinmux API Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 3 ++- src/cpu/allwinner/a10/pinmux.c | 51 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index f285451..709f74b 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -46,6 +46,7 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); -void gpio_set_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func); #endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index 083f7ec..ae73009 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -11,7 +11,14 @@ static struct a10_gpio *gpio = (void *)GPIO_BASE; -void gpio_set_func(u8 port, u8 pin, u8 pad_func) +/** + * \brief Set the pad function of a single pin + * + * @param [in] port GPIO port of the pin (GPA -> GPS) + * @param [in] pin the pin number in the given port (1 -> 31) + * @param [in] pad_func The peripheral function to which to connect this pin + */ +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) { u8 reg, bit; u32 reg32; @@ -28,3 +35,45 @@ void gpio_set_func(u8 port, u8 pin, u8 pad_func) reg32 |= (pad_func & 0xf) << bit; write32(reg32, &gpio->port[port].cfg[reg]); } + +/** + * \brief Set the pad function of a group of pins + * + * Multiplex a group of pins to the same pad function. This is useful for + * peripherals that use the same function number for several pins. This function + * allows those pins to be set with a single call. + * + * Example: + * gpio_set_multipin_func(GPB, (1 << 23) | (1 << 22), 2); + * + * @param [in] port GPIO port of the pin (GPA -> GPS) + * @param [in] pin_mask 32-bit mask indicating which pins to re-multiplex. For + * each set bit, the corresponding pin will be multiplexed. + * @param [in] pad_func The peripheral function to which to connect the pins + */ +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) +{ + int j; + u8 reg, bit; + u32 reg32, mask_offset; + + if ((port > GPS)) + return; + + for (reg = 0; reg < 4; reg++) { + mask_offset = 8 * reg; + /* Don't run the inner loop if we're not touching any pins */ + if (!(pin_mask & (0xff << mask_offset))) + continue; + + reg32 = read32(&gpio->port[port].cfg[reg]); + for (j = 0; j < 8; j++) { + if (!(pin_mask & (1 << (j + mask_offset)))) + continue; + bit = j * 4; + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + } + write32(reg32, &gpio->port[port].cfg[reg]); + } +}

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Patch set updated for coreboot: fbd198b cpu/allwinner/a10: Clear the usage of SRAM during the bootblock
by Alexandru Gagniuc 23 Dec '13

23 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4563 -gerrit commit fbd198b619cab4d08a18b7000e823e5e10882533 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 18:51:29 2013 -0500 cpu/allwinner/a10: Clear the usage of SRAM during the bootblock We have 32KiB of usable SRAM right when we boot. The first 24KiB can be loaded with our bootblock, while the other 8KiB can be used as stack during the bootblock stage. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb --- src/cpu/allwinner/a10/Kconfig | 10 +++++++--- src/cpu/allwinner/a10/Makefile.inc | 15 ++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 646fe80..f40fa26 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -30,18 +30,22 @@ config ROMSTAGE_BASE hex default SYS_SDRAM_BASE -# Keep the stack in SRAM +# Keep the stack in SRAM block A2. +# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the +# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up +# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32 KiB +# to use however we see fit. config STACK_TOP hex default 0x00008000 config STACK_BOTTOM hex - default 0x00004000 + default 0x00006000 config STACK_SIZE hex - default 0x00004000 + default 0x00002000 ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 48f3110..9f7208a 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -21,15 +21,16 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) -# The boot ROM in the SoC will start loading code if a special boot0 header is +# The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. this header is normally added by the 'mxsunxiboot' tool. The file -# passed to mksunxiboot should only include the bootblock due to size -# limitations. -# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy -# the first 15 KiB of coreboot.rom (This will not collide with stack) +# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM +# will load at most 24KiB of data to SRAM, so limit the file size accordingly. +# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. +# FIXME: Figure out how to safely integrate in coreboot.rom. +# FIXME: The file passed to mksunxiboot should only include the bootblock due +# to size limitations. $(obj)/BOOT0: $(obj)/coreboot.rom @printf " BOOT0 $(subst $(obj)/,,$(^))\n" touch $@ - dd if=$^ of=$^.tmp bs=1024 count=15 + dd if=$^ of=$^.tmp bs=24544 count=1 -mksunxiboot $^.tmp $@

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Patch set updated for coreboot: c379c8a cpu: Add initial support for Allwinner A10 SoC
by Alexandru Gagniuc 23 Dec '13

23 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4549 -gerrit commit c379c8ac1e06968e9fe9727164850c2c0164722a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:44:48 2013 -0600 cpu: Add initial support for Allwinner A10 SoC Add minimal support needed to get a bootblock capable of initialising a serial console. Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/allwinner/Kconfig | 10 +++ src/cpu/allwinner/Makefile.inc | 1 + src/cpu/allwinner/a10/Kconfig | 108 +++++++++++++++++++++++++ src/cpu/allwinner/a10/Makefile.inc | 35 ++++++++ src/cpu/allwinner/a10/bootblock.c | 21 +++++ src/cpu/allwinner/a10/bootblock_media.c | 14 ++++ src/cpu/allwinner/a10/clock.h | 137 ++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/gpio.h | 51 ++++++++++++ src/cpu/allwinner/a10/memmap.h | 117 +++++++++++++++++++++++++++ src/cpu/allwinner/a10/monotonic_timer.c | 13 +++ src/cpu/allwinner/a10/pinmux.c | 30 +++++++ src/cpu/allwinner/a10/timer.c | 19 +++++ src/cpu/allwinner/a10/uart.c | 92 +++++++++++++++++++++ src/cpu/allwinner/a10/uart.h | 102 ++++++++++++++++++++++++ src/cpu/allwinner/a10/uart_console.c | 109 +++++++++++++++++++++++++ 17 files changed, 861 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index cd6c7a0..f3883d3 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,6 +3,7 @@ # (See also src/Kconfig) if ARCH_ARMV7 +source src/cpu/allwinner/Kconfig source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig source src/cpu/ti/Kconfig diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 7cd9d5f..f206fdc 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,6 +1,7 @@ ################################################################################ ## Subdirectories ################################################################################ +subdirs-y += allwinner subdirs-y += amd subdirs-y += dmp subdirs-y += armltd diff --git a/src/cpu/allwinner/Kconfig b/src/cpu/allwinner/Kconfig new file mode 100644 index 0000000..d73d0af --- /dev/null +++ b/src/cpu/allwinner/Kconfig @@ -0,0 +1,10 @@ +config CPU_ALLWINNER_A10 + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + bool + default n + +source src/cpu/allwinner/a10/Kconfig diff --git a/src/cpu/allwinner/Makefile.inc b/src/cpu/allwinner/Makefile.inc new file mode 100644 index 0000000..e52a12e --- /dev/null +++ b/src/cpu/allwinner/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_ALLWINNER_A10) += a10 diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig new file mode 100644 index 0000000..646fe80 --- /dev/null +++ b/src/cpu/allwinner/a10/Kconfig @@ -0,0 +1,108 @@ +if CPU_ALLWINNER_A10 + +config BOOTBLOCK_CPU_INIT + string + default "cpu/allwinner/a10/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# The "eGON.BT0" header takes 32 bytes +config BOOTBLOCK_BASE + hex + default 0x20 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x00 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x10 + +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + default 0x4c00 + +# FIXME: untested +config ROMSTAGE_BASE + hex + default SYS_SDRAM_BASE + +# Keep the stack in SRAM +config STACK_TOP + hex + default 0x00008000 + +config STACK_BOTTOM + hex + default 0x00004000 + +config STACK_SIZE + hex + default 0x00004000 + +## TODO Change this to some better address not overlapping bootblock when +## cbfstool supports creating header in arbitrary location. +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x40 + +config SYS_SDRAM_BASE + hex + default 0x40000000 + +# FIXME: this can probably be smaller +config COREBOOT_TABLES_SIZE + hex + default 0x800 + +choice CONSOLE_SERIAL_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART0 + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +config CONSOLE_SERIAL_UART4 + bool "UART4" + help + Serial console on UART4 + +config CONSOLE_SERIAL_UART5 + bool "UART5" + help + Serial console on UART5 + +config CONSOLE_SERIAL_UART6 + bool "UART6" + help + Serial console on UART6 + +config CONSOLE_SERIAL_UART7 + bool "UART7" + help + Serial console on UART7 + +endchoice + +endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc new file mode 100644 index 0000000..48f3110 --- /dev/null +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -0,0 +1,35 @@ +bootblock-y += pinmux.c +bootblock-y += bootblock_media.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c + +romstage-y += uart.c +romstage-y += uart_console.c +romstage-y += bootblock_media.c + +ramstage-y += uart.c +ramstage-y += uart_console.c +ramstage-y += timer.c +ramstage-y += monotonic_timer.c +ramstage-y += bootblock_media.c + + +real-target: $(obj)/BOOT0 + +get_bootblock_size= \ + $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ + sed 's/[^0-9 ]//g')) \ + $(shell echo $$(($(word 2, $(strip $(bb_s)))))) + +# The boot ROM in the SoC will start loading code if a special boot0 header is +# found (at an offset of 8KiB in either NAND or SD), and the checksum is +# correct. this header is normally added by the 'mxsunxiboot' tool. The file +# passed to mksunxiboot should only include the bootblock due to size +# limitations. +# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy +# the first 15 KiB of coreboot.rom (This will not collide with stack) +$(obj)/BOOT0: $(obj)/coreboot.rom + @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + touch $@ + dd if=$^ of=$^.tmp bs=1024 count=15 + -mksunxiboot $^.tmp $@ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c new file mode 100644 index 0000000..38fe953 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock.c @@ -0,0 +1,21 @@ +/* + * Allwinner A10 bootblock initialization + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> +#include <arch/cache.h> + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + uint32_t sctlr; + + /* enable dcache */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C; + write_sctlr(sctlr); +} diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c new file mode 100644 index 0000000..a5863b6 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock_media.c @@ -0,0 +1,14 @@ +/* + * CBFS accessors for bootblock stage. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ +#include <cbfs.h> +#include <console/console.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet."); + return 0; +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h new file mode 100644 index 0000000..e028d13 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.h @@ -0,0 +1,137 @@ +/* + * Definitions for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_CLOCK_H +#define CPU_ALLWINNER_A10_CLOCK_H + +#include "memmap.h" +#include <types.h> + +/* CPU_AHB_APB0 config values */ +#define CPU_CLK_SRC_MASK (3 << 16) +#define CPU_CLK_SRC_OSC24M (1 << 16) +#define CPU_CLK_SRC_PLL1 (2 << 16) +#define APB0_DIV_MASK (3 << 8) +#define APB0_DIV_1 (0 << 8) +#define APB0_DIV_2 (1 << 8) +#define APB0_DIV_4 (2 << 8) +#define APB0_DIV_8 (3 << 8) +#define AHB_DIV_MASK (3 << 4) +#define AHB_DIV_1 (0 << 4) +#define AHB_DIV_2 (1 << 4) +#define AHB_DIV_4 (2 << 4) +#define AHB_DIV_8 (3 << 4) +#define AXI_DIV_MASK (3 << 0) +#define AXI_DIV_1 (0 << 0) +#define AXI_DIV_2 (1 << 0) +#define AXI_DIV_3 (2 << 0) +#define AXI_DIV_4 (3 << 0) + +/* APB1_CLK_DIV values */ +#define APB1_CLK_SRC_MASK (3 << 24) +#define APB1_CLK_SRC_OSC24M (0 << 24) +#define APB1_CLK_SRC_PLL6 (1 << 24) +#define APB1_CLK_SRC_32K (2 << 24) +#define APB1_RAT_N_MASK (3 << 16) +#define APB1_RAT_N(m) (((m) & 0x3) << 16) +#define APB1_RAT_M_MASK 0x1f << 0) +#define APB1_RAT_M(n) (((n) & 0x1f) << 0) + +/* APB0_GATING values */ +#define APB0_GATE_KEYPAD (1 << 10) +#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) +#define APB0_GATE_PIO (1 << 5) +#define APB0_GATE_IIS (1 << 3) +#define APB0_GATE_AC97 (1 << 2) +#define APB0_GATE_CODEC (1 << 0) + +/* APB1_GATING values */ +#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) +#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) +#define APB1_GATE_CAN (1 << 4) +#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) + +struct a10_ccm { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ +} __attribute__ ((packed)); + +#endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h new file mode 100644 index 0000000..f285451 --- /dev/null +++ b/src/cpu/allwinner/a10/gpio.h @@ -0,0 +1,51 @@ +/* + * Definitions for GPIO and pin multiplexing on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CPU_ALLWINNER_A10_PINMUX_H +#define __CPU_ALLWINNER_A10_PINMUX_H + +#include <types.h> + +#define GPIO_BASE 0x01C20800 + +#define GPA 0 +#define GPB 1 +#define GPC 2 +#define GPD 3 +#define GPE 4 +#define GPF 5 +#define GPG 6 +#define GPH 7 +#define GPI 8 +#define GPS 9 + +struct a10_gpio_port { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pul[2]; +} __attribute__ ((packed)); + +struct a10_gpio { + struct a10_gpio_port port[10]; + u8 reserved_0x168[0x98]; + + /* Offset 0x200 */ + u32 int_cfg[4]; + + u32 int_ctl; + u32 int_sta; + u8 reserved_0x21C[4]; + u32 int_deb; + + u32 sdr_pad_drv; + u32 sdr_pad_pul; +} __attribute__ ((packed)); + +void gpio_set_func(u8 port, u8 pin, u8 pad_func); + +#endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h new file mode 100644 index 0000000..78d81dc --- /dev/null +++ b/src/cpu/allwinner/a10/memmap.h @@ -0,0 +1,117 @@ +/* + * Memory map definitions for Allwinner A10 CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_MEMMAP_H +#define CPU_ALLWINNER_A10_MEMMAP_H + +#define A1X_SRAM_A1_BASE 0x00000000 +#define A1X_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define A1X_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define A1X_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define A1X_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define A1X_SRAM_D_BASE 0x01c00000 +#define A1X_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */ + +#define A1X_SRAMC_BASE 0x01c00000 +#define A1X_DRAMC_BASE 0x01c01000 +#define A1X_DMA_BASE 0x01c02000 +#define A1X_NFC_BASE 0x01c03000 +#define A1X_TS_BASE 0x01c04000 +#define A1X_SPI0_BASE 0x01c05000 +#define A1X_SPI1_BASE 0x01c06000 +#define A1X_MS_BASE 0x01c07000 +#define A1X_TVD_BASE 0x01c08000 +#define A1X_CSI0_BASE 0x01c09000 +#define A1X_TVE0_BASE 0x01c0a000 +#define A1X_EMAC_BASE 0x01c0b000 +#define A1X_LCD0_BASE 0x01c0C000 +#define A1X_LCD1_BASE 0x01c0d000 +#define A1X_VE_BASE 0x01c0e000 +#define A1X_MMC0_BASE 0x01c0f000 +#define A1X_MMC1_BASE 0x01c10000 +#define A1X_MMC2_BASE 0x01c11000 +#define A1X_MMC3_BASE 0x01c12000 +#define A1X_USB0_BASE 0x01c13000 +#define A1X_USB1_BASE 0x01c14000 +#define A1X_SS_BASE 0x01c15000 +#define A1X_HDMI_BASE 0x01c16000 +#define A1X_SPI2_BASE 0x01c17000 +#define A1X_SATA_BASE 0x01c18000 +#define A1X_PATA_BASE 0x01c19000 +#define A1X_ACE_BASE 0x01c1a000 +#define A1X_TVE1_BASE 0x01c1b000 +#define A1X_USB2_BASE 0x01c1c000 +#define A1X_CSI1_BASE 0x01c1d000 +#define A1X_TZASC_BASE 0x01c1e000 +#define A1X_SPI3_BASE 0x01c1f000 + +#define A1X_CCM_BASE 0x01c20000 +#define A1X_INTC_BASE 0x01c20400 +#define A1X_PIO_BASE 0x01c20800 +#define A1X_TIMER_BASE 0x01c20c00 +#define A1X_SPDIF_BASE 0x01c21000 +#define A1X_AC97_BASE 0x01c21400 +#define A1X_IR0_BASE 0x01c21800 +#define A1X_IR1_BASE 0x01c21c00 + +#define A1X_IIS_BASE 0x01c22400 +#define A1X_LRADC_BASE 0x01c22800 +#define A1X_AD_DA_BASE 0x01c22c00 +#define A1X_KEYPAD_BASE 0x01c23000 +#define A1X_TZPC_BASE 0x01c23400 +#define A1X_SID_BASE 0x01c23800 +#define A1X_SJTAG_BASE 0x01c23c00 + +#define A1X_TP_BASE 0x01c25000 +#define A1X_PMU_BASE 0x01c25400 +#define A1X_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */ + +#define A1X_UART0_BASE 0x01c28000 +#define A1X_UART1_BASE 0x01c28400 +#define A1X_UART2_BASE 0x01c28800 +#define A1X_UART3_BASE 0x01c28c00 +#define A1X_UART4_BASE 0x01c29000 +#define A1X_UART5_BASE 0x01c29400 +#define A1X_UART6_BASE 0x01c29800 +#define A1X_UART7_BASE 0x01c29c00 +#define A1X_PS2_0_BASE 0x01c2a000 +#define A1X_PS2_1_BASE 0x01c2a400 + +#define A1X_TWI0_BASE 0x01c2ac00 +#define A1X_TWI1_BASE 0x01c2b000 +#define A1X_TWI2_BASE 0x01c2b400 + +#define A1X_CAN_BASE 0x01c2bc00 + +#define A1X_SCR_BASE 0x01c2c400 + +#define A1X_GPS_BASE 0x01c30000 +#define A1X_MALI400_BASE 0x01c40000 + +/* module sram */ +#define A1X_SRAM_C_BASE 0x01d00000 + +#define A1X_DE_FE0_BASE 0x01e00000 +#define A1X_DE_FE1_BASE 0x01e20000 +#define A1X_DE_BE0_BASE 0x01e60000 +#define A1X_DE_BE1_BASE 0x01e40000 +#define A1X_MP_BASE 0x01e80000 +#define A1X_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define A1X_CSDM_BASE 0x3f500000 + +#define A1X_DRAM_BASE 0x40000000 /* 2 GiB */ + +#define A1X_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define A1X_CPU_CFG (A1X_TIMER_BASE + 0x13c) + +#endif /* CPU_ALLWINNER_A10_MEMMAP_H */ diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c new file mode 100644 index 0000000..16d478a --- /dev/null +++ b/src/cpu/allwinner/a10/monotonic_timer.c @@ -0,0 +1,13 @@ +/* + * Placeholder for code to come (needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + (void)mt; +} diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c new file mode 100644 index 0000000..083f7ec --- /dev/null +++ b/src/cpu/allwinner/a10/pinmux.c @@ -0,0 +1,30 @@ +/* + * Helpers to multiplex and configure pins on Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "gpio.h" + +#include <arch/io.h> + +static struct a10_gpio *gpio = (void *)GPIO_BASE; + +void gpio_set_func(u8 port, u8 pin, u8 pad_func) +{ + u8 reg, bit; + u32 reg32; + + if ((port > GPS)) + return; + + pin &= 0x1f; + reg = pin / 8; + bit = (pin % 8) * 4; + + reg32 = read32(&gpio->port[port].cfg[reg]); + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + write32(reg32, &gpio->port[port].cfg[reg]); +} diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c new file mode 100644 index 0000000..e156398 --- /dev/null +++ b/src/cpu/allwinner/a10/timer.c @@ -0,0 +1,19 @@ +/* + * Placeholder for code to come(needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <delay.h> +#include <timer.h> + +void init_timer(void) +{ + /* Stub */ +} + +void udelay(unsigned usec) +{ + /* Stub */ +} diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c new file mode 100644 index 0000000..923c7c1 --- /dev/null +++ b/src/cpu/allwinner/a10/uart.c @@ -0,0 +1,92 @@ +/* + * Uart setup helpers for Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "uart.h" +#include <arch/io.h> + +/** + * \brief Configure line control settings for UART + */ +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits) +{ + u32 reg32; + u16 div; + struct a10_uart *uart = uart_base; + + /* Enable access to Divisor Latch register */ + write32(UART_LCR_DLAB, &uart->lcr); + /* Set baudrate */ + /* FIXME: We assume clock is 24MHz, which may not be the case */ + div = 24000000 / 16 / baud_rate; + write32((div >> 8) & 0xff, &uart->dlh); + write32(div & 0xff, &uart->dll); + /* Set line control */ + reg32 = UART_LCR_DATALEN(data_bits); + switch (parity) { + case UART_PARITY_ODD: + reg32 |= UART_LCR_PEN; + break; + case UART_PARITY_EVEN: + reg32 |= UART_LCR_PEN; + reg32 |= UART_LCR_EPS; + break; + case UART_PARITY_NONE: /* Fall through */ + default: + break; + } + write32(reg32, &uart->lcr); +} + +void a10_uart_enable_fifos(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + write32(UART_FCR_FIFOE, &uart->fcr); +} + +static int tx_fifo_full(struct a10_uart *uart) +{ + /* This may be a misnomer, or a typo in the datasheet. THRE indicates + * that the TX register is empty, not that the FIFO is not full, but + * this may be due to a datasheet typo. Keep the current name to signal + * intent. */ + return !(read32(&uart->lsr) & UART_LSR_THRE); +} + +static int rx_fifo_empty(struct a10_uart *uart) +{ + return !(read32(&uart->lsr) & UART_LSR_DR); +} + +/** + * \brief Read a single byte from the UART. + * + * Blocks until at least a byte is available. + */ +u8 a10_uart_rx_blocking(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + while (rx_fifo_empty(uart)) ; + + return read32(&uart->rbr); +} + +/** + * \brief Write a single byte to the UART. + * + * Blocks until there is space in the FIFO. + */ +void a10_uart_tx_blocking(void *uart_base, u8 data) +{ + struct a10_uart *uart = uart_base; + + while (tx_fifo_full(uart)) ; + + return write32(data, &uart->thr); +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h new file mode 100644 index 0000000..c324dc1d --- /dev/null +++ b/src/cpu/allwinner/a10/uart.h @@ -0,0 +1,102 @@ +/* + * Definitions for UART on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_UART_H +#define CPU_ALLWINNER_A10_UART_H + +#include "memmap.h" +#include <types.h> + +/* UART_FCR definitions */ +#define UART_FCR_DMAM (1 << 3) +#define UART_FCR_XFIFOR (1 << 2) +#define UART_FCR_RFIFOR (1 << 1) +#define UART_FCR_FIFOE (1 << 0) + +/* UART_LCR definitions */ +#define UART_LCR_DLAB (1 << 7) +#define UART_LCR_BC (1 << 6) +#define UART_LCR_EPS (1 << 4) +#define UART_LCR_PEN (1 << 3) +#define UART_LCR_STOP_MASK (0x3 << 2) +#define UART_LCR_STOP_1BIT (0 << 2) +#define UART_LCR_STOP_2BIT (1 << 2) +#define UART_LCR_DLS_MASK (3 << 0) +#define UART_LCR_DATALEN(bits) ((bits - 5) & UART_LCR_DLS_MASK) + +/* UART_LSR definitions */ +#define UART_LSR_FIFOERR (1 << 7) +#define UART_LSR_TEMT (1 << 6) +#define UART_LSR_THRE (1 << 5) +#define UART_LSR_BI (1 << 4) +#define UART_LSR_FE (1 << 3) +#define UART_LSR_PE (1 << 2) +#define UART_LSR_OE (1 << 1) +#define UART_LSR_DR (1 << 0) + +#define BAUD_115200 (0xd) + +struct a10_uart { + union { + /* operational mode */ + u32 rbr; /* receiver buffer (read) */ + u32 thr; /* transmit holding (write) */ + /* config mode A and B */ + u32 dll; /* divisor latches low */ + }; + + union { + /* operational mode */ + u32 ier; /* interrupt enable */ + /* config mode A and B */ + u32 dlh; /* divisor latches high */ + }; + + union { + /* operational mode, config mode A */ + u32 iir; /* interrupt ID (read) */ + u32 fcr; /* FIFO control (write) */ + }; + + u32 lcr; /* line control */ + + /* 0x10 */ + u32 mcr; /* modem control */ + u32 lsr; /* line status, read-only */ + u32 msr; /* modem status */ + u32 sch; /* trigger level */ + + u8 reserved_0x20[0x50]; + + /* 0x70 */ + u8 reserved_0x70[0xc]; + u32 usr; /* frequency select */ + + /* 0x80 */ + u32 tfl; /* mode definition register 3 */ + u32 rfl; + u8 reserved_0x88[0x18]; + + /* 0xa0 */ + u8 reserved_0xa0[4]; + u32 halt; /* TX DMA threshold */ + +} __attribute__ ((packed)); + +enum uart_parity { + UART_PARITY_NONE, + UART_PARITY_EVEN, + UART_PARITY_ODD, +}; + +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits); +void a10_uart_enable_fifos(void *uart_base); +u8 a10_uart_rx_blocking(void *uart_base); +void a10_uart_tx_blocking(void *uart_base, u8 data); + +#endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c new file mode 100644 index 0000000..58930dd --- /dev/null +++ b/src/cpu/allwinner/a10/uart_console.c @@ -0,0 +1,109 @@ +/* + * Glue to UART code to enable serial console + * + * Copyright 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> +#include <types.h> +#include <uart.h> +#include <arch/io.h> + +#include <console/console.h> +#include <cpu/allwinner/a10/uart.h> + +static void *get_console_uart_base_addr(void) +{ + /* This big block gets compiled to a constant, not a function call */ + if (CONFIG_CONSOLE_SERIAL_UART0) + return (void *)A1X_UART0_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART1) + return (void *)A1X_UART1_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART2) + return (void *)A1X_UART2_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART3) + return (void *)A1X_UART3_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART4) + return (void *)A1X_UART4_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART5) + return (void *)A1X_UART5_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART6) + return (void *)A1X_UART6_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART7) + return (void *)A1X_UART7_BASE; + + /* If selection is invalid, default to UART0 */ + return (void *)A1X_UART0_BASE; +} + +static u32 get_console_uart_baud(void) +{ + if (CONFIG_CONSOLE_SERIAL_115200) + return 115200; + else if (CONFIG_CONSOLE_SERIAL_57600) + return 57600; + else if (CONFIG_CONSOLE_SERIAL_38400) + return 34800; + else if (CONFIG_CONSOLE_SERIAL_19200) + return 19200; + else if (CONFIG_CONSOLE_SERIAL_9600) + return 9600; + + /* Default to 115200 if selection is invalid */ + return 115200; +} + +static void a10_uart_init_dev(void) +{ + void *uart_base = get_console_uart_base_addr(); + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, get_console_uart_baud(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +static unsigned char a10_uart_rx_byte(void) +{ + return a10_uart_rx_blocking(get_console_uart_base_addr()); +} + +static void a10_uart_tx_byte(unsigned char data) +{ + a10_uart_tx_blocking(get_console_uart_base_addr(), data); +} + +uint32_t uartmem_getbaseaddr(void) +{ + return (uint32_t) get_console_uart_base_addr(); +} + +#if !defined(__PRE_RAM__) +static const struct console_driver a10_uart_console __console = { + .init = a10_uart_init_dev, + .tx_byte = a10_uart_tx_byte, + .rx_byte = a10_uart_rx_byte, +}; +#else + +void uart_init(void) +{ + a10_uart_init_dev(); +} + +unsigned char uart_rx_byte(void) +{ + return a10_uart_rx_byte(); +} + +void uart_tx_byte(unsigned char data) +{ + a10_uart_tx_byte(data); +} + +void uart_tx_flush(void) +{ +} + +#endif

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coreboot-gerrit December 2013