coreboot-gerrit December 2013

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Patch set updated for coreboot: eaeac47 mainboard: Add preliminary support for A10-based Cubieboard
by Alexandru Gagniuc 23 Dec '13

23 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4553 -gerrit commit eaeac4772f943b5773bcc5ac63cf021272498e81 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:25:04 2013 -0600 mainboard: Add preliminary support for A10-based Cubieboard Add a minimal infrastructure which initializes the system clocks and serial console. Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/cubietech/Kconfig | 18 ++++++ src/mainboard/cubietech/cubieboard/Kconfig | 34 ++++++++++ src/mainboard/cubietech/cubieboard/Makefile.inc | 1 + src/mainboard/cubietech/cubieboard/bootblock.c | 80 ++++++++++++++++++++++++ src/mainboard/cubietech/cubieboard/devicetree.cb | 3 + src/mainboard/cubietech/cubieboard/romstage.c | 14 +++++ 7 files changed, 153 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fdb0eac..6ba057a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -48,6 +48,8 @@ config VENDOR_BROADCOM bool "Broadcom" config VENDOR_COMPAQ bool "Compaq" +config VENDOR_CUBIETECH + bool "Cubietech" config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_DMP @@ -161,6 +163,7 @@ source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" +source "src/mainboard/cubietech/Kconfig" source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/dmp/Kconfig" source "src/mainboard/eaglelion/Kconfig" diff --git a/src/mainboard/cubietech/Kconfig b/src/mainboard/cubietech/Kconfig new file mode 100644 index 0000000..840ee85 --- /dev/null +++ b/src/mainboard/cubietech/Kconfig @@ -0,0 +1,18 @@ +if VENDOR_CUBIETECH + +# Auto select common options +choice + prompt "Mainboard model" + +config BOARD_CUBIETECH_CUBIEBOARD + bool "Cubieboard" + +endchoice + +source "src/mainboard/cubietech/cubieboard/Kconfig" + +config MAINBOARD_VENDOR + string + default "Cubietech" + +endif # VENDOR_CUBIETECH diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig new file mode 100644 index 0000000..3e08ce0 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -0,0 +1,34 @@ +if BOARD_CUBIETECH_CUBIEBOARD + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_ALLWINNER_A10 + select HAVE_UART_MEMORY_MAPPED + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default cubietech/cubieboard + +config MAINBOARD_PART_NUMBER + string + default "Cubieboard A10" + +config MAX_CPUS + int + default 1 + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/cubietech/cubieboard/bootblock.c" + +config DRAM_SIZE_MB + int + default 1024 + +config NR_DRAM_BANKS + int + default 1 + +endif # BOARD_CUBIETECH_CUBIEBOARD diff --git a/src/mainboard/cubietech/cubieboard/Makefile.inc b/src/mainboard/cubietech/cubieboard/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c new file mode 100644 index 0000000..6e8b751 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -0,0 +1,80 @@ +/* + * Minimal bootblock for Cubieboard + * It sets up CPU clock, and enables the bootblock console. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <arch/io.h> +#include <uart.h> +#include <console/console.h> +#include <cpu/allwinner/a10/gpio.h> +#include <cpu/allwinner/a10/clock.h> + +#define CPU_AHB_APB0_DEFAULT \ + CPU_CLK_SRC_OSC24M \ + | APB0_DIV_1 \ + | AHB_DIV_1 \ + | AXI_DIV_1 + +#define GPB22_UART0_TX_FUNC 2 +#define GPB23_UART0_RX_FUNC 2 + +static void cubieboard_set_sys_clock(void) +{ + u32 reg32; + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + + /* Switch CPU clock to main oscillator */ + write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg); + + /* Configure the PLL1. The value is the same one used by u-boot */ + write32(0xa1005000, &ccm->pll1_cfg); + + /* FIXME: Delay to wait for PLL to lock */ + u32 wait = 1000; + while (--wait); + + /* Switch CPU to PLL clock */ + reg32 = read32(&ccm->cpu_ahb_apb0_cfg); + reg32 &= ~CPU_CLK_SRC_MASK; + reg32 |= CPU_CLK_SRC_PLL1; + write32(reg32, &ccm->cpu_ahb_apb0_cfg); +} + +static void cubieboard_setup_clocks(void) +{ + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + + cubieboard_set_sys_clock(); + /* Configure the clock source for APB1. This drives our UART */ + write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), + &ccm->apb1_clk_div_cfg); + +} + +static void cubieboard_setup_gpios(void) +{ + /* Mux UART pins */ + gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); + gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); +} + +static void cubieboard_enable_uart(void) +{ + u32 reg32; + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + /* Enable clock to UART0 */ + reg32 = read32(&ccm->apb1_gate); + reg32 |= APB1_GATE_UART(0); + write32(reg32, &ccm->apb1_gate); +} + +void bootblock_mainboard_init(void); +void bootblock_mainboard_init(void) +{ + cubieboard_setup_clocks(); + cubieboard_setup_gpios(); + cubieboard_enable_uart(); +} diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb new file mode 100644 index 0000000..1358777 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/devicetree.cb @@ -0,0 +1,3 @@ +chip cpu/allwinner/a10 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c new file mode 100644 index 0000000..19192cd --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -0,0 +1,14 @@ +/* + * Placeholder for Cubieboard romstage + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <console/console.h> + +void main(void) +{ + console_init(); + printk(BIOS_INFO, "You have managed to succesfully load romstage.\n"); +}

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Patch merged into coreboot/master: d84b24d Coding style: punctuation cleanup [1/2].
by gerrit＠coreboot.org 23 Dec '13

23 Dec '13

the following patch was just integrated into master: commit d84b24d3e2e092fdbd6569f6a01e186f5a3a2519 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 Coding style: punctuation cleanup [1/2]. Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/4562 for details. -gerrit

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Patch set updated for coreboot: d84b24d Coding style: punctuation cleanup [1/2].
by Idwer Vollering 23 Dec '13

23 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4562 -gerrit commit d84b24d3e2e092fdbd6569f6a01e186f5a3a2519 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 Coding style: punctuation cleanup [1/2]. Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/i2c/rtd2132/rtd2132.c | 2 +- src/ec/quanta/it8518/ec.c | 4 ++-- src/lib/cbfs.c | 2 +- src/lib/dynamic_cbmem.c | 2 +- src/mainboard/google/bolt/smihandler.c | 2 +- src/mainboard/google/falco/smihandler.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/peppy/smihandler.c | 2 +- src/mainboard/google/slippy/smihandler.c | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- src/northbridge/intel/i5000/raminit.c | 4 ++-- src/northbridge/via/vx800/detection.c | 2 +- src/northbridge/via/vx800/freq_setting.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 4 ++-- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/intel/i82371eb/fadt.c | 2 +- src/southbridge/nvidia/mcp55/fadt.c | 2 +- src/southbridge/via/vt8237r/fadt.c | 2 +- 21 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 22a9f03..44333ac 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -181,7 +181,7 @@ static void rtd2132_lvds_swap(device_t dev, if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL) swap_value |= RTD2132_LVDS_SWAP_DUAL; - printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value);; + printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value); rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 4798cee..6516cee 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -40,7 +40,7 @@ static int input_buffer_empty(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { @@ -56,7 +56,7 @@ static int output_buffer_full(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) & KBD_OBF) == 0); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23e1600..1f44695 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -312,7 +312,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated;; + void *address = buffer->buffer + buffer->allocated; DEBUG("simple_buffer_map(offset=%zd, count=%zd): " "allocated=%zd, size=%zd, last_allocate=%zd\n", offset, count, buffer->allocated, buffer->size, diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index e21f96e..b934aed 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -294,7 +294,7 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { struct cbmem_root *root; const struct cbmem_entry *entry; - unsigned long base;; + unsigned long base; u32 size; u32 aligned_size; diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c index 7b7dd69..b392852 100644 --- a/src/mainboard/google/bolt/smihandler.c +++ b/src/mainboard/google/bolt/smihandler.c @@ -149,7 +149,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c index bf2165f..511bfc5 100644 --- a/src/mainboard/google/falco/smihandler.c +++ b/src/mainboard/google/falco/smihandler.c @@ -166,7 +166,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 3785121..c545a86 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -153,7 +153,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 8a647dc..6f50a79 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -72,7 +72,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid switch GPIO active high (open). */ gpios->gpios[3].port = 15; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = ((gp_lvl >> 15) & 1);; + gpios->gpios[3].value = ((gp_lvl >> 15) & 1); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button */ diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c index f225468..e95dc4c 100644 --- a/src/mainboard/google/peppy/smihandler.c +++ b/src/mainboard/google/peppy/smihandler.c @@ -163,7 +163,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index dd0a605..f8eac31 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -150,7 +150,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index d6860b2..8c45332 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index) //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 7055c7a..4be7d5d 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1283,8 +1283,8 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) } printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); - printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; - printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1); + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2); pci_write_config16(dev16, I5000_MIR0, mir0); pci_write_config16(dev16, I5000_MIR1, mir1); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index eb1ddcc..69e520c 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -180,7 +180,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) DramAttr->DimmNumChB++; DramAttr->LoadNumChB = (u8) (DramAttr->LoadNumChB * LoadNum * - RankNum);; + RankNum); } RankNum |= 1; /* Set rank map. */ DramAttr->RankPresentMap |= (RankNum << (Sockets * 2)); diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 65b058a..55a6316 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -65,7 +65,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) Data = (u8) ((Data & 0xf8) | 6); break; default: - Data = (u8) ((Data & 0xf8) | 1);; + Data = (u8) ((Data & 0xf8) | 1); } pci_write_config8(MEMCTRL, 0x90, Data); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1c052c0..f148ffe 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -426,7 +426,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms, } else { /* Otherwise, everything is held in the first bank */ ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = 0;; + ranks->phys_rank_size_mb[(i << 1) | 1] = 0; } } } @@ -1294,7 +1294,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, { /* Same timeout reasoning as in receive delays */ size_t n_tries = 0; - int dq_tries = 0, dqs_tries = 0;; + int dq_tries = 0, dqs_tries = 0; const size_t max_tries = 100; for (;;) { if (n_tries++ >= max_tries) { diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index d85a515..3b2f556 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -117,7 +117,7 @@ static void ImcSleep(void) static void ImcWakeup(void) { u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ - u8 reg0_val = 0;; /* clear response register */ + u8 reg0_val = 0; /* clear response register */ u8 reg1_val = 0xB5; /* release ownership flag */ WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2c2f6d5..0fb6556 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -151,7 +151,7 @@ static void sm_init(device_t dev) pm_iowrite(0x55, byte); byte = pm_ioread(0xD7); - byte |= 1 << 6 | 1 << 1;; + byte |= 1 << 6 | 1 << 1; pm_iowrite(0xD7, byte); /* 2.15 */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..213cae9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -276,7 +276,7 @@ void sb800_pci_port80(void) pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index e4c8208..09874f7 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -212,7 +212,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index f9ac8ee..68f03e0 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c index 5b3bc56..ecd81b3 100644 --- a/src/southbridge/via/vt8237r/fadt.c +++ b/src/southbridge/via/vt8237r/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;

1 0

New patch to review for coreboot: 3219780 src/vendorcode/amd/: punctuation cleanup [2/2].
by Idwer Vollering 23 Dec '13

23 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4564 -gerrit commit 3219780c5b569982d390a8b8ef3d1f5c772b9eb2 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 src/vendorcode/amd/: punctuation cleanup [2/2]. Clean up superfluous line terminators. Change-Id: I3b0a77d971e9cd3cfd4413680841623051f4286c Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/southbridge/amd/sb800/early_setup.c | 2 +- .../agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- .../agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 2 +- src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..213cae9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -276,7 +276,7 @@ void sb800_pci_port80(void) pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 370a825..ab86118 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -533,7 +533,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index ae9fd5c..fa48682 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -531,7 +531,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c index 55adc8a..61bc58c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c @@ -837,7 +837,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c index 99a28b1..d0e66b9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c @@ -842,7 +842,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 3a8b32f..9a64e7e 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -159,7 +159,7 @@ AmdSbDispatcher ( } if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { - sbECfancontrolservice((AMDSBCFG*)pConfig);; + sbECfancontrolservice((AMDSBCFG*)pConfig); } #endif return Status;

1 0

Patch set updated for coreboot: 4b13029 Coding style: punctuation cleanup.
by Idwer Vollering 23 Dec '13

23 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4562 -gerrit commit 4b13029cdd9d219fb603b325cc033ea23a54d8b6 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 Coding style: punctuation cleanup. Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/i2c/rtd2132/rtd2132.c | 2 +- src/ec/quanta/it8518/ec.c | 4 ++-- src/lib/cbfs.c | 2 +- src/lib/dynamic_cbmem.c | 2 +- src/mainboard/google/bolt/smihandler.c | 2 +- src/mainboard/google/falco/smihandler.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/peppy/smihandler.c | 2 +- src/mainboard/google/slippy/smihandler.c | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- src/northbridge/intel/i5000/raminit.c | 4 ++-- src/northbridge/via/vx800/detection.c | 2 +- src/northbridge/via/vx800/freq_setting.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 4 ++-- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/intel/i82371eb/fadt.c | 2 +- src/southbridge/nvidia/mcp55/fadt.c | 2 +- src/southbridge/via/vt8237r/fadt.c | 2 +- .../f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- .../f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 2 +- src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 2 +- 26 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 22a9f03..44333ac 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -181,7 +181,7 @@ static void rtd2132_lvds_swap(device_t dev, if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL) swap_value |= RTD2132_LVDS_SWAP_DUAL; - printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value);; + printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value); rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 4798cee..6516cee 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -40,7 +40,7 @@ static int input_buffer_empty(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { @@ -56,7 +56,7 @@ static int output_buffer_full(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) & KBD_OBF) == 0); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23e1600..1f44695 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -312,7 +312,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated;; + void *address = buffer->buffer + buffer->allocated; DEBUG("simple_buffer_map(offset=%zd, count=%zd): " "allocated=%zd, size=%zd, last_allocate=%zd\n", offset, count, buffer->allocated, buffer->size, diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index e21f96e..b934aed 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -294,7 +294,7 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { struct cbmem_root *root; const struct cbmem_entry *entry; - unsigned long base;; + unsigned long base; u32 size; u32 aligned_size; diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c index 7b7dd69..b392852 100644 --- a/src/mainboard/google/bolt/smihandler.c +++ b/src/mainboard/google/bolt/smihandler.c @@ -149,7 +149,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c index bf2165f..511bfc5 100644 --- a/src/mainboard/google/falco/smihandler.c +++ b/src/mainboard/google/falco/smihandler.c @@ -166,7 +166,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 3785121..c545a86 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -153,7 +153,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 8a647dc..6f50a79 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -72,7 +72,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid switch GPIO active high (open). */ gpios->gpios[3].port = 15; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = ((gp_lvl >> 15) & 1);; + gpios->gpios[3].value = ((gp_lvl >> 15) & 1); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button */ diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c index f225468..e95dc4c 100644 --- a/src/mainboard/google/peppy/smihandler.c +++ b/src/mainboard/google/peppy/smihandler.c @@ -163,7 +163,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index dd0a605..f8eac31 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -150,7 +150,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index d6860b2..8c45332 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index) //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 7055c7a..4be7d5d 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1283,8 +1283,8 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) } printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); - printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; - printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1); + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2); pci_write_config16(dev16, I5000_MIR0, mir0); pci_write_config16(dev16, I5000_MIR1, mir1); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index eb1ddcc..69e520c 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -180,7 +180,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) DramAttr->DimmNumChB++; DramAttr->LoadNumChB = (u8) (DramAttr->LoadNumChB * LoadNum * - RankNum);; + RankNum); } RankNum |= 1; /* Set rank map. */ DramAttr->RankPresentMap |= (RankNum << (Sockets * 2)); diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 65b058a..55a6316 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -65,7 +65,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) Data = (u8) ((Data & 0xf8) | 6); break; default: - Data = (u8) ((Data & 0xf8) | 1);; + Data = (u8) ((Data & 0xf8) | 1); } pci_write_config8(MEMCTRL, 0x90, Data); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1c052c0..f148ffe 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -426,7 +426,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms, } else { /* Otherwise, everything is held in the first bank */ ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = 0;; + ranks->phys_rank_size_mb[(i << 1) | 1] = 0; } } } @@ -1294,7 +1294,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, { /* Same timeout reasoning as in receive delays */ size_t n_tries = 0; - int dq_tries = 0, dqs_tries = 0;; + int dq_tries = 0, dqs_tries = 0; const size_t max_tries = 100; for (;;) { if (n_tries++ >= max_tries) { diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index d85a515..3b2f556 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -117,7 +117,7 @@ static void ImcSleep(void) static void ImcWakeup(void) { u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ - u8 reg0_val = 0;; /* clear response register */ + u8 reg0_val = 0; /* clear response register */ u8 reg1_val = 0xB5; /* release ownership flag */ WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2c2f6d5..0fb6556 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -151,7 +151,7 @@ static void sm_init(device_t dev) pm_iowrite(0x55, byte); byte = pm_ioread(0xD7); - byte |= 1 << 6 | 1 << 1;; + byte |= 1 << 6 | 1 << 1; pm_iowrite(0xD7, byte); /* 2.15 */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..213cae9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -276,7 +276,7 @@ void sb800_pci_port80(void) pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index e4c8208..09874f7 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -212,7 +212,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index f9ac8ee..68f03e0 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c index 5b3bc56..ecd81b3 100644 --- a/src/southbridge/via/vt8237r/fadt.c +++ b/src/southbridge/via/vt8237r/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 370a825..ab86118 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -533,7 +533,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index ae9fd5c..fa48682 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -531,7 +531,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c index 55adc8a..61bc58c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c @@ -837,7 +837,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c index 99a28b1..d0e66b9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c @@ -842,7 +842,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 3a8b32f..9a64e7e 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -159,7 +159,7 @@ AmdSbDispatcher ( } if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { - sbECfancontrolservice((AMDSBCFG*)pConfig);; + sbECfancontrolservice((AMDSBCFG*)pConfig); } #endif return Status;

1 0

Patch set updated for coreboot: e2ecfd7 src/vendorcode/amd/: punctuation cleanup [2/2].
by Idwer Vollering 23 Dec '13

23 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4562 -gerrit commit e2ecfd7599f8a787415ca384b42bab9a81f77950 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 src/vendorcode/amd/: punctuation cleanup [2/2]. Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/southbridge/amd/sb800/early_setup.c | 2 +- .../agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- .../agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 2 +- src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..213cae9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -276,7 +276,7 @@ void sb800_pci_port80(void) pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 370a825..ab86118 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -533,7 +533,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index ae9fd5c..fa48682 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -531,7 +531,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c index 55adc8a..61bc58c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c @@ -837,7 +837,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c index 99a28b1..d0e66b9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c @@ -842,7 +842,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 3a8b32f..9a64e7e 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -159,7 +159,7 @@ AmdSbDispatcher ( } if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { - sbECfancontrolservice((AMDSBCFG*)pConfig);; + sbECfancontrolservice((AMDSBCFG*)pConfig); } #endif return Status;

1 0

New patch to review for coreboot: ab8be71 cpu/allwinner/a10: Clear the usage of SRAM during the bootblock
by Alexandru Gagniuc 23 Dec '13

23 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4563 -gerrit commit ab8be711a019cf2f329143551c7b87e35a1b2547 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 18:51:29 2013 -0500 cpu/allwinner/a10: Clear the usage of SRAM during the bootblock We have 32KiB of usable SRAM right when we boot. The first 24KiB can be loaded with our bootblock, while the other 8KiB can be used as stack during the bootblock stage. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb --- src/cpu/allwinner/a10/Kconfig | 10 +++++++--- src/cpu/allwinner/a10/Makefile.inc | 15 ++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 646fe80..f40fa26 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -30,18 +30,22 @@ config ROMSTAGE_BASE hex default SYS_SDRAM_BASE -# Keep the stack in SRAM +# Keep the stack in SRAM block A2. +# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the +# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up +# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32 KiB +# to use however we see fit. config STACK_TOP hex default 0x00008000 config STACK_BOTTOM hex - default 0x00004000 + default 0x00006000 config STACK_SIZE hex - default 0x00004000 + default 0x00002000 ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 48f3110..9f7208a 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -21,15 +21,16 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) -# The boot ROM in the SoC will start loading code if a special boot0 header is +# The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. this header is normally added by the 'mxsunxiboot' tool. The file -# passed to mksunxiboot should only include the bootblock due to size -# limitations. -# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy -# the first 15 KiB of coreboot.rom (This will not collide with stack) +# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM +# will load at most 24KiB of data to SRAM, so limit the file size accordingly. +# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. +# FIXME: Figure out how to safely integrate in coreboot.rom. +# FIXME: The file passed to mksunxiboot should only include the bootblock due +# to size limitations. $(obj)/BOOT0: $(obj)/coreboot.rom @printf " BOOT0 $(subst $(obj)/,,$(^))\n" touch $@ - dd if=$^ of=$^.tmp bs=1024 count=15 + dd if=$^ of=$^.tmp bs=24544 count=1 -mksunxiboot $^.tmp $@

1 0

Patch set updated for coreboot: a9a8a99 Coding style: punctuation cleanup [1/2].
by Idwer Vollering 23 Dec '13

23 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4562 -gerrit commit a9a8a99881a56408d6f61b2d124a11028e92f63d Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 Coding style: punctuation cleanup [1/2]. Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/i2c/rtd2132/rtd2132.c | 2 +- src/ec/quanta/it8518/ec.c | 4 ++-- src/lib/cbfs.c | 2 +- src/lib/dynamic_cbmem.c | 2 +- src/mainboard/google/bolt/smihandler.c | 2 +- src/mainboard/google/falco/smihandler.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/peppy/smihandler.c | 2 +- src/mainboard/google/slippy/smihandler.c | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- src/northbridge/intel/i5000/raminit.c | 4 ++-- src/northbridge/via/vx800/detection.c | 2 +- src/northbridge/via/vx800/freq_setting.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 4 ++-- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/intel/i82371eb/fadt.c | 2 +- src/southbridge/nvidia/mcp55/fadt.c | 2 +- src/southbridge/via/vt8237r/fadt.c | 2 +- 21 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 22a9f03..44333ac 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -181,7 +181,7 @@ static void rtd2132_lvds_swap(device_t dev, if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL) swap_value |= RTD2132_LVDS_SWAP_DUAL; - printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value);; + printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value); rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 4798cee..6516cee 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -40,7 +40,7 @@ static int input_buffer_empty(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { @@ -56,7 +56,7 @@ static int output_buffer_full(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) & KBD_OBF) == 0); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23e1600..1f44695 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -312,7 +312,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated;; + void *address = buffer->buffer + buffer->allocated; DEBUG("simple_buffer_map(offset=%zd, count=%zd): " "allocated=%zd, size=%zd, last_allocate=%zd\n", offset, count, buffer->allocated, buffer->size, diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index e21f96e..b934aed 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -294,7 +294,7 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { struct cbmem_root *root; const struct cbmem_entry *entry; - unsigned long base;; + unsigned long base; u32 size; u32 aligned_size; diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c index 7b7dd69..b392852 100644 --- a/src/mainboard/google/bolt/smihandler.c +++ b/src/mainboard/google/bolt/smihandler.c @@ -149,7 +149,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c index bf2165f..511bfc5 100644 --- a/src/mainboard/google/falco/smihandler.c +++ b/src/mainboard/google/falco/smihandler.c @@ -166,7 +166,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 3785121..c545a86 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -153,7 +153,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 8a647dc..6f50a79 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -72,7 +72,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid switch GPIO active high (open). */ gpios->gpios[3].port = 15; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = ((gp_lvl >> 15) & 1);; + gpios->gpios[3].value = ((gp_lvl >> 15) & 1); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button */ diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c index f225468..e95dc4c 100644 --- a/src/mainboard/google/peppy/smihandler.c +++ b/src/mainboard/google/peppy/smihandler.c @@ -163,7 +163,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index dd0a605..f8eac31 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -150,7 +150,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index d6860b2..8c45332 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index) //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 7055c7a..4be7d5d 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1283,8 +1283,8 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) } printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); - printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; - printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1); + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2); pci_write_config16(dev16, I5000_MIR0, mir0); pci_write_config16(dev16, I5000_MIR1, mir1); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index eb1ddcc..69e520c 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -180,7 +180,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) DramAttr->DimmNumChB++; DramAttr->LoadNumChB = (u8) (DramAttr->LoadNumChB * LoadNum * - RankNum);; + RankNum); } RankNum |= 1; /* Set rank map. */ DramAttr->RankPresentMap |= (RankNum << (Sockets * 2)); diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 65b058a..55a6316 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -65,7 +65,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) Data = (u8) ((Data & 0xf8) | 6); break; default: - Data = (u8) ((Data & 0xf8) | 1);; + Data = (u8) ((Data & 0xf8) | 1); } pci_write_config8(MEMCTRL, 0x90, Data); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1c052c0..f148ffe 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -426,7 +426,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms, } else { /* Otherwise, everything is held in the first bank */ ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = 0;; + ranks->phys_rank_size_mb[(i << 1) | 1] = 0; } } } @@ -1294,7 +1294,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, { /* Same timeout reasoning as in receive delays */ size_t n_tries = 0; - int dq_tries = 0, dqs_tries = 0;; + int dq_tries = 0, dqs_tries = 0; const size_t max_tries = 100; for (;;) { if (n_tries++ >= max_tries) { diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index d85a515..3b2f556 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -117,7 +117,7 @@ static void ImcSleep(void) static void ImcWakeup(void) { u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ - u8 reg0_val = 0;; /* clear response register */ + u8 reg0_val = 0; /* clear response register */ u8 reg1_val = 0xB5; /* release ownership flag */ WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2c2f6d5..0fb6556 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -151,7 +151,7 @@ static void sm_init(device_t dev) pm_iowrite(0x55, byte); byte = pm_ioread(0xD7); - byte |= 1 << 6 | 1 << 1;; + byte |= 1 << 6 | 1 << 1; pm_iowrite(0xD7, byte); /* 2.15 */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..213cae9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -276,7 +276,7 @@ void sb800_pci_port80(void) pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index e4c8208..09874f7 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -212,7 +212,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index f9ac8ee..68f03e0 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c index 5b3bc56..ecd81b3 100644 --- a/src/southbridge/via/vt8237r/fadt.c +++ b/src/southbridge/via/vt8237r/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;

1 0

Patch set updated for coreboot: 91f6da0 Asus F2A85-M: show POST codes
by Idwer Vollering 22 Dec '13

22 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4561 -gerrit commit 91f6da05c8a72b138c4af006ff658f374e7e94b2 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:01:51 2013 +0000 Asus F2A85-M: show POST codes Add conditional POST code output, toggled by CONFIG_IO_POST. Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index fe66dde..df21ede 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,7 +64,9 @@ static void sbxxx_enable_48mhzout(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { +#if CONFIG_IO_POST_PORT hudson_pci_port80(); +#endif u32 val; u8 byte;

1 0

New patch to review for coreboot: 797e16c Coding style: punctuation cleanup.
by Idwer Vollering 22 Dec '13

22 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4562 -gerrit commit 797e16c83142177d4590eb0b35afdd328b5ed374 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:38:18 2013 +0000 Coding style: punctuation cleanup. Clean up line terminators, found with: for f in $(git grep ";;" src | egrep -v 'asm|for|inc' | cut -d: -f1) ; do nano $f ; done Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/i2c/rtd2132/rtd2132.c | 2 +- src/ec/quanta/it8518/ec.c | 4 ++-- src/lib/cbfs.c | 2 +- src/lib/dynamic_cbmem.c | 2 +- src/mainboard/google/bolt/smihandler.c | 2 +- src/mainboard/google/falco/smihandler.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/peppy/smihandler.c | 2 +- src/mainboard/google/slippy/smihandler.c | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- src/northbridge/intel/i5000/raminit.c | 4 ++-- src/northbridge/via/vx800/detection.c | 2 +- src/northbridge/via/vx800/freq_setting.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 4 ++-- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/intel/i82371eb/fadt.c | 2 +- src/southbridge/nvidia/mcp55/fadt.c | 2 +- src/southbridge/via/vt8237r/fadt.c | 2 +- .../f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- .../f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 2 +- src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 2 +- 26 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 22a9f03..44333ac 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -181,7 +181,7 @@ static void rtd2132_lvds_swap(device_t dev, if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL) swap_value |= RTD2132_LVDS_SWAP_DUAL; - printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value);; + printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value); rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 4798cee..6516cee 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -40,7 +40,7 @@ static int input_buffer_empty(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { @@ -56,7 +56,7 @@ static int output_buffer_full(u16 status_reg) u32 timeout; for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) & KBD_OBF) == 0); timeout--) { - udelay(1000);; + udelay(1000); } if (!timeout) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23e1600..1f44695 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -312,7 +312,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated;; + void *address = buffer->buffer + buffer->allocated; DEBUG("simple_buffer_map(offset=%zd, count=%zd): " "allocated=%zd, size=%zd, last_allocate=%zd\n", offset, count, buffer->allocated, buffer->size, diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index e21f96e..b934aed 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -294,7 +294,7 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { struct cbmem_root *root; const struct cbmem_entry *entry; - unsigned long base;; + unsigned long base; u32 size; u32 aligned_size; diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c index 7b7dd69..b392852 100644 --- a/src/mainboard/google/bolt/smihandler.c +++ b/src/mainboard/google/bolt/smihandler.c @@ -149,7 +149,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c index bf2165f..511bfc5 100644 --- a/src/mainboard/google/falco/smihandler.c +++ b/src/mainboard/google/falco/smihandler.c @@ -166,7 +166,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 3785121..c545a86 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -153,7 +153,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 8a647dc..6f50a79 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -72,7 +72,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid switch GPIO active high (open). */ gpios->gpios[3].port = 15; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = ((gp_lvl >> 15) & 1);; + gpios->gpios[3].value = ((gp_lvl >> 15) & 1); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button */ diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c index f225468..e95dc4c 100644 --- a/src/mainboard/google/peppy/smihandler.c +++ b/src/mainboard/google/peppy/smihandler.c @@ -163,7 +163,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index dd0a605..f8eac31 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -150,7 +150,7 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index d6860b2..8c45332 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index) //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 7055c7a..4be7d5d 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1283,8 +1283,8 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) } printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); - printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; - printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1); + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2); pci_write_config16(dev16, I5000_MIR0, mir0); pci_write_config16(dev16, I5000_MIR1, mir1); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index eb1ddcc..69e520c 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -180,7 +180,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) DramAttr->DimmNumChB++; DramAttr->LoadNumChB = (u8) (DramAttr->LoadNumChB * LoadNum * - RankNum);; + RankNum); } RankNum |= 1; /* Set rank map. */ DramAttr->RankPresentMap |= (RankNum << (Sockets * 2)); diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 65b058a..55a6316 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -65,7 +65,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) Data = (u8) ((Data & 0xf8) | 6); break; default: - Data = (u8) ((Data & 0xf8) | 1);; + Data = (u8) ((Data & 0xf8) | 1); } pci_write_config8(MEMCTRL, 0x90, Data); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1c052c0..f148ffe 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -426,7 +426,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms, } else { /* Otherwise, everything is held in the first bank */ ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = 0;; + ranks->phys_rank_size_mb[(i << 1) | 1] = 0; } } } @@ -1294,7 +1294,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, { /* Same timeout reasoning as in receive delays */ size_t n_tries = 0; - int dq_tries = 0, dqs_tries = 0;; + int dq_tries = 0, dqs_tries = 0; const size_t max_tries = 100; for (;;) { if (n_tries++ >= max_tries) { diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index d85a515..3b2f556 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -117,7 +117,7 @@ static void ImcSleep(void) static void ImcWakeup(void) { u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ - u8 reg0_val = 0;; /* clear response register */ + u8 reg0_val = 0; /* clear response register */ u8 reg1_val = 0xB5; /* release ownership flag */ WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2c2f6d5..0fb6556 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -151,7 +151,7 @@ static void sm_init(device_t dev) pm_iowrite(0x55, byte); byte = pm_ioread(0xD7); - byte |= 1 << 6 | 1 << 1;; + byte |= 1 << 6 | 1 << 1; pm_iowrite(0xD7, byte); /* 2.15 */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..213cae9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -276,7 +276,7 @@ void sb800_pci_port80(void) pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index e4c8208..09874f7 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -212,7 +212,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index f9ac8ee..68f03e0 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c index 5b3bc56..ecd81b3 100644 --- a/src/southbridge/via/vt8237r/fadt.c +++ b/src/southbridge/via/vt8237r/fadt.c @@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 370a825..ab86118 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -533,7 +533,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index ae9fd5c..fa48682 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -531,7 +531,7 @@ PcieTopologyInitSrbmReset ( ) { UINT32 pcireg; - UINT32 regmask = 0x7030;; + UINT32 regmask = 0x7030; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c index 55adc8a..61bc58c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c @@ -837,7 +837,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c index 99a28b1..d0e66b9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c @@ -842,7 +842,7 @@ LibAmdPciWrite ( LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); } else { // Setup the MMIO address diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 3a8b32f..9a64e7e 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -159,7 +159,7 @@ AmdSbDispatcher ( } if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { - sbECfancontrolservice((AMDSBCFG*)pConfig);; + sbECfancontrolservice((AMDSBCFG*)pConfig); } #endif return Status;

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coreboot-gerrit December 2013