the following patch was just integrated into master:
commit d1d9b49b02967371ba6fe9447a047722310007f1
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Dec 20 17:47:19 2013 +0100
Remove PCI_ROM_RUN option
The main purpose of option rom is to supply int* handlers.
But supplying those is outside of coreboot scope and if someone needs those
they should run SeaBIOS anyway which runs the option roms wonderfully.
Running VGA oprom is kept because they're needed to init graphics.
This patch still keeps the options to include the option roms to make them
available to SeaBIOS.
Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/4545 for details.
-gerrit
the following patch was just integrated into master:
commit a8bba2597c208c013e59eaa0b4d502d19c1dc72b
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Dec 6 21:50:55 2013 +0200
usbdebug: Add option to disable console for romstage
If there is trouble setting up usbdebug, it may be useful to delay
usbdebug init to run in ramstage.
Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/4488 for details.
-gerrit
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4567
-gerrit
commit 007fa11d63a75ed46c175cf59ea2dd5ae02b50e6
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Dec 22 23:14:27 2013 +0200
AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all
K8 rev F boards do the same things here.
Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/serengeti_cheetah/romstage.c | 2 --
src/mainboard/asus/m2n-e/romstage.c | 2 --
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 --
src/mainboard/gigabyte/m57sli/romstage.c | 2 --
src/mainboard/hp/dl145_g3/romstage.c | 2 --
src/mainboard/msi/ms7260/romstage.c | 2 --
src/mainboard/nvidia/l1_2pvv/romstage.c | 2 --
src/mainboard/supermicro/h8dme/romstage.c | 2 --
src/mainboard/supermicro/h8dmr/romstage.c | 2 --
src/mainboard/tyan/s2912/romstage.c | 2 --
src/northbridge/amd/amdk8/raminit_f_dqs.c | 5 +++--
11 files changed, 3 insertions(+), 22 deletions(-)
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 8d985b7..20fe0f3 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -137,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index b6d7625..62891ff 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -123,10 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
-#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
-#endif
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index e06cb5b..09e9857 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -147,9 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 469e195..3004f7f 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -150,9 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 3d2d3cd..4b31bb7 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -160,9 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain();
wait_all_core0_started();
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 96a0c1b..0252402 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -141,10 +141,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex8(bsp_apicid);
print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
-#endif
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 4497a37..5530579 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -139,9 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 9363c63..d92c348 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -207,9 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex8(bsp_apicid);
print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
/* dump_smbus_registers(); */
setup_coherent_ht_domain(); // routing table and start other core0
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index daae389..268f120 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -134,9 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 511f902..2345a84 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -137,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 4438340..95987b2 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1793,6 +1793,7 @@ static void clear_mtrr_dqs(unsigned tom2_k)
}
}
+#if CONFIG_MEM_TRAIN_SEQ == 1
static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
{
uint32_t dword;
@@ -1802,8 +1803,6 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword);
}
-
-#if CONFIG_MEM_TRAIN_SEQ == 1
static unsigned get_htic_bit(unsigned i, unsigned bit)
{
uint32_t dword;
@@ -1822,7 +1821,9 @@ static void wait_till_sysinfo_in_ram(void)
static void set_sysinfo_in_ram(unsigned val)
{
+#if CONFIG_MEM_TRAIN_SEQ == 1
set_htic_bit(0, val, 9);
+#endif
}
#if CONFIG_HAVE_ACPI_RESUME