coreboot-gerrit December 2013

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Patch set updated for coreboot: dc31b65 cpu/allwinner/a10: Refactor and document pinmux API
by Alexandru Gagniuc 25 Dec '13

25 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4565 -gerrit commit dc31b65fe7094743a48c16bff607a8c82bffc035 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 21:30:21 2013 -0500 cpu/allwinner/a10: Refactor and document pinmux API Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 3 +- src/cpu/allwinner/a10/pinmux.c | 51 +++++++++++++++++++++++++- src/mainboard/cubietech/cubieboard/bootblock.c | 7 ++-- 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index f285451..709f74b 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -46,6 +46,7 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); -void gpio_set_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func); #endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index 083f7ec..ae73009 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -11,7 +11,14 @@ static struct a10_gpio *gpio = (void *)GPIO_BASE; -void gpio_set_func(u8 port, u8 pin, u8 pad_func) +/** + * \brief Set the pad function of a single pin + * + * @param [in] port GPIO port of the pin (GPA -> GPS) + * @param [in] pin the pin number in the given port (1 -> 31) + * @param [in] pad_func The peripheral function to which to connect this pin + */ +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) { u8 reg, bit; u32 reg32; @@ -28,3 +35,45 @@ void gpio_set_func(u8 port, u8 pin, u8 pad_func) reg32 |= (pad_func & 0xf) << bit; write32(reg32, &gpio->port[port].cfg[reg]); } + +/** + * \brief Set the pad function of a group of pins + * + * Multiplex a group of pins to the same pad function. This is useful for + * peripherals that use the same function number for several pins. This function + * allows those pins to be set with a single call. + * + * Example: + * gpio_set_multipin_func(GPB, (1 << 23) | (1 << 22), 2); + * + * @param [in] port GPIO port of the pin (GPA -> GPS) + * @param [in] pin_mask 32-bit mask indicating which pins to re-multiplex. For + * each set bit, the corresponding pin will be multiplexed. + * @param [in] pad_func The peripheral function to which to connect the pins + */ +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) +{ + int j; + u8 reg, bit; + u32 reg32, mask_offset; + + if ((port > GPS)) + return; + + for (reg = 0; reg < 4; reg++) { + mask_offset = 8 * reg; + /* Don't run the inner loop if we're not touching any pins */ + if (!(pin_mask & (0xff << mask_offset))) + continue; + + reg32 = read32(&gpio->port[port].cfg[reg]); + for (j = 0; j < 8; j++) { + if (!(pin_mask & (1 << (j + mask_offset)))) + continue; + bit = j * 4; + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + } + write32(reg32, &gpio->port[port].cfg[reg]); + } +} diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 6e8b751..a91391c 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -18,8 +18,8 @@ | AHB_DIV_1 \ | AXI_DIV_1 -#define GPB22_UART0_TX_FUNC 2 -#define GPB23_UART0_RX_FUNC 2 +#define GPB_UART0_FUNC 2 +#define GPB_UART0_PINS ((1 << 22) | (1 << 23)) static void cubieboard_set_sys_clock(void) { @@ -57,8 +57,7 @@ static void cubieboard_setup_clocks(void) static void cubieboard_setup_gpios(void) { /* Mux UART pins */ - gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); - gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); + gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); } static void cubieboard_enable_uart(void)

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Patch set updated for coreboot: e21d70b cpu: Add initial support for Allwinner A10 SoC
by Alexandru Gagniuc 25 Dec '13

25 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4549 -gerrit commit e21d70bb84cf1ba1622bd3d20eb62830a765b454 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:44:48 2013 -0600 cpu: Add initial support for Allwinner A10 SoC Add minimal support needed to get a bootblock capable of initialising a serial console. Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/allwinner/Kconfig | 10 +++ src/cpu/allwinner/Makefile.inc | 1 + src/cpu/allwinner/a10/Kconfig | 108 +++++++++++++++++++++++++ src/cpu/allwinner/a10/Makefile.inc | 35 ++++++++ src/cpu/allwinner/a10/bootblock.c | 21 +++++ src/cpu/allwinner/a10/bootblock_media.c | 14 ++++ src/cpu/allwinner/a10/clock.h | 137 ++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/gpio.h | 51 ++++++++++++ src/cpu/allwinner/a10/memmap.h | 117 +++++++++++++++++++++++++++ src/cpu/allwinner/a10/monotonic_timer.c | 13 +++ src/cpu/allwinner/a10/pinmux.c | 30 +++++++ src/cpu/allwinner/a10/timer.c | 19 +++++ src/cpu/allwinner/a10/uart.c | 92 +++++++++++++++++++++ src/cpu/allwinner/a10/uart.h | 102 ++++++++++++++++++++++++ src/cpu/allwinner/a10/uart_console.c | 109 +++++++++++++++++++++++++ 17 files changed, 861 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index cd6c7a0..f3883d3 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,6 +3,7 @@ # (See also src/Kconfig) if ARCH_ARMV7 +source src/cpu/allwinner/Kconfig source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig source src/cpu/ti/Kconfig diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 7cd9d5f..f206fdc 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,6 +1,7 @@ ################################################################################ ## Subdirectories ################################################################################ +subdirs-y += allwinner subdirs-y += amd subdirs-y += dmp subdirs-y += armltd diff --git a/src/cpu/allwinner/Kconfig b/src/cpu/allwinner/Kconfig new file mode 100644 index 0000000..d73d0af --- /dev/null +++ b/src/cpu/allwinner/Kconfig @@ -0,0 +1,10 @@ +config CPU_ALLWINNER_A10 + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + bool + default n + +source src/cpu/allwinner/a10/Kconfig diff --git a/src/cpu/allwinner/Makefile.inc b/src/cpu/allwinner/Makefile.inc new file mode 100644 index 0000000..e52a12e --- /dev/null +++ b/src/cpu/allwinner/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_ALLWINNER_A10) += a10 diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig new file mode 100644 index 0000000..646fe80 --- /dev/null +++ b/src/cpu/allwinner/a10/Kconfig @@ -0,0 +1,108 @@ +if CPU_ALLWINNER_A10 + +config BOOTBLOCK_CPU_INIT + string + default "cpu/allwinner/a10/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# The "eGON.BT0" header takes 32 bytes +config BOOTBLOCK_BASE + hex + default 0x20 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x00 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x10 + +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + default 0x4c00 + +# FIXME: untested +config ROMSTAGE_BASE + hex + default SYS_SDRAM_BASE + +# Keep the stack in SRAM +config STACK_TOP + hex + default 0x00008000 + +config STACK_BOTTOM + hex + default 0x00004000 + +config STACK_SIZE + hex + default 0x00004000 + +## TODO Change this to some better address not overlapping bootblock when +## cbfstool supports creating header in arbitrary location. +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x40 + +config SYS_SDRAM_BASE + hex + default 0x40000000 + +# FIXME: this can probably be smaller +config COREBOOT_TABLES_SIZE + hex + default 0x800 + +choice CONSOLE_SERIAL_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART0 + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +config CONSOLE_SERIAL_UART4 + bool "UART4" + help + Serial console on UART4 + +config CONSOLE_SERIAL_UART5 + bool "UART5" + help + Serial console on UART5 + +config CONSOLE_SERIAL_UART6 + bool "UART6" + help + Serial console on UART6 + +config CONSOLE_SERIAL_UART7 + bool "UART7" + help + Serial console on UART7 + +endchoice + +endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc new file mode 100644 index 0000000..48f3110 --- /dev/null +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -0,0 +1,35 @@ +bootblock-y += pinmux.c +bootblock-y += bootblock_media.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c + +romstage-y += uart.c +romstage-y += uart_console.c +romstage-y += bootblock_media.c + +ramstage-y += uart.c +ramstage-y += uart_console.c +ramstage-y += timer.c +ramstage-y += monotonic_timer.c +ramstage-y += bootblock_media.c + + +real-target: $(obj)/BOOT0 + +get_bootblock_size= \ + $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ + sed 's/[^0-9 ]//g')) \ + $(shell echo $$(($(word 2, $(strip $(bb_s)))))) + +# The boot ROM in the SoC will start loading code if a special boot0 header is +# found (at an offset of 8KiB in either NAND or SD), and the checksum is +# correct. this header is normally added by the 'mxsunxiboot' tool. The file +# passed to mksunxiboot should only include the bootblock due to size +# limitations. +# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy +# the first 15 KiB of coreboot.rom (This will not collide with stack) +$(obj)/BOOT0: $(obj)/coreboot.rom + @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + touch $@ + dd if=$^ of=$^.tmp bs=1024 count=15 + -mksunxiboot $^.tmp $@ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c new file mode 100644 index 0000000..38fe953 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock.c @@ -0,0 +1,21 @@ +/* + * Allwinner A10 bootblock initialization + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> +#include <arch/cache.h> + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + uint32_t sctlr; + + /* enable dcache */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C; + write_sctlr(sctlr); +} diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c new file mode 100644 index 0000000..a5863b6 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock_media.c @@ -0,0 +1,14 @@ +/* + * CBFS accessors for bootblock stage. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ +#include <cbfs.h> +#include <console/console.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet."); + return 0; +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h new file mode 100644 index 0000000..e028d13 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.h @@ -0,0 +1,137 @@ +/* + * Definitions for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_CLOCK_H +#define CPU_ALLWINNER_A10_CLOCK_H + +#include "memmap.h" +#include <types.h> + +/* CPU_AHB_APB0 config values */ +#define CPU_CLK_SRC_MASK (3 << 16) +#define CPU_CLK_SRC_OSC24M (1 << 16) +#define CPU_CLK_SRC_PLL1 (2 << 16) +#define APB0_DIV_MASK (3 << 8) +#define APB0_DIV_1 (0 << 8) +#define APB0_DIV_2 (1 << 8) +#define APB0_DIV_4 (2 << 8) +#define APB0_DIV_8 (3 << 8) +#define AHB_DIV_MASK (3 << 4) +#define AHB_DIV_1 (0 << 4) +#define AHB_DIV_2 (1 << 4) +#define AHB_DIV_4 (2 << 4) +#define AHB_DIV_8 (3 << 4) +#define AXI_DIV_MASK (3 << 0) +#define AXI_DIV_1 (0 << 0) +#define AXI_DIV_2 (1 << 0) +#define AXI_DIV_3 (2 << 0) +#define AXI_DIV_4 (3 << 0) + +/* APB1_CLK_DIV values */ +#define APB1_CLK_SRC_MASK (3 << 24) +#define APB1_CLK_SRC_OSC24M (0 << 24) +#define APB1_CLK_SRC_PLL6 (1 << 24) +#define APB1_CLK_SRC_32K (2 << 24) +#define APB1_RAT_N_MASK (3 << 16) +#define APB1_RAT_N(m) (((m) & 0x3) << 16) +#define APB1_RAT_M_MASK 0x1f << 0) +#define APB1_RAT_M(n) (((n) & 0x1f) << 0) + +/* APB0_GATING values */ +#define APB0_GATE_KEYPAD (1 << 10) +#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) +#define APB0_GATE_PIO (1 << 5) +#define APB0_GATE_IIS (1 << 3) +#define APB0_GATE_AC97 (1 << 2) +#define APB0_GATE_CODEC (1 << 0) + +/* APB1_GATING values */ +#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) +#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) +#define APB1_GATE_CAN (1 << 4) +#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) + +struct a10_ccm { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ +} __attribute__ ((packed)); + +#endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h new file mode 100644 index 0000000..f285451 --- /dev/null +++ b/src/cpu/allwinner/a10/gpio.h @@ -0,0 +1,51 @@ +/* + * Definitions for GPIO and pin multiplexing on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CPU_ALLWINNER_A10_PINMUX_H +#define __CPU_ALLWINNER_A10_PINMUX_H + +#include <types.h> + +#define GPIO_BASE 0x01C20800 + +#define GPA 0 +#define GPB 1 +#define GPC 2 +#define GPD 3 +#define GPE 4 +#define GPF 5 +#define GPG 6 +#define GPH 7 +#define GPI 8 +#define GPS 9 + +struct a10_gpio_port { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pul[2]; +} __attribute__ ((packed)); + +struct a10_gpio { + struct a10_gpio_port port[10]; + u8 reserved_0x168[0x98]; + + /* Offset 0x200 */ + u32 int_cfg[4]; + + u32 int_ctl; + u32 int_sta; + u8 reserved_0x21C[4]; + u32 int_deb; + + u32 sdr_pad_drv; + u32 sdr_pad_pul; +} __attribute__ ((packed)); + +void gpio_set_func(u8 port, u8 pin, u8 pad_func); + +#endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h new file mode 100644 index 0000000..78d81dc --- /dev/null +++ b/src/cpu/allwinner/a10/memmap.h @@ -0,0 +1,117 @@ +/* + * Memory map definitions for Allwinner A10 CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_MEMMAP_H +#define CPU_ALLWINNER_A10_MEMMAP_H + +#define A1X_SRAM_A1_BASE 0x00000000 +#define A1X_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define A1X_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define A1X_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define A1X_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define A1X_SRAM_D_BASE 0x01c00000 +#define A1X_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */ + +#define A1X_SRAMC_BASE 0x01c00000 +#define A1X_DRAMC_BASE 0x01c01000 +#define A1X_DMA_BASE 0x01c02000 +#define A1X_NFC_BASE 0x01c03000 +#define A1X_TS_BASE 0x01c04000 +#define A1X_SPI0_BASE 0x01c05000 +#define A1X_SPI1_BASE 0x01c06000 +#define A1X_MS_BASE 0x01c07000 +#define A1X_TVD_BASE 0x01c08000 +#define A1X_CSI0_BASE 0x01c09000 +#define A1X_TVE0_BASE 0x01c0a000 +#define A1X_EMAC_BASE 0x01c0b000 +#define A1X_LCD0_BASE 0x01c0C000 +#define A1X_LCD1_BASE 0x01c0d000 +#define A1X_VE_BASE 0x01c0e000 +#define A1X_MMC0_BASE 0x01c0f000 +#define A1X_MMC1_BASE 0x01c10000 +#define A1X_MMC2_BASE 0x01c11000 +#define A1X_MMC3_BASE 0x01c12000 +#define A1X_USB0_BASE 0x01c13000 +#define A1X_USB1_BASE 0x01c14000 +#define A1X_SS_BASE 0x01c15000 +#define A1X_HDMI_BASE 0x01c16000 +#define A1X_SPI2_BASE 0x01c17000 +#define A1X_SATA_BASE 0x01c18000 +#define A1X_PATA_BASE 0x01c19000 +#define A1X_ACE_BASE 0x01c1a000 +#define A1X_TVE1_BASE 0x01c1b000 +#define A1X_USB2_BASE 0x01c1c000 +#define A1X_CSI1_BASE 0x01c1d000 +#define A1X_TZASC_BASE 0x01c1e000 +#define A1X_SPI3_BASE 0x01c1f000 + +#define A1X_CCM_BASE 0x01c20000 +#define A1X_INTC_BASE 0x01c20400 +#define A1X_PIO_BASE 0x01c20800 +#define A1X_TIMER_BASE 0x01c20c00 +#define A1X_SPDIF_BASE 0x01c21000 +#define A1X_AC97_BASE 0x01c21400 +#define A1X_IR0_BASE 0x01c21800 +#define A1X_IR1_BASE 0x01c21c00 + +#define A1X_IIS_BASE 0x01c22400 +#define A1X_LRADC_BASE 0x01c22800 +#define A1X_AD_DA_BASE 0x01c22c00 +#define A1X_KEYPAD_BASE 0x01c23000 +#define A1X_TZPC_BASE 0x01c23400 +#define A1X_SID_BASE 0x01c23800 +#define A1X_SJTAG_BASE 0x01c23c00 + +#define A1X_TP_BASE 0x01c25000 +#define A1X_PMU_BASE 0x01c25400 +#define A1X_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */ + +#define A1X_UART0_BASE 0x01c28000 +#define A1X_UART1_BASE 0x01c28400 +#define A1X_UART2_BASE 0x01c28800 +#define A1X_UART3_BASE 0x01c28c00 +#define A1X_UART4_BASE 0x01c29000 +#define A1X_UART5_BASE 0x01c29400 +#define A1X_UART6_BASE 0x01c29800 +#define A1X_UART7_BASE 0x01c29c00 +#define A1X_PS2_0_BASE 0x01c2a000 +#define A1X_PS2_1_BASE 0x01c2a400 + +#define A1X_TWI0_BASE 0x01c2ac00 +#define A1X_TWI1_BASE 0x01c2b000 +#define A1X_TWI2_BASE 0x01c2b400 + +#define A1X_CAN_BASE 0x01c2bc00 + +#define A1X_SCR_BASE 0x01c2c400 + +#define A1X_GPS_BASE 0x01c30000 +#define A1X_MALI400_BASE 0x01c40000 + +/* module sram */ +#define A1X_SRAM_C_BASE 0x01d00000 + +#define A1X_DE_FE0_BASE 0x01e00000 +#define A1X_DE_FE1_BASE 0x01e20000 +#define A1X_DE_BE0_BASE 0x01e60000 +#define A1X_DE_BE1_BASE 0x01e40000 +#define A1X_MP_BASE 0x01e80000 +#define A1X_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define A1X_CSDM_BASE 0x3f500000 + +#define A1X_DRAM_BASE 0x40000000 /* 2 GiB */ + +#define A1X_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define A1X_CPU_CFG (A1X_TIMER_BASE + 0x13c) + +#endif /* CPU_ALLWINNER_A10_MEMMAP_H */ diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c new file mode 100644 index 0000000..16d478a --- /dev/null +++ b/src/cpu/allwinner/a10/monotonic_timer.c @@ -0,0 +1,13 @@ +/* + * Placeholder for code to come (needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + (void)mt; +} diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c new file mode 100644 index 0000000..083f7ec --- /dev/null +++ b/src/cpu/allwinner/a10/pinmux.c @@ -0,0 +1,30 @@ +/* + * Helpers to multiplex and configure pins on Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "gpio.h" + +#include <arch/io.h> + +static struct a10_gpio *gpio = (void *)GPIO_BASE; + +void gpio_set_func(u8 port, u8 pin, u8 pad_func) +{ + u8 reg, bit; + u32 reg32; + + if ((port > GPS)) + return; + + pin &= 0x1f; + reg = pin / 8; + bit = (pin % 8) * 4; + + reg32 = read32(&gpio->port[port].cfg[reg]); + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + write32(reg32, &gpio->port[port].cfg[reg]); +} diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c new file mode 100644 index 0000000..e156398 --- /dev/null +++ b/src/cpu/allwinner/a10/timer.c @@ -0,0 +1,19 @@ +/* + * Placeholder for code to come(needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <delay.h> +#include <timer.h> + +void init_timer(void) +{ + /* Stub */ +} + +void udelay(unsigned usec) +{ + /* Stub */ +} diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c new file mode 100644 index 0000000..923c7c1 --- /dev/null +++ b/src/cpu/allwinner/a10/uart.c @@ -0,0 +1,92 @@ +/* + * Uart setup helpers for Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "uart.h" +#include <arch/io.h> + +/** + * \brief Configure line control settings for UART + */ +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits) +{ + u32 reg32; + u16 div; + struct a10_uart *uart = uart_base; + + /* Enable access to Divisor Latch register */ + write32(UART_LCR_DLAB, &uart->lcr); + /* Set baudrate */ + /* FIXME: We assume clock is 24MHz, which may not be the case */ + div = 24000000 / 16 / baud_rate; + write32((div >> 8) & 0xff, &uart->dlh); + write32(div & 0xff, &uart->dll); + /* Set line control */ + reg32 = UART_LCR_DATALEN(data_bits); + switch (parity) { + case UART_PARITY_ODD: + reg32 |= UART_LCR_PEN; + break; + case UART_PARITY_EVEN: + reg32 |= UART_LCR_PEN; + reg32 |= UART_LCR_EPS; + break; + case UART_PARITY_NONE: /* Fall through */ + default: + break; + } + write32(reg32, &uart->lcr); +} + +void a10_uart_enable_fifos(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + write32(UART_FCR_FIFOE, &uart->fcr); +} + +static int tx_fifo_full(struct a10_uart *uart) +{ + /* This may be a misnomer, or a typo in the datasheet. THRE indicates + * that the TX register is empty, not that the FIFO is not full, but + * this may be due to a datasheet typo. Keep the current name to signal + * intent. */ + return !(read32(&uart->lsr) & UART_LSR_THRE); +} + +static int rx_fifo_empty(struct a10_uart *uart) +{ + return !(read32(&uart->lsr) & UART_LSR_DR); +} + +/** + * \brief Read a single byte from the UART. + * + * Blocks until at least a byte is available. + */ +u8 a10_uart_rx_blocking(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + while (rx_fifo_empty(uart)) ; + + return read32(&uart->rbr); +} + +/** + * \brief Write a single byte to the UART. + * + * Blocks until there is space in the FIFO. + */ +void a10_uart_tx_blocking(void *uart_base, u8 data) +{ + struct a10_uart *uart = uart_base; + + while (tx_fifo_full(uart)) ; + + return write32(data, &uart->thr); +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h new file mode 100644 index 0000000..c324dc1d --- /dev/null +++ b/src/cpu/allwinner/a10/uart.h @@ -0,0 +1,102 @@ +/* + * Definitions for UART on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_UART_H +#define CPU_ALLWINNER_A10_UART_H + +#include "memmap.h" +#include <types.h> + +/* UART_FCR definitions */ +#define UART_FCR_DMAM (1 << 3) +#define UART_FCR_XFIFOR (1 << 2) +#define UART_FCR_RFIFOR (1 << 1) +#define UART_FCR_FIFOE (1 << 0) + +/* UART_LCR definitions */ +#define UART_LCR_DLAB (1 << 7) +#define UART_LCR_BC (1 << 6) +#define UART_LCR_EPS (1 << 4) +#define UART_LCR_PEN (1 << 3) +#define UART_LCR_STOP_MASK (0x3 << 2) +#define UART_LCR_STOP_1BIT (0 << 2) +#define UART_LCR_STOP_2BIT (1 << 2) +#define UART_LCR_DLS_MASK (3 << 0) +#define UART_LCR_DATALEN(bits) ((bits - 5) & UART_LCR_DLS_MASK) + +/* UART_LSR definitions */ +#define UART_LSR_FIFOERR (1 << 7) +#define UART_LSR_TEMT (1 << 6) +#define UART_LSR_THRE (1 << 5) +#define UART_LSR_BI (1 << 4) +#define UART_LSR_FE (1 << 3) +#define UART_LSR_PE (1 << 2) +#define UART_LSR_OE (1 << 1) +#define UART_LSR_DR (1 << 0) + +#define BAUD_115200 (0xd) + +struct a10_uart { + union { + /* operational mode */ + u32 rbr; /* receiver buffer (read) */ + u32 thr; /* transmit holding (write) */ + /* config mode A and B */ + u32 dll; /* divisor latches low */ + }; + + union { + /* operational mode */ + u32 ier; /* interrupt enable */ + /* config mode A and B */ + u32 dlh; /* divisor latches high */ + }; + + union { + /* operational mode, config mode A */ + u32 iir; /* interrupt ID (read) */ + u32 fcr; /* FIFO control (write) */ + }; + + u32 lcr; /* line control */ + + /* 0x10 */ + u32 mcr; /* modem control */ + u32 lsr; /* line status, read-only */ + u32 msr; /* modem status */ + u32 sch; /* trigger level */ + + u8 reserved_0x20[0x50]; + + /* 0x70 */ + u8 reserved_0x70[0xc]; + u32 usr; /* frequency select */ + + /* 0x80 */ + u32 tfl; /* mode definition register 3 */ + u32 rfl; + u8 reserved_0x88[0x18]; + + /* 0xa0 */ + u8 reserved_0xa0[4]; + u32 halt; /* TX DMA threshold */ + +} __attribute__ ((packed)); + +enum uart_parity { + UART_PARITY_NONE, + UART_PARITY_EVEN, + UART_PARITY_ODD, +}; + +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits); +void a10_uart_enable_fifos(void *uart_base); +u8 a10_uart_rx_blocking(void *uart_base); +void a10_uart_tx_blocking(void *uart_base, u8 data); + +#endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c new file mode 100644 index 0000000..58930dd --- /dev/null +++ b/src/cpu/allwinner/a10/uart_console.c @@ -0,0 +1,109 @@ +/* + * Glue to UART code to enable serial console + * + * Copyright 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> +#include <types.h> +#include <uart.h> +#include <arch/io.h> + +#include <console/console.h> +#include <cpu/allwinner/a10/uart.h> + +static void *get_console_uart_base_addr(void) +{ + /* This big block gets compiled to a constant, not a function call */ + if (CONFIG_CONSOLE_SERIAL_UART0) + return (void *)A1X_UART0_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART1) + return (void *)A1X_UART1_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART2) + return (void *)A1X_UART2_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART3) + return (void *)A1X_UART3_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART4) + return (void *)A1X_UART4_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART5) + return (void *)A1X_UART5_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART6) + return (void *)A1X_UART6_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART7) + return (void *)A1X_UART7_BASE; + + /* If selection is invalid, default to UART0 */ + return (void *)A1X_UART0_BASE; +} + +static u32 get_console_uart_baud(void) +{ + if (CONFIG_CONSOLE_SERIAL_115200) + return 115200; + else if (CONFIG_CONSOLE_SERIAL_57600) + return 57600; + else if (CONFIG_CONSOLE_SERIAL_38400) + return 34800; + else if (CONFIG_CONSOLE_SERIAL_19200) + return 19200; + else if (CONFIG_CONSOLE_SERIAL_9600) + return 9600; + + /* Default to 115200 if selection is invalid */ + return 115200; +} + +static void a10_uart_init_dev(void) +{ + void *uart_base = get_console_uart_base_addr(); + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, get_console_uart_baud(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +static unsigned char a10_uart_rx_byte(void) +{ + return a10_uart_rx_blocking(get_console_uart_base_addr()); +} + +static void a10_uart_tx_byte(unsigned char data) +{ + a10_uart_tx_blocking(get_console_uart_base_addr(), data); +} + +uint32_t uartmem_getbaseaddr(void) +{ + return (uint32_t) get_console_uart_base_addr(); +} + +#if !defined(__PRE_RAM__) +static const struct console_driver a10_uart_console __console = { + .init = a10_uart_init_dev, + .tx_byte = a10_uart_tx_byte, + .rx_byte = a10_uart_rx_byte, +}; +#else + +void uart_init(void) +{ + a10_uart_init_dev(); +} + +unsigned char uart_rx_byte(void) +{ + return a10_uart_rx_byte(); +} + +void uart_tx_byte(unsigned char data) +{ + a10_uart_tx_byte(data); +} + +void uart_tx_flush(void) +{ +} + +#endif

1 0

Patch set updated for coreboot: 3640d85 Remove sprintf
by Vladimir Serbinenko 25 Dec '13

25 Dec '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4280 -gerrit commit 3640d8581c826b5b2da00fc76ae9443313fc16de Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:42:52 2013 +0100 Remove sprintf Remove sprintf as if you can't easily use snprintf then you probably have buffer overflow. Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/console/vsprintf.c | 14 -------------- src/include/string.h | 1 - 2 files changed, 15 deletions(-) diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index b1b6d47..1fb834f 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -57,20 +57,6 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) return i; } -int sprintf(char *buf, const char *fmt, ...) -{ - va_list args; - int i; - - va_start(args, fmt); - /* A trick: we have at most (size_t)-1 adressable space anyway, so - if we output so much we'll crash anyway. */ - i = vsnprintf(buf, -1, fmt, args); - va_end(args); - - return i; -} - int snprintf(char *buf, size_t size, const char *fmt, ...) { va_list args; diff --git a/src/include/string.h b/src/include/string.h index dc125e1..b4d0268 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -16,7 +16,6 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) -int sprintf(char * buf, const char *fmt, ...); int snprintf(char * buf, size_t size, const char *fmt, ...); #endif

1 0

Patch set updated for coreboot: 0eb0662 Replace all occurences of sprintf with snprintf
by Vladimir Serbinenko 25 Dec '13

25 Dec '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4279 -gerrit commit 0eb06626b59dccf63ab65738e8968bd605de8a17 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:41:26 2013 +0100 Replace all occurences of sprintf with snprintf THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 3 +- src/device/device_util.c | 83 ++++++++++++---------- src/device/oprom/x86emu/debug.c | 8 +-- src/ec/lenovo/h8/h8.c | 4 +- src/mainboard/google/link/i915.c | 2 +- src/mainboard/google/stout/i915.c | 2 +- src/mainboard/intel/wtm2/i915.c | 2 +- src/mainboard/lenovo/x60/i915.c | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 4 +- src/northbridge/amd/amdk8/northbridge.c | 4 +- src/southbridge/intel/lynxpoint/acpi.c | 2 +- 18 files changed, 70 insertions(+), 60 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 121cb22..6496d75 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -274,7 +274,8 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(0x83); len = acpigen_write_len_f(); - sprintf(pscope, "\\_PR.CPU%x", (unsigned int) cpuindex); + snprintf(pscope, sizeof (pscope), + "\\_PR.CPU%x", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/device/device_util.c b/src/device/device_util.c index cad2a06..38654fa 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -231,48 +231,52 @@ const char *dev_path(device_t dev) break; case DEVICE_PATH_PCI: #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary >> 8, - dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); + snprintf(buffer, sizeof (buffer), + "PCI: %04x:%02x:%02x.%01x", + dev->bus->secondary >> 8, + dev->bus->secondary & 0xff, + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #else - sprintf(buffer, "PCI: %02x:%02x.%01x", - dev->bus->secondary, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); + snprintf(buffer, sizeof (buffer), + "PCI: %02x:%02x.%01x", + dev->bus->secondary, + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #endif break; case DEVICE_PATH_PNP: - sprintf(buffer, "PNP: %04x.%01x", - dev->path.pnp.port, dev->path.pnp.device); + snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x", + dev->path.pnp.port, dev->path.pnp.device); break; case DEVICE_PATH_I2C: - sprintf(buffer, "I2C: %02x:%02x", - dev->bus->secondary, - dev->path.i2c.device); + snprintf(buffer, sizeof (buffer), "I2C: %02x:%02x", + dev->bus->secondary, + dev->path.i2c.device); break; case DEVICE_PATH_APIC: - sprintf(buffer, "APIC: %02x", - dev->path.apic.apic_id); + snprintf(buffer, sizeof (buffer), "APIC: %02x", + dev->path.apic.apic_id); break; case DEVICE_PATH_IOAPIC: - sprintf(buffer, "IOAPIC: %02x", - dev->path.ioapic.ioapic_id); + snprintf(buffer, sizeof (buffer), "IOAPIC: %02x", + dev->path.ioapic.ioapic_id); break; case DEVICE_PATH_DOMAIN: - sprintf(buffer, "DOMAIN: %04x", + snprintf(buffer, sizeof (buffer), "DOMAIN: %04x", dev->path.domain.domain); break; case DEVICE_PATH_CPU_CLUSTER: - sprintf(buffer, "CPU_CLUSTER: %01x", + snprintf(buffer, sizeof (buffer), "CPU_CLUSTER: %01x", dev->path.cpu_cluster.cluster); break; case DEVICE_PATH_CPU: - sprintf(buffer, "CPU: %02x", dev->path.cpu.id); + snprintf(buffer, sizeof (buffer), + "CPU: %02x", dev->path.cpu.id); break; case DEVICE_PATH_CPU_BUS: - sprintf(buffer, "CPU_BUS: %02x", dev->path.cpu_bus.id); + snprintf(buffer, sizeof (buffer), + "CPU_BUS: %02x", dev->path.cpu_bus.id); break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", @@ -296,7 +300,8 @@ const char *dev_name(device_t dev) const char *bus_path(struct bus *bus) { static char buffer[BUS_PATH_MAX]; - sprintf(buffer, "%s,%d", dev_path(bus->dev), bus->link_num); + snprintf(buffer, sizeof (buffer), + "%s,%d", dev_path(bus->dev), bus->link_num); return buffer; } @@ -584,15 +589,15 @@ resource_t resource_max(struct resource *resource) const char *resource_type(struct resource *resource) { static char buffer[RESOURCE_TYPE_MAX]; - sprintf(buffer, "%s%s%s%s", - ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""), - ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""), - ((resource->flags == 0) ? "unused" : - (resource->flags & IORESOURCE_IO) ? "io" : - (resource->flags & IORESOURCE_DRQ) ? "drq" : - (resource->flags & IORESOURCE_IRQ) ? "irq" : - (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"), - ((resource->flags & IORESOURCE_PCI64) ? "64" : "")); + snprintf(buffer, sizeof (buffer), "%s%s%s%s", + ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""), + ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""), + ((resource->flags == 0) ? "unused" : + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_DRQ) ? "drq" : + (resource->flags & IORESOURCE_IRQ) ? "irq" : + (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"), + ((resource->flags & IORESOURCE_PCI64) ? "64" : "")); return buffer; } @@ -618,10 +623,12 @@ void report_resource_stored(device_t dev, struct resource *resource, if (resource->flags & IORESOURCE_PCI_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, + snprintf(buf, sizeof (buf), + "bus %04x:%02x ", dev->bus->secondary >> 8, dev->link_list->secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link_list->secondary); + snprintf(buf, sizeof (buf), + "bus %02x ", dev->link_list->secondary); #endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " @@ -830,10 +837,12 @@ void show_one_resource(int debug_level, struct device *dev, /* if (resource->flags & IORESOURCE_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, - dev->link[0].secondary & 0xff); + snprintf(buf, sizeof (buf), "bus %04x:%02x ", + dev->bus->secondary >> 8, + dev->link[0].secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link[0].secondary); + snprintf(buf, sizeof (buf), + "bus %02x ", dev->link[0].secondary); #endif } */ diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index b3f4b6e..e7a111b 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -163,15 +163,15 @@ void x86emu_inc_decoded_inst_len (int x) void x86emu_decode_printf (const char *x) { - sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",x); + strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,x); M.x86.enc_str_pos += strlen(x); } void x86emu_decode_printf2 (const char *x, int y) { char temp[100]; - sprintf(temp,x,y); - sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",temp); + snprintf(temp, sizeof (temp), x,y); + strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,temp); M.x86.enc_str_pos += strlen(temp); } @@ -186,7 +186,7 @@ static void print_encoded_bytes (u16 s, u16 o) int i; char buf1[64]; for (i=0; i< M.x86.enc_pos; i++) { - sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); + snprintf(buf1+2*i, 64 - 2 * i, "%02x", fetch_data_byte_abs(s,o+i)); } printf("%-20s ",buf1); } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 4f9d228..213ede3 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -125,14 +125,14 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) for (i = 0; i < 8; i++) { c = ec_read(0xf0 + i); if (c < 0x20 || c > 0x7f) { - i = sprintf(str, "*INVALID"); + i = snprintf(str, sizeof (str), "*INVALID"); break; } str[i] = c; } /* EC firmware function specification version */ - i += sprintf(str + i, "-%u.%u", ec_read(0xef), ec_read(0xeb)); + i += snprintf(str + i, sizeof (str) - i, "-%u.%u", ec_read(0xef), ec_read(0xeb)); i = MIN(buf_len, i); memcpy(buf, str, i); diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 6481234..a38760b 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -78,7 +78,7 @@ const u32 link_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 89a8594..8085de6 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -88,7 +88,7 @@ setgtt(int start, int end, unsigned long base, int inc) static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c index df88138..b664c35 100644 --- a/src/mainboard/intel/wtm2/i915.c +++ b/src/mainboard/intel/wtm2/i915.c @@ -88,7 +88,7 @@ static int ioread = 0, iowrite = 0; static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 0d32672..ea01ef1 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -80,7 +80,7 @@ const u32 x60_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1c7e547..60f3951 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -657,7 +657,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index e6be598..9757d96 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -402,7 +402,7 @@ static void set_resource(device_t dev, struct resource *resource, set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7cc812b..847e6dd 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -402,7 +402,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) rbase >> 8, rend >> 8, 1); // [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a8cc1cc..aa9ec56 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -400,7 +400,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index b55d52b..2b5549d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b8bba50..6feabf4 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -380,7 +380,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index ee842d5..abba0ce 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -313,7 +313,7 @@ static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex) CONTROL = sspr + 0x8d; STATUS = sspr + 0x8f; - sprintf((char*)CPU, "%02x", (char)cpuindex); + snprintf((char*)CPU, 3, "%02x", (char)cpuindex); *CPUIN = (u8) cpuindex; for(i=0;i<sysconf.p_state_num;i++) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6bcab41..26e040f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -541,8 +541,8 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", - nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 8f0a11b..b0acdf7 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -479,8 +479,8 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", - nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index b619e6e..ef1c9d8 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -60,7 +60,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) static int acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) { char sio_name[5] = {}; - sprintf(sio_name, "S%1uEN", id); + snprintf(sio_name, sizeof (sio_name), "S%1uEN", id); return acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); }

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Patch set updated for coreboot: d3c63d8 Replace all occurences of sprintf with snprintf
by Vladimir Serbinenko 24 Dec '13

24 Dec '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4279 -gerrit commit d3c63d8c566fcd7a3a93916ea6bc80ad188e5c01 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:41:26 2013 +0100 Replace all occurences of sprintf with snprintf THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 3 +- src/device/device_util.c | 83 ++++++++++++---------- src/device/oprom/x86emu/debug.c | 8 +-- src/mainboard/google/link/i915.c | 2 +- src/mainboard/google/stout/i915.c | 2 +- src/mainboard/intel/wtm2/i915.c | 2 +- src/mainboard/lenovo/x60/i915.c | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 4 +- src/northbridge/amd/amdk8/northbridge.c | 4 +- 16 files changed, 67 insertions(+), 57 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 121cb22..6496d75 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -274,7 +274,8 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(0x83); len = acpigen_write_len_f(); - sprintf(pscope, "\\_PR.CPU%x", (unsigned int) cpuindex); + snprintf(pscope, sizeof (pscope), + "\\_PR.CPU%x", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/device/device_util.c b/src/device/device_util.c index cad2a06..38654fa 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -231,48 +231,52 @@ const char *dev_path(device_t dev) break; case DEVICE_PATH_PCI: #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary >> 8, - dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); + snprintf(buffer, sizeof (buffer), + "PCI: %04x:%02x:%02x.%01x", + dev->bus->secondary >> 8, + dev->bus->secondary & 0xff, + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #else - sprintf(buffer, "PCI: %02x:%02x.%01x", - dev->bus->secondary, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); + snprintf(buffer, sizeof (buffer), + "PCI: %02x:%02x.%01x", + dev->bus->secondary, + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #endif break; case DEVICE_PATH_PNP: - sprintf(buffer, "PNP: %04x.%01x", - dev->path.pnp.port, dev->path.pnp.device); + snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x", + dev->path.pnp.port, dev->path.pnp.device); break; case DEVICE_PATH_I2C: - sprintf(buffer, "I2C: %02x:%02x", - dev->bus->secondary, - dev->path.i2c.device); + snprintf(buffer, sizeof (buffer), "I2C: %02x:%02x", + dev->bus->secondary, + dev->path.i2c.device); break; case DEVICE_PATH_APIC: - sprintf(buffer, "APIC: %02x", - dev->path.apic.apic_id); + snprintf(buffer, sizeof (buffer), "APIC: %02x", + dev->path.apic.apic_id); break; case DEVICE_PATH_IOAPIC: - sprintf(buffer, "IOAPIC: %02x", - dev->path.ioapic.ioapic_id); + snprintf(buffer, sizeof (buffer), "IOAPIC: %02x", + dev->path.ioapic.ioapic_id); break; case DEVICE_PATH_DOMAIN: - sprintf(buffer, "DOMAIN: %04x", + snprintf(buffer, sizeof (buffer), "DOMAIN: %04x", dev->path.domain.domain); break; case DEVICE_PATH_CPU_CLUSTER: - sprintf(buffer, "CPU_CLUSTER: %01x", + snprintf(buffer, sizeof (buffer), "CPU_CLUSTER: %01x", dev->path.cpu_cluster.cluster); break; case DEVICE_PATH_CPU: - sprintf(buffer, "CPU: %02x", dev->path.cpu.id); + snprintf(buffer, sizeof (buffer), + "CPU: %02x", dev->path.cpu.id); break; case DEVICE_PATH_CPU_BUS: - sprintf(buffer, "CPU_BUS: %02x", dev->path.cpu_bus.id); + snprintf(buffer, sizeof (buffer), + "CPU_BUS: %02x", dev->path.cpu_bus.id); break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", @@ -296,7 +300,8 @@ const char *dev_name(device_t dev) const char *bus_path(struct bus *bus) { static char buffer[BUS_PATH_MAX]; - sprintf(buffer, "%s,%d", dev_path(bus->dev), bus->link_num); + snprintf(buffer, sizeof (buffer), + "%s,%d", dev_path(bus->dev), bus->link_num); return buffer; } @@ -584,15 +589,15 @@ resource_t resource_max(struct resource *resource) const char *resource_type(struct resource *resource) { static char buffer[RESOURCE_TYPE_MAX]; - sprintf(buffer, "%s%s%s%s", - ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""), - ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""), - ((resource->flags == 0) ? "unused" : - (resource->flags & IORESOURCE_IO) ? "io" : - (resource->flags & IORESOURCE_DRQ) ? "drq" : - (resource->flags & IORESOURCE_IRQ) ? "irq" : - (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"), - ((resource->flags & IORESOURCE_PCI64) ? "64" : "")); + snprintf(buffer, sizeof (buffer), "%s%s%s%s", + ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""), + ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""), + ((resource->flags == 0) ? "unused" : + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_DRQ) ? "drq" : + (resource->flags & IORESOURCE_IRQ) ? "irq" : + (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"), + ((resource->flags & IORESOURCE_PCI64) ? "64" : "")); return buffer; } @@ -618,10 +623,12 @@ void report_resource_stored(device_t dev, struct resource *resource, if (resource->flags & IORESOURCE_PCI_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, + snprintf(buf, sizeof (buf), + "bus %04x:%02x ", dev->bus->secondary >> 8, dev->link_list->secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link_list->secondary); + snprintf(buf, sizeof (buf), + "bus %02x ", dev->link_list->secondary); #endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " @@ -830,10 +837,12 @@ void show_one_resource(int debug_level, struct device *dev, /* if (resource->flags & IORESOURCE_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, - dev->link[0].secondary & 0xff); + snprintf(buf, sizeof (buf), "bus %04x:%02x ", + dev->bus->secondary >> 8, + dev->link[0].secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link[0].secondary); + snprintf(buf, sizeof (buf), + "bus %02x ", dev->link[0].secondary); #endif } */ diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index b3f4b6e..e7a111b 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -163,15 +163,15 @@ void x86emu_inc_decoded_inst_len (int x) void x86emu_decode_printf (const char *x) { - sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",x); + strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,x); M.x86.enc_str_pos += strlen(x); } void x86emu_decode_printf2 (const char *x, int y) { char temp[100]; - sprintf(temp,x,y); - sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",temp); + snprintf(temp, sizeof (temp), x,y); + strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,temp); M.x86.enc_str_pos += strlen(temp); } @@ -186,7 +186,7 @@ static void print_encoded_bytes (u16 s, u16 o) int i; char buf1[64]; for (i=0; i< M.x86.enc_pos; i++) { - sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); + snprintf(buf1+2*i, 64 - 2 * i, "%02x", fetch_data_byte_abs(s,o+i)); } printf("%-20s ",buf1); } diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 6481234..a38760b 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -78,7 +78,7 @@ const u32 link_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 89a8594..8085de6 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -88,7 +88,7 @@ setgtt(int start, int end, unsigned long base, int inc) static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c index df88138..b664c35 100644 --- a/src/mainboard/intel/wtm2/i915.c +++ b/src/mainboard/intel/wtm2/i915.c @@ -88,7 +88,7 @@ static int ioread = 0, iowrite = 0; static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 0d32672..ea01ef1 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -80,7 +80,7 @@ const u32 x60_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1c7e547..60f3951 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -657,7 +657,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index e6be598..9757d96 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -402,7 +402,7 @@ static void set_resource(device_t dev, struct resource *resource, set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7cc812b..847e6dd 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -402,7 +402,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) rbase >> 8, rend >> 8, 1); // [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a8cc1cc..aa9ec56 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -400,7 +400,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index b55d52b..2b5549d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b8bba50..6feabf4 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -380,7 +380,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index ee842d5..abba0ce 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -313,7 +313,7 @@ static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex) CONTROL = sspr + 0x8d; STATUS = sspr + 0x8f; - sprintf((char*)CPU, "%02x", (char)cpuindex); + snprintf((char*)CPU, 3, "%02x", (char)cpuindex); *CPUIN = (u8) cpuindex; for(i=0;i<sysconf.p_state_num;i++) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6bcab41..26e040f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -541,8 +541,8 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", - nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 8f0a11b..b0acdf7 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -479,8 +479,8 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", - nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); }

1 0

Patch set updated for coreboot: 33ba0d5 console/vsprintf: Implement snprintf
by Vladimir Serbinenko 24 Dec '13

24 Dec '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4278 -gerrit commit 33ba0d5453712f8cbf318664ac461d018767a576 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 22:07:47 2013 +0100 console/vsprintf: Implement snprintf snprintf is a safe variant of sprintf. To avoid buffer overflows we shouldn't use sprintf at all. But for now let's start by implementing snprintf in first place. Change-Id: Ic17d94b8cd91b72f66b84b0589a06b8abef5e5c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/console/vsprintf.c | 36 ++++++++++++++++++++++++++++-------- src/include/string.h | 1 + 2 files changed, 29 insertions(+), 8 deletions(-) diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 321ce81..b1b6d47 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -23,28 +23,34 @@ #include <console/vtxprintf.h> #include <trace.h> -struct vsprintf_context +struct vsnprintf_context { char *str_buf; + size_t buf_limit; }; static void str_tx_byte(unsigned char byte, void *data) { - struct vsprintf_context *ctx = data; - *ctx->str_buf = byte; - ctx->str_buf++; + struct vsnprintf_context *ctx = data; + if (ctx->buf_limit) { + *ctx->str_buf = byte; + ctx->str_buf++; + ctx->buf_limit--; + } } -static int vsprintf(char *buf, const char *fmt, va_list args) +static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) { int i; - struct vsprintf_context ctx; + struct vsnprintf_context ctx; DISABLE_TRACE; ctx.str_buf = buf; + ctx.buf_limit = size ? size - 1 : 0; i = vtxdprintf(str_tx_byte, fmt, args, &ctx); - *ctx.str_buf = '\0'; + if (size) + *ctx.str_buf = '\0'; ENABLE_TRACE; @@ -57,7 +63,21 @@ int sprintf(char *buf, const char *fmt, ...) int i; va_start(args, fmt); - i = vsprintf(buf, fmt, args); + /* A trick: we have at most (size_t)-1 adressable space anyway, so + if we output so much we'll crash anyway. */ + i = vsnprintf(buf, -1, fmt, args); + va_end(args); + + return i; +} + +int snprintf(char *buf, size_t size, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = vsnprintf(buf, size, fmt, args); va_end(args); return i; diff --git a/src/include/string.h b/src/include/string.h index 77985e1..dc125e1 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -17,6 +17,7 @@ int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); +int snprintf(char * buf, size_t size, const char *fmt, ...); #endif // simple string functions

1 0

Patch set updated for coreboot: 2b9a686 Remove sprintf
by Vladimir Serbinenko 24 Dec '13

24 Dec '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4280 -gerrit commit 2b9a686cbd51f64b30125bc74e5688e71a84928b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:42:52 2013 +0100 Remove sprintf Remove sprintf as if you can't easily use snprintf then you probably have buffer overflow. Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/console/vsprintf.c | 14 -------------- src/include/string.h | 1 - 2 files changed, 15 deletions(-) diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index b1b6d47..1fb834f 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -57,20 +57,6 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) return i; } -int sprintf(char *buf, const char *fmt, ...) -{ - va_list args; - int i; - - va_start(args, fmt); - /* A trick: we have at most (size_t)-1 adressable space anyway, so - if we output so much we'll crash anyway. */ - i = vsnprintf(buf, -1, fmt, args); - va_end(args); - - return i; -} - int snprintf(char *buf, size_t size, const char *fmt, ...) { va_list args; diff --git a/src/include/string.h b/src/include/string.h index dc125e1..b4d0268 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -16,7 +16,6 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) -int sprintf(char * buf, const char *fmt, ...); int snprintf(char * buf, size_t size, const char *fmt, ...); #endif

1 0

Patch set updated for coreboot: 8f1d393 cpu/intel: Remove dummy terminators from microcode blobs
by Alexandru Gagniuc 24 Dec '13

24 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4506 -gerrit commit 8f1d39395ac7dc09c0767bba2f7b100d9d9bdd87 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 8 16:41:18 2013 -0600 cpu/intel: Remove dummy terminators from microcode blobs Now that CBFS microcode no longer requires a NULL termination, remove the dummy terminators from all microcode blobs. This also enables microcode blobs from different CPU models to be linked in the same cpu_microcode_blob.bin without the terminators getting in the way. Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/intel/ep80579/microcode_blob.c | 5 ----- src/cpu/intel/haswell/microcode_blob.h | 5 ----- src/cpu/intel/model_1067x/microcode_blob.c | 6 ------ src/cpu/intel/model_106cx/microcode_blob.c | 6 ------ src/cpu/intel/model_2065x/microcode_blob.h | 6 ------ src/cpu/intel/model_206ax/microcode_blob.h | 6 ------ src/cpu/intel/model_65x/microcode_blob.c | 6 ------ src/cpu/intel/model_67x/microcode_blob.c | 5 ----- src/cpu/intel/model_68x/microcode_blob.c | 5 ----- src/cpu/intel/model_69x/microcode_blob.c | 6 ------ src/cpu/intel/model_6bx/microcode_blob.c | 5 ----- src/cpu/intel/model_6dx/microcode_blob.c | 6 ------ src/cpu/intel/model_6ex/microcode_blob.c | 5 ----- src/cpu/intel/model_6fx/microcode_blob.c | 6 ------ src/cpu/intel/model_6xx/microcode_blob.c | 11 ----------- src/cpu/intel/model_f0x/microcode_blob.c | 6 ------ src/cpu/intel/model_f1x/microcode_blob.c | 10 ---------- src/cpu/intel/model_f2x/microcode_blob.c | 11 ----------- src/cpu/intel/model_f3x/microcode_blob.c | 11 ----------- src/cpu/intel/model_f4x/microcode_blob.c | 11 ----------- 20 files changed, 138 deletions(-) diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c index cb95b1a..689f59e 100644 --- a/src/cpu/intel/ep80579/microcode_blob.c +++ b/src/cpu/intel/ep80579/microcode_blob.c @@ -5,9 +5,4 @@ * coreboot.rom image. */ unsigned microcode_updates_ep80579[] = { - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index 5776154..c616f80 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -26,8 +26,3 @@ #include "microcode-M32306c3_00000012.h" #include "microcode-M3240660_ffff000b.h" #endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c index 3b22e70..1a626c1 100644 --- a/src/cpu/intel/model_1067x/microcode_blob.c +++ b/src/cpu/intel/model_1067x/microcode_blob.c @@ -8,10 +8,4 @@ unsigned microcode_updates_1067ax[] = { #include "microcode-m441067AA0B.h" #include "microcode-m801067660F.h" #include "microcode-mA01067AA0B.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c index 573d41f..1ca4cdc 100644 --- a/src/cpu/intel/model_106cx/microcode_blob.c +++ b/src/cpu/intel/model_106cx/microcode_blob.c @@ -6,10 +6,4 @@ unsigned microcode_updates_106cx[] = { #include "microcode-M08106C2219.h" #include "microcode-M08106CA107.h" #include "microcode-M10106CA107.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_2065x/microcode_blob.h b/src/cpu/intel/model_2065x/microcode_blob.h index 1da40d9..7aa6fdf 100644 --- a/src/cpu/intel/model_2065x/microcode_blob.h +++ b/src/cpu/intel/model_2065x/microcode_blob.h @@ -18,9 +18,3 @@ */ #include "microcode-m9220655_00000003.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_206ax/microcode_blob.h b/src/cpu/intel/model_206ax/microcode_blob.h index 10865ab..9b8d4af 100644 --- a/src/cpu/intel/model_206ax/microcode_blob.h +++ b/src/cpu/intel/model_206ax/microcode_blob.h @@ -19,9 +19,3 @@ #include "microcode-m12206a7_00000028.h" #include "microcode-m12306a9_00000017.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c index f14f317..ff3d87e 100644 --- a/src/cpu/intel/model_65x/microcode_blob.c +++ b/src/cpu/intel/model_65x/microcode_blob.c @@ -16,10 +16,4 @@ unsigned microcode_updates_65x[] = { #include "microcode-429-MU165040.h" #include "microcode-436-MU165142.h" #include "microcode-411-MU16530c.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c index 7840484..55d0112 100644 --- a/src/cpu/intel/model_67x/microcode_blob.c +++ b/src/cpu/intel/model_67x/microcode_blob.c @@ -5,9 +5,4 @@ unsigned microcode_updates_67x[] = { #include "microcode-531-MU26732e.h" #include "microcode-539-MU167210.h" #include "microcode-540-MU267238.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c index 78e2e03..686a768 100644 --- a/src/cpu/intel/model_68x/microcode_blob.c +++ b/src/cpu/intel/model_68x/microcode_blob.c @@ -17,9 +17,4 @@ unsigned microcode_updates_68x[] = { #include "microcode-662-MU168a01.h" #include "microcode-691-MU168a04.h" #include "microcode-692-MU168a05.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c index 4b06772..d6beb0f 100644 --- a/src/cpu/intel/model_69x/microcode_blob.c +++ b/src/cpu/intel/model_69x/microcode_blob.c @@ -2,10 +2,4 @@ unsigned microcode_updates_69x[] = { #include "microcode-1376-m8069547.h" #include "microcode-1373-m1069507.h" #include "microcode-1374-m2069507.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c index a6f9bc6..e9a7cb7 100644 --- a/src/cpu/intel/model_6bx/microcode_blob.c +++ b/src/cpu/intel/model_6bx/microcode_blob.c @@ -3,9 +3,4 @@ unsigned microcode_updates_6bx[] = { #include "microcode-738-MU16b11d.h" #include "microcode-875-MU16b401.h" #include "microcode-885-MU16b402.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c index 52489e4..c66eca4 100644 --- a/src/cpu/intel/model_6dx/microcode_blob.c +++ b/src/cpu/intel/model_6dx/microcode_blob.c @@ -1,9 +1,3 @@ unsigned microcode_updates_6dx[] = { #include "microcode-1355-m206d618.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c index 0798316..e934da7 100644 --- a/src/cpu/intel/model_6ex/microcode_blob.c +++ b/src/cpu/intel/model_6ex/microcode_blob.c @@ -2,9 +2,4 @@ unsigned microcode_updates_6ex[] = { #include "microcode-1624-m206e839.h" #include "microcode-1729-m206ec54.h" #include "microcode-1869-m806ec59.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c index f17613b..85bf467 100644 --- a/src/cpu/intel/model_6fx/microcode_blob.c +++ b/src/cpu/intel/model_6fx/microcode_blob.c @@ -17,10 +17,4 @@ unsigned microcode_updates_6fx[] = { #include "microcode-m806fa95.h" #include "microcode-m806fbBA.h" #include "microcode-m806fda4.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c index 8a7ef26..1de815c 100644 --- a/src/cpu/intel/model_6xx/microcode_blob.c +++ b/src/cpu/intel/model_6xx/microcode_blob.c @@ -1,9 +1,4 @@ unsigned microcode_updates_6xx[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - #include "microcode-99-B_c6_612.h" #include "microcode-43-B_c6_617.h" #include "microcode-51-B_c6_616.h" @@ -24,10 +19,4 @@ unsigned microcode_updates_6xx[] = { #include "microcode-566-mu26a003.h" #include "microcode-588-mu26a101.h" #include "microcode-620-MU26a401.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c index 079a2cb..314b024 100644 --- a/src/cpu/intel/model_f0x/microcode_blob.c +++ b/src/cpu/intel/model_f0x/microcode_blob.c @@ -5,10 +5,4 @@ unsigned microcode_updates_f0x[] = { #include "microcode-983-m02f0a15.h" #include "microcode-964-m01f0712.h" #include "microcode-966-m04f0a14.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c index 308402c..6adcc41 100644 --- a/src/cpu/intel/model_f1x/microcode_blob.c +++ b/src/cpu/intel/model_f1x/microcode_blob.c @@ -1,17 +1,7 @@ /* 256KB cache */ unsigned microcode_updates_f1x[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ #include "microcode-1068-m01f122d.h" #include "microcode-1069-m04f122e.h" #include "microcode-1070-m02f122f.h" #include "microcode-1072-m04f1305.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c index e8c9302..e9ee147 100644 --- a/src/cpu/intel/model_f2x/microcode_blob.c +++ b/src/cpu/intel/model_f2x/microcode_blob.c @@ -1,10 +1,5 @@ /* 512KB cache */ unsigned microcode_updates_f2x[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - /* Old microcode file not present in Intel's microcode.dat. */ #include "microcode_m02f2203.h" @@ -24,10 +19,4 @@ unsigned microcode_updates_f2x[] = { #include "microcode-1104-m04f241e.h" #include "microcode-1342-m02f252a.h" #include "microcode-1106-m02f241f.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c index 0bd2a5b..2847f75 100644 --- a/src/cpu/intel/model_f3x/microcode_blob.c +++ b/src/cpu/intel/model_f3x/microcode_blob.c @@ -1,16 +1,5 @@ unsigned microcode_updates_f3x[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - #include "microcode-1290-m0df320a.h" #include "microcode-1467-m0df330c.h" #include "microcode-1468-m1df3417.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c index 4f1147c..dd5e3fa 100644 --- a/src/cpu/intel/model_f4x/microcode_blob.c +++ b/src/cpu/intel/model_f4x/microcode_blob.c @@ -1,9 +1,4 @@ unsigned microcode_updates_f4x[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - #include "microcode-1735-m01f480c.h" #include "microcode-1460-m9df4305.h" #include "microcode-2492-m02f480e.h" @@ -15,10 +10,4 @@ unsigned microcode_updates_f4x[] = { #include "microcode-1637-m5cf4a04.h" #include "microcode-1462-mbdf4903.h" #include "microcode-1498-m5df4a02.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, };

1 0

Patch set updated for coreboot: fc8acc1 cpu/intel: Make all Intel CPUs load microcode from CBFS
by Alexandru Gagniuc 24 Dec '13

24 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4495 -gerrit commit fc8acc1bb39a38b1986cc19c49eaac7df598073b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 6 23:14:54 2013 -0600 cpu/intel: Make all Intel CPUs load microcode from CBFS The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/intel/ep80579/Kconfig | 1 + src/cpu/intel/ep80579/Makefile.inc | 1 + src/cpu/intel/ep80579/ep80579_init.c | 10 +-- src/cpu/intel/ep80579/microcode_blob.c | 13 ++++ src/cpu/intel/microcode/Makefile.inc | 2 +- src/cpu/intel/microcode/microcode.c | 96 ++-------------------------- src/cpu/intel/model_1067x/Kconfig | 1 + src/cpu/intel/model_1067x/Makefile.inc | 1 + src/cpu/intel/model_1067x/microcode_blob.c | 17 +++++ src/cpu/intel/model_1067x/model_1067x_init.c | 20 +----- src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/intel/model_106cx/Makefile.inc | 1 + src/cpu/intel/model_106cx/microcode_blob.c | 15 +++++ src/cpu/intel/model_106cx/model_106cx_init.c | 18 +----- src/cpu/intel/model_65x/Kconfig | 1 + src/cpu/intel/model_65x/Makefile.inc | 1 + src/cpu/intel/model_65x/microcode_blob.c | 25 ++++++++ src/cpu/intel/model_65x/model_65x_init.c | 29 +-------- src/cpu/intel/model_67x/Kconfig | 1 + src/cpu/intel/model_67x/Makefile.inc | 1 + src/cpu/intel/model_67x/microcode_blob.c | 13 ++++ src/cpu/intel/model_67x/model_67x_init.c | 16 +---- src/cpu/intel/model_68x/Kconfig | 1 + src/cpu/intel/model_68x/Makefile.inc | 1 + src/cpu/intel/model_68x/microcode_blob.c | 25 ++++++++ src/cpu/intel/model_68x/model_68x_init.c | 28 +------- src/cpu/intel/model_69x/Kconfig | 1 + src/cpu/intel/model_69x/Makefile.inc | 2 + src/cpu/intel/model_69x/microcode_blob.c | 11 ++++ src/cpu/intel/model_69x/model_69x_init.c | 14 +--- src/cpu/intel/model_6bx/Kconfig | 1 + src/cpu/intel/model_6bx/Makefile.inc | 2 + src/cpu/intel/model_6bx/microcode_blob.c | 11 ++++ src/cpu/intel/model_6bx/model_6bx_init.c | 14 +--- src/cpu/intel/model_6dx/Kconfig | 1 + src/cpu/intel/model_6dx/Makefile.inc | 2 + src/cpu/intel/model_6dx/microcode_blob.c | 9 +++ src/cpu/intel/model_6dx/model_6dx_init.c | 12 +--- src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6ex/Makefile.inc | 1 + src/cpu/intel/model_6ex/microcode_blob.c | 10 +++ src/cpu/intel/model_6ex/model_6ex_init.c | 12 +--- src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/intel/model_6fx/Makefile.inc | 2 + src/cpu/intel/model_6fx/microcode_blob.c | 26 ++++++++ src/cpu/intel/model_6fx/model_6fx_init.c | 29 +-------- src/cpu/intel/model_6xx/Kconfig | 1 + src/cpu/intel/model_6xx/Makefile.inc | 2 + src/cpu/intel/model_6xx/microcode_blob.c | 33 ++++++++++ src/cpu/intel/model_6xx/model_6xx_init.c | 36 +---------- src/cpu/intel/model_f0x/Kconfig | 1 + src/cpu/intel/model_f0x/Makefile.inc | 2 + src/cpu/intel/model_f0x/microcode_blob.c | 14 ++++ src/cpu/intel/model_f0x/model_f0x_init.c | 17 +---- src/cpu/intel/model_f1x/Kconfig | 1 + src/cpu/intel/model_f1x/Makefile.inc | 2 + src/cpu/intel/model_f1x/microcode_blob.c | 17 +++++ src/cpu/intel/model_f1x/model_f1x_init.c | 20 +----- src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/intel/model_f2x/Makefile.inc | 2 + src/cpu/intel/model_f2x/microcode_blob.c | 33 ++++++++++ src/cpu/intel/model_f2x/model_f2x_init.c | 36 +---------- src/cpu/intel/model_f3x/Kconfig | 1 + src/cpu/intel/model_f3x/Makefile.inc | 2 + src/cpu/intel/model_f3x/microcode_blob.c | 16 +++++ src/cpu/intel/model_f3x/model_f3x_init.c | 19 +----- src/cpu/intel/model_f4x/Kconfig | 1 + src/cpu/intel/model_f4x/Makefile.inc | 2 + src/cpu/intel/model_f4x/microcode_blob.c | 24 +++++++ src/cpu/intel/model_f4x/model_f4x_init.c | 27 +------- src/cpu/intel/slot_1/Kconfig | 12 +++- src/cpu/intel/socket_PGA370/Kconfig | 1 + src/include/cpu/intel/microcode.h | 4 -- 73 files changed, 390 insertions(+), 438 deletions(-) diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 025ad3f..380869a 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_EP80579 bool select SSE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc index 080e2ee..b213c08 100644 --- a/src/cpu/intel/ep80579/Makefile.inc +++ b/src/cpu/intel/ep80579/Makefile.inc @@ -7,3 +7,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index b1c1e22..22166b1 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -29,14 +29,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -static u32 microcode_updates[] = { - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void ep80579_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -45,7 +37,7 @@ static void ep80579_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c new file mode 100644 index 0000000..cb95b1a --- /dev/null +++ b/src/cpu/intel/ep80579/microcode_blob.c @@ -0,0 +1,13 @@ +/* + * We support updating microcode from CBFS, but do not have any microcode + * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in + * CBFS, but this file can be later replaced without needing to recompile the + * coreboot.rom image. + */ +unsigned microcode_updates_ep80579[] = { + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 22655c9..1feb504 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -2,4 +2,4 @@ ## One small file with the awesome super-power of updating the cpu microcode ## directly from CBFS. You have been WARNED!!! ################################################################################ -ramstage-y += microcode.c \ No newline at end of file +ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 83a4126..c823eb8 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -29,16 +29,12 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#ifdef __PRE_RAM__ -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS -#include <arch/cbfs.h> -#endif -#else -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS +#if !defined(__PRE_RAM__) #include <cbfs.h> -#endif #include <smp/spinlock.h> DECLARE_SPIN_LOCK(microcode_lock) +#else +#include <arch/cbfs.h> #endif struct microcode { @@ -82,8 +78,6 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS - #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_microcode_load_unlocked(const void *microcode_patch) @@ -168,7 +162,7 @@ const void *intel_microcode_find(void) update_size = m->total_size; } else { #if !defined(__ROMCC__) - printk(BIOS_WARNING, "Microcode has no valid size field!\n"); + printk(BIOS_SPEW, "Microcode size field is 0\n"); #endif update_size = 2048; } @@ -206,85 +200,3 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } - -#else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */ - -void intel_update_microcode(const void *microcode_updates) -{ - u32 eax; - u32 pf, rev, sig; - unsigned int x86_model, x86_family; - const struct microcode *m; - const char *c; - msr_t msr; - - if (!microcode_updates) { -#if !defined(__ROMCC__) - printk(BIOS_WARNING, "No microcode updates found.\n"); -#endif - return; - } - - /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ - msr.lo = 0; - msr.hi = 0; - wrmsr(0x8B, msr); - eax = cpuid_eax(1); - msr = rdmsr(0x8B); - rev = msr.hi; - x86_model = (eax >>4) & 0x0f; - x86_family = (eax >>8) & 0x0f; - sig = eax; - - pf = 0; - if ((x86_model >= 5)||(x86_family>6)) { - msr = rdmsr(0x17); - pf = 1 << ((msr.hi >> 18) & 7); - } -#if !defined(__ROMCC__) - /* If this code is compiled with ROMCC we're probably in - * the bootblock and don't have console output yet. - */ - printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n", - sig, pf, rev); -#endif -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) - spin_lock(&microcode_lock); -#endif - - m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { - if ((m->sig == sig) && (m->pf & pf)) { - unsigned int new_rev; - msr.lo = (unsigned long)c + sizeof(struct microcode); - msr.hi = 0; - wrmsr(0x79, msr); - - /* Read back the new microcode version */ - new_rev = read_microcode_rev(); - -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "microcode: updated to revision " - "0x%x date=%04x-%02x-%02x\n", new_rev, - m->date & 0xffff, (m->date >> 24) & 0xff, - (m->date >> 16) & 0xff); -#endif - break; - } - - if (m->total_size) { - c += m->total_size; - } else { -#if !defined(__ROMCC__) - printk(BIOS_WARNING, "Microcode has no valid size field!\n"); -#endif - c += 2048; - } - } - -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) - spin_unlock(&microcode_lock); -#endif -} - -#endif diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 852c9cd..7d5bf94 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_1067X select SMP select SSE2 select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index c0e98bc..ccfeb7f 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_1067x_init.c subdirs-y += ../../x86/name +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c new file mode 100644 index 0000000..3b22e70 --- /dev/null +++ b/src/cpu/intel/model_1067x/microcode_blob.c @@ -0,0 +1,17 @@ +unsigned microcode_updates_1067ax[] = { + #include "microcode-m011067660F.h" + #include "microcode-m041067660F.h" + #include "microcode-m101067660F.h" + #include "microcode-m101067770A.h" + #include "microcode-m111067AA0B.h" + #include "microcode-m401067660F.h" + #include "microcode-m441067AA0B.h" + #include "microcode-m801067660F.h" + #include "microcode-mA01067AA0B.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 47d87de..2b151a3 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -36,24 +36,6 @@ #include "chip.h" -static const uint32_t microcode_updates[] = { - #include "microcode-m011067660F.h" - #include "microcode-m041067660F.h" - #include "microcode-m101067660F.h" - #include "microcode-m101067770A.h" - #include "microcode-m111067AA0B.h" - #include "microcode-m401067660F.h" - #include "microcode-m441067AA0B.h" - #include "microcode-m801067660F.h" - #include "microcode-mA01067AA0B.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void init_timer(void) { /* Set the apic timer to no interrupts and periodic mode */ @@ -335,7 +317,7 @@ static void model_1067x_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index e26bf1f..c438008 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,6 +6,7 @@ config CPU_INTEL_MODEL_106CX select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS config CPU_ADDR_BITS int diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 1f217fe..dbc093d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c new file mode 100644 index 0000000..573d41f --- /dev/null +++ b/src/cpu/intel/model_106cx/microcode_blob.c @@ -0,0 +1,15 @@ +unsigned microcode_updates_106cx[] = { + #include "microcode-M01106C2217.h" + #include "microcode-M01106CA107.h" + #include "microcode-M04106C2218.h" + #include "microcode-M04106CA107.h" + #include "microcode-M08106C2219.h" + #include "microcode-M08106CA107.h" + #include "microcode-M10106CA107.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e0aa120..0d96172 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -31,22 +31,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-M01106C2217.h" - #include "microcode-M01106CA107.h" - #include "microcode-M04106C2218.h" - #include "microcode-M04106CA107.h" - #include "microcode-M08106C2219.h" - #include "microcode-M08106CA107.h" - #include "microcode-M10106CA107.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - #define IA32_FEATURE_CONTROL 0x003a #define CPUID_VMX (1 << 5) @@ -135,7 +119,7 @@ static void model_106cx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 1ef4813..e8f0767 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_65X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index 50639e7..9298037 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += model_65x_init.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c new file mode 100644 index 0000000..f14f317 --- /dev/null +++ b/src/cpu/intel/model_65x/microcode_blob.c @@ -0,0 +1,25 @@ +unsigned microcode_updates_65x[] = { + #include "microcode-410-MU16522d.h" + #include "microcode-422-MU26530b.h" + #include "microcode-412-MU16530d.h" + #include "microcode-423-MU26522b.h" + #include "microcode-407-MU16522a.h" + #include "microcode-146-MU16502e.h" + #include "microcode-409-MU16522c.h" + #include "microcode-147-MU16502f.h" + #include "microcode-94-MU265019.h" + #include "microcode-430-MU165041.h" + #include "microcode-452-MU165310.h" + #include "microcode-434-MU165140.h" + #include "microcode-435-MU165141.h" + #include "microcode-433-MU165045.h" + #include "microcode-429-MU165040.h" + #include "microcode-436-MU165142.h" + #include "microcode-411-MU16530c.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 285bacd..6914122 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -29,37 +29,10 @@ #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> -static u32 microcode_updates[] = { - #include "microcode-410-MU16522d.h" - #include "microcode-422-MU26530b.h" - #include "microcode-412-MU16530d.h" - #include "microcode-423-MU26522b.h" - #include "microcode-407-MU16522a.h" - #include "microcode-146-MU16502e.h" - #include "microcode-409-MU16522c.h" - #include "microcode-147-MU16502f.h" - #include "microcode-94-MU265019.h" - #include "microcode-430-MU165041.h" - #include "microcode-452-MU165310.h" - #include "microcode-434-MU165140.h" - #include "microcode-435-MU165141.h" - #include "microcode-433-MU165045.h" - #include "microcode-429-MU165040.h" - #include "microcode-436-MU165142.h" - #include "microcode-411-MU16530c.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_65x_init(device_t dev) { /* Update the microcode */ - intel_update_microcode(microcode_updates); - + intel_update_microcode_from_cbfs(); /* Initialize L2 cache */ p6_configure_l2_cache(); diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index b65081c..74ef8d5 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_67X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index 48cfc15..04970b0 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += model_67x_init.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c new file mode 100644 index 0000000..7840484 --- /dev/null +++ b/src/cpu/intel/model_67x/microcode_blob.c @@ -0,0 +1,13 @@ +unsigned microcode_updates_67x[] = { + /* Include microcode updates here. */ + #include "microcode-293-MU267114.h" + #include "microcode-530-MU16730e.h" + #include "microcode-531-MU26732e.h" + #include "microcode-539-MU167210.h" + #include "microcode-540-MU267238.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 3ebe361..467d3db 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -29,24 +29,10 @@ #include <cpu/x86/msr.h> #include <cpu/intel/l2_cache.h> -static const uint32_t microcode_updates[] = { - /* Include microcode updates here. */ - #include "microcode-293-MU267114.h" - #include "microcode-530-MU16730e.h" - #include "microcode-531-MU26732e.h" - #include "microcode-539-MU167210.h" - #include "microcode-540-MU267238.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_67x_init(device_t cpu) { /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Initialize L2 cache */ p6_configure_l2_cache(); diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index f7f05f6..9d9983e 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -21,3 +21,4 @@ config CPU_INTEL_MODEL_68X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 40bdd43..addee29 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -21,3 +21,4 @@ ramstage-y += model_68x_init.c subdirs-y += ../../x86/name +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c new file mode 100644 index 0000000..78e2e03 --- /dev/null +++ b/src/cpu/intel/model_68x/microcode_blob.c @@ -0,0 +1,25 @@ +unsigned microcode_updates_68x[] = { + #include "microcode-534-MU16810d.h" + #include "microcode-535-MU16810e.h" + #include "microcode-536-MU16810f.h" + #include "microcode-537-MU268110.h" + #include "microcode-538-MU168111.h" + #include "microcode-550-MU168307.h" + #include "microcode-551-MU168308.h" + #include "microcode-727-MU168313.h" + #include "microcode-728-MU168314.h" + #include "microcode-729-MU268310.h" + #include "microcode-611-MU168607.h" + #include "microcode-612-MU168608.h" + #include "microcode-615-MU16860a.h" + #include "microcode-617-MU16860c.h" + #include "microcode-618-MU268602.h" + #include "microcode-662-MU168a01.h" + #include "microcode-691-MU168a04.h" + #include "microcode-692-MU168a05.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index c4bd7ac..4bb9b56 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -32,32 +32,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-534-MU16810d.h" - #include "microcode-535-MU16810e.h" - #include "microcode-536-MU16810f.h" - #include "microcode-537-MU268110.h" - #include "microcode-538-MU168111.h" - #include "microcode-550-MU168307.h" - #include "microcode-551-MU168308.h" - #include "microcode-727-MU168313.h" - #include "microcode-728-MU168314.h" - #include "microcode-729-MU268310.h" - #include "microcode-611-MU168607.h" - #include "microcode-612-MU168608.h" - #include "microcode-615-MU16860a.h" - #include "microcode-617-MU16860c.h" - #include "microcode-618-MU268602.h" - #include "microcode-662-MU168a01.h" - #include "microcode-691-MU168a04.h" - #include "microcode-692-MU168a05.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_68x_init(device_t cpu) { char processor_name[49]; @@ -66,7 +40,7 @@ static void model_68x_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig index 596763c..4e88979 100644 --- a/src/cpu/intel/model_69x/Kconfig +++ b/src/cpu/intel/model_69x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_69X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc index 927bfeb..e9d90ca 100644 --- a/src/cpu/intel/model_69x/Makefile.inc +++ b/src/cpu/intel/model_69x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_69x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c new file mode 100644 index 0000000..4b06772 --- /dev/null +++ b/src/cpu/intel/model_69x/microcode_blob.c @@ -0,0 +1,11 @@ +unsigned microcode_updates_69x[] = { + #include "microcode-1376-m8069547.h" + #include "microcode-1373-m1069507.h" + #include "microcode-1374-m2069507.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index cb805ae..9ee7424 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -9,18 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - #include "microcode-1376-m8069547.h" - #include "microcode-1373-m1069507.h" - #include "microcode-1374-m2069507.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_69x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -29,7 +17,7 @@ static void model_69x_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 10661d0..26b5995 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6BX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 2d33f85..5f1f894 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c new file mode 100644 index 0000000..a6f9bc6 --- /dev/null +++ b/src/cpu/intel/model_6bx/microcode_blob.c @@ -0,0 +1,11 @@ +unsigned microcode_updates_6bx[] = { + #include "microcode-737-MU16b11c.h" + #include "microcode-738-MU16b11d.h" + #include "microcode-875-MU16b401.h" + #include "microcode-885-MU16b402.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b7affd9..e06665a 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -32,18 +32,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-737-MU16b11c.h" - #include "microcode-738-MU16b11d.h" - #include "microcode-875-MU16b401.h" - #include "microcode-885-MU16b402.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6bx_init(device_t cpu) { char processor_name[49]; @@ -52,7 +40,7 @@ static void model_6bx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig index 5e70f59..546d9ec 100644 --- a/src/cpu/intel/model_6dx/Kconfig +++ b/src/cpu/intel/model_6dx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6DX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc index cc88a2c..4731de3 100644 --- a/src/cpu/intel/model_6dx/Makefile.inc +++ b/src/cpu/intel/model_6dx/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_6dx_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c new file mode 100644 index 0000000..52489e4 --- /dev/null +++ b/src/cpu/intel/model_6dx/microcode_blob.c @@ -0,0 +1,9 @@ +unsigned microcode_updates_6dx[] = { + #include "microcode-1355-m206d618.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 19b351d..06236a3 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -9,16 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - #include "microcode-1355-m206d618.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6dx_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -27,7 +17,7 @@ static void model_6dx_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index e2b1986..8187838 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6EX select UDELAY_LAPIC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index b515c4f..6d94302 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c new file mode 100644 index 0000000..0798316 --- /dev/null +++ b/src/cpu/intel/model_6ex/microcode_blob.c @@ -0,0 +1,10 @@ +unsigned microcode_updates_6ex[] = { + #include "microcode-1624-m206e839.h" + #include "microcode-1729-m206ec54.h" + #include "microcode-1869-m806ec59.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index e9c63da..4dc642a 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -33,16 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-1624-m206e839.h" - #include "microcode-1729-m206ec54.h" - #include "microcode-1869-m806ec59.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; #define IA32_FEATURE_CONTROL 0x003a @@ -160,7 +150,7 @@ static void model_6ex_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 4517f17..3335a26 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6FX select UDELAY_LAPIC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index b75cde3..6a1bb51 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c new file mode 100644 index 0000000..f17613b --- /dev/null +++ b/src/cpu/intel/model_6fx/microcode_blob.c @@ -0,0 +1,26 @@ +unsigned microcode_updates_6fx[] = { + #include "microcode-m016fbBA.h" + #include "microcode-m046fbBC.h" + #include "microcode-m086fbBB.h" + #include "microcode-m106f76a.h" + #include "microcode-m106fbBA.h" + #include "microcode-m16f25d.h" + #include "microcode-m16f6d0.h" + #include "microcode-m16fda4.h" + #include "microcode-m206f25c.h" + #include "microcode-m206f6d1.h" + #include "microcode-m206fbBA.h" + #include "microcode-m206fda4.h" + #include "microcode-m406f76b.h" + #include "microcode-m406fbBC.h" + #include "microcode-m46f6d2.h" + #include "microcode-m806fa95.h" + #include "microcode-m806fbBA.h" + #include "microcode-m806fda4.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index faf1277..39aa8e9 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -33,33 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-m016fbBA.h" - #include "microcode-m046fbBC.h" - #include "microcode-m086fbBB.h" - #include "microcode-m106f76a.h" - #include "microcode-m106fbBA.h" - #include "microcode-m16f25d.h" - #include "microcode-m16f6d0.h" - #include "microcode-m16fda4.h" - #include "microcode-m206f25c.h" - #include "microcode-m206f6d1.h" - #include "microcode-m206fbBA.h" - #include "microcode-m206fda4.h" - #include "microcode-m406f76b.h" - #include "microcode-m406fbBC.h" - #include "microcode-m46f6d2.h" - #include "microcode-m806fa95.h" - #include "microcode-m806fbBA.h" - #include "microcode-m806fda4.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - #define IA32_FEATURE_CONTROL 0x003a #define CPUID_VMX (1 << 5) @@ -197,7 +170,7 @@ static void model_6fx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index 96c7040..b572385 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6XX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 5fdd71c..0c41cf2 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_6xx_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c new file mode 100644 index 0000000..8a7ef26 --- /dev/null +++ b/src/cpu/intel/model_6xx/microcode_blob.c @@ -0,0 +1,33 @@ +unsigned microcode_updates_6xx[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + +#include "microcode-99-B_c6_612.h" +#include "microcode-43-B_c6_617.h" +#include "microcode-51-B_c6_616.h" +#include "microcode-153-d2_619.h" + +#include "microcode-308-MU163336.h" +#include "microcode-309-MU163437.h" + +#include "microcode-358-MU166d05.h" +#include "microcode-359-MU166d06.h" +#include "microcode-386-MU16600a.h" +#include "microcode-398-MU166503.h" +#include "microcode-399-MU166a0b.h" +#include "microcode-400-MU166a0c.h" +#include "microcode-401-MU166a0d.h" +#include "microcode-402-MU166d07.h" + +#include "microcode-566-mu26a003.h" +#include "microcode-588-mu26a101.h" +#include "microcode-620-MU26a401.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 5724add..e81f9ae 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -9,40 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - -#include "microcode-99-B_c6_612.h" -#include "microcode-43-B_c6_617.h" -#include "microcode-51-B_c6_616.h" -#include "microcode-153-d2_619.h" - -#include "microcode-308-MU163336.h" -#include "microcode-309-MU163437.h" - -#include "microcode-358-MU166d05.h" -#include "microcode-359-MU166d06.h" -#include "microcode-386-MU16600a.h" -#include "microcode-398-MU166503.h" -#include "microcode-399-MU166a0b.h" -#include "microcode-400-MU166a0c.h" -#include "microcode-401-MU166a0d.h" -#include "microcode-402-MU166d07.h" - -#include "microcode-566-mu26a003.h" -#include "microcode-588-mu26a101.h" -#include "microcode-620-MU26a401.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6xx_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -51,7 +17,7 @@ static void model_6xx_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig index 9dd7fd0..0616589 100644 --- a/src/cpu/intel/model_f0x/Kconfig +++ b/src/cpu/intel/model_f0x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F0X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc index 79ea2a0..6c16419 100644 --- a/src/cpu/intel/model_f0x/Makefile.inc +++ b/src/cpu/intel/model_f0x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f0x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c new file mode 100644 index 0000000..079a2cb --- /dev/null +++ b/src/cpu/intel/model_f0x/microcode_blob.c @@ -0,0 +1,14 @@ +/* 256KB cache */ +unsigned microcode_updates_f0x[] = { + #include "microcode-678-2f0708.h" + #include "microcode-965-m01f0a13.h" + #include "microcode-983-m02f0a15.h" + #include "microcode-964-m01f0712.h" + #include "microcode-966-m04f0a14.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ed12b6e..8d81182 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -9,21 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -/* 256KB cache */ -static uint32_t microcode_updates[] = { - #include "microcode-678-2f0708.h" - #include "microcode-965-m01f0a13.h" - #include "microcode-983-m02f0a15.h" - #include "microcode-964-m01f0712.h" - #include "microcode-966-m04f0a14.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f0x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -32,7 +17,7 @@ static void model_f0x_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig index ea75857..fd64920 100644 --- a/src/cpu/intel/model_f1x/Kconfig +++ b/src/cpu/intel/model_f1x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F1X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc index 6449ae9..c706234 100644 --- a/src/cpu/intel/model_f1x/Makefile.inc +++ b/src/cpu/intel/model_f1x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f1x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c new file mode 100644 index 0000000..308402c --- /dev/null +++ b/src/cpu/intel/model_f1x/microcode_blob.c @@ -0,0 +1,17 @@ +/* 256KB cache */ +unsigned microcode_updates_f1x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + #include "microcode-1068-m01f122d.h" + #include "microcode-1069-m04f122e.h" + #include "microcode-1070-m02f122f.h" + #include "microcode-1072-m04f1305.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index feb8410..b294c61 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -9,24 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -/* 256KB cache */ -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - #include "microcode-1068-m01f122d.h" - #include "microcode-1069-m04f122e.h" - #include "microcode-1070-m02f122f.h" - #include "microcode-1072-m04f1305.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f1x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -35,7 +17,7 @@ static void model_f1x_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 50cac79..8483d33 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F2X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 9b366d6..3360611 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f2x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c new file mode 100644 index 0000000..e8c9302 --- /dev/null +++ b/src/cpu/intel/model_f2x/microcode_blob.c @@ -0,0 +1,33 @@ +/* 512KB cache */ +unsigned microcode_updates_f2x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + + /* Old microcode file not present in Intel's microcode.dat. */ +#include "microcode_m02f2203.h" + + /* files from Intel's microcode.dat */ +#include "microcode-1343-m04f252b.h" +#include "microcode-1346-m10f252c.h" +#include "microcode-1338-m02f292d.h" +#include "microcode-1340-m08f292f.h" +#include "microcode-1107-m10f2421.h" +#include "microcode-1339-m04f292e.h" +#include "microcode-1105-m08f2420.h" +#include "microcode-1336-m02f2610.h" +#include "microcode-1101-m02f2738.h" +#include "microcode-1100-m04f2737.h" +#include "microcode-1341-m01f2529.h" +#include "microcode-1102-m08f2739.h" +#include "microcode-1104-m04f241e.h" +#include "microcode-1342-m02f252a.h" +#include "microcode-1106-m02f241f.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 8fd8abc..9e8fbfc 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -10,40 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -/* 512KB cache */ -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - - /* Old microcode file not present in Intel's microcode.dat. */ -#include "microcode_m02f2203.h" - - /* files from Intel's microcode.dat */ -#include "microcode-1343-m04f252b.h" -#include "microcode-1346-m10f252c.h" -#include "microcode-1338-m02f292d.h" -#include "microcode-1340-m08f292f.h" -#include "microcode-1107-m10f2421.h" -#include "microcode-1339-m04f292e.h" -#include "microcode-1105-m08f2420.h" -#include "microcode-1336-m02f2610.h" -#include "microcode-1101-m02f2738.h" -#include "microcode-1100-m04f2737.h" -#include "microcode-1341-m01f2529.h" -#include "microcode-1102-m08f2739.h" -#include "microcode-1104-m04f241e.h" -#include "microcode-1342-m02f252a.h" -#include "microcode-1106-m02f241f.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f2x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -55,7 +21,7 @@ static void model_f2x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 4cfca83..8ae2dcf 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F3X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index cf8f918..ebd47cf 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f3x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c new file mode 100644 index 0000000..0bd2a5b --- /dev/null +++ b/src/cpu/intel/model_f3x/microcode_blob.c @@ -0,0 +1,16 @@ +unsigned microcode_updates_f3x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + +#include "microcode-1290-m0df320a.h" +#include "microcode-1467-m0df330c.h" +#include "microcode-1468-m1df3417.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 2504ba9..5752347 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -10,23 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - -#include "microcode-1290-m0df320a.h" -#include "microcode-1467-m0df330c.h" -#include "microcode-1468-m1df3417.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -38,7 +21,7 @@ static void model_f3x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 97c909a..c21a274 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F4X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index ac99095..6ade9f3 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f4x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c new file mode 100644 index 0000000..4f1147c --- /dev/null +++ b/src/cpu/intel/model_f4x/microcode_blob.c @@ -0,0 +1,24 @@ +unsigned microcode_updates_f4x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + + #include "microcode-1735-m01f480c.h" + #include "microcode-1460-m9df4305.h" + #include "microcode-2492-m02f480e.h" + #include "microcode-1470-m9df4703.h" + #include "microcode-1521-m5ff4807.h" + #include "microcode-1466-m02f4116.h" + #include "microcode-1469-m9df4406.h" + #include "microcode-1471-mbdf4117.h" + #include "microcode-1637-m5cf4a04.h" + #include "microcode-1462-mbdf4903.h" + #include "microcode-1498-m5df4a02.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index f3f0b2a..80d7dc8 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -10,31 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - - #include "microcode-1735-m01f480c.h" - #include "microcode-1460-m9df4305.h" - #include "microcode-2492-m02f480e.h" - #include "microcode-1470-m9df4703.h" - #include "microcode-1521-m5ff4807.h" - #include "microcode-1466-m02f4116.h" - #include "microcode-1469-m9df4406.h" - #include "microcode-1471-mbdf4117.h" - #include "microcode-1637-m5cf4a04.h" - #include "microcode-1462-mbdf4903.h" - #include "microcode-1498-m5df4a02.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f4x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -46,7 +21,7 @@ static void model_f4x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 92775aa..e3e6fb2 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -19,10 +19,20 @@ config CPU_INTEL_SLOT_1 bool + +if CPU_INTEL_SLOT_1 + +config SLOT_SPECIFIC_OPTIONS # dummy + def_bool y select CACHE_AS_RAM + select CPU_INTEL_MODEL_65X + select CPU_INTEL_MODEL_67X + select CPU_INTEL_MODEL_68X + select CPU_INTEL_MODEL_6BX + select CPU_INTEL_MODEL_6XX config DCACHE_RAM_SIZE hex default 0x01000 - depends on CPU_INTEL_SLOT_1 +endif diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 7ab2933..c8a4b59 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -19,6 +19,7 @@ config CPU_INTEL_SOCKET_PGA370 bool + select CPU_INTEL_MODEL_6XX select MMX select UDELAY_TSC select CACHE_AS_RAM diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 460bafb..3d1c23a 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,6 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); /* Find a microcode that matches the revision and platform family returning * NULL if none found. */ @@ -30,9 +29,6 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); -#else -void intel_update_microcode(const void *microcode_updates); -#endif #endif #endif

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Patch set updated for coreboot: a492a71 cpu/intel: Make all Intel CPUs load microcode from CBFS
by Alexandru Gagniuc 24 Dec '13

24 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4495 -gerrit commit a492a7132b9edc6fe5e207956c49020c3d3dba20 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 6 23:14:54 2013 -0600 cpu/intel: Make all Intel CPUs load microcode from CBFS The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/intel/ep80579/Kconfig | 1 + src/cpu/intel/ep80579/Makefile.inc | 1 + src/cpu/intel/ep80579/ep80579_init.c | 10 +-- src/cpu/intel/ep80579/microcode_blob.c | 13 ++++ src/cpu/intel/microcode/Makefile.inc | 2 +- src/cpu/intel/microcode/microcode.c | 96 ++-------------------------- src/cpu/intel/model_1067x/Kconfig | 1 + src/cpu/intel/model_1067x/Makefile.inc | 1 + src/cpu/intel/model_1067x/microcode_blob.c | 17 +++++ src/cpu/intel/model_1067x/model_1067x_init.c | 20 +----- src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/intel/model_106cx/Makefile.inc | 1 + src/cpu/intel/model_106cx/microcode_blob.c | 15 +++++ src/cpu/intel/model_106cx/model_106cx_init.c | 18 +----- src/cpu/intel/model_65x/Kconfig | 1 + src/cpu/intel/model_65x/Makefile.inc | 1 + src/cpu/intel/model_65x/microcode_blob.c | 25 ++++++++ src/cpu/intel/model_65x/model_65x_init.c | 29 +-------- src/cpu/intel/model_67x/Kconfig | 1 + src/cpu/intel/model_67x/Makefile.inc | 1 + src/cpu/intel/model_67x/microcode_blob.c | 13 ++++ src/cpu/intel/model_67x/model_67x_init.c | 16 +---- src/cpu/intel/model_68x/Kconfig | 1 + src/cpu/intel/model_68x/Makefile.inc | 1 + src/cpu/intel/model_68x/microcode_blob.c | 25 ++++++++ src/cpu/intel/model_68x/model_68x_init.c | 28 +------- src/cpu/intel/model_69x/Kconfig | 1 + src/cpu/intel/model_69x/Makefile.inc | 2 + src/cpu/intel/model_69x/microcode_blob.c | 13 ++++ src/cpu/intel/model_69x/model_69x_init.c | 14 +--- src/cpu/intel/model_6bx/Kconfig | 1 + src/cpu/intel/model_6bx/Makefile.inc | 2 + src/cpu/intel/model_6bx/microcode_blob.c | 11 ++++ src/cpu/intel/model_6bx/model_6bx_init.c | 14 +--- src/cpu/intel/model_6dx/Kconfig | 1 + src/cpu/intel/model_6dx/Makefile.inc | 2 + src/cpu/intel/model_6dx/microcode_blob.c | 9 +++ src/cpu/intel/model_6dx/model_6dx_init.c | 12 +--- src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6ex/Makefile.inc | 1 + src/cpu/intel/model_6ex/microcode_blob.c | 10 +++ src/cpu/intel/model_6ex/model_6ex_init.c | 12 +--- src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/intel/model_6fx/Makefile.inc | 2 + src/cpu/intel/model_6fx/microcode_blob.c | 26 ++++++++ src/cpu/intel/model_6fx/model_6fx_init.c | 29 +-------- src/cpu/intel/model_6xx/Kconfig | 1 + src/cpu/intel/model_6xx/Makefile.inc | 2 + src/cpu/intel/model_6xx/microcode_blob.c | 33 ++++++++++ src/cpu/intel/model_6xx/model_6xx_init.c | 36 +---------- src/cpu/intel/model_f0x/Kconfig | 1 + src/cpu/intel/model_f0x/Makefile.inc | 2 + src/cpu/intel/model_f0x/microcode_blob.c | 14 ++++ src/cpu/intel/model_f0x/model_f0x_init.c | 17 +---- src/cpu/intel/model_f1x/Kconfig | 1 + src/cpu/intel/model_f1x/Makefile.inc | 2 + src/cpu/intel/model_f1x/microcode_blob.c | 17 +++++ src/cpu/intel/model_f1x/model_f1x_init.c | 20 +----- src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/intel/model_f2x/Makefile.inc | 2 + src/cpu/intel/model_f2x/microcode_blob.c | 33 ++++++++++ src/cpu/intel/model_f2x/model_f2x_init.c | 36 +---------- src/cpu/intel/model_f3x/Kconfig | 1 + src/cpu/intel/model_f3x/Makefile.inc | 2 + src/cpu/intel/model_f3x/microcode_blob.c | 16 +++++ src/cpu/intel/model_f3x/model_f3x_init.c | 19 +----- src/cpu/intel/model_f4x/Kconfig | 1 + src/cpu/intel/model_f4x/Makefile.inc | 2 + src/cpu/intel/model_f4x/microcode_blob.c | 24 +++++++ src/cpu/intel/model_f4x/model_f4x_init.c | 27 +------- src/cpu/intel/slot_1/Kconfig | 12 +++- src/cpu/intel/socket_PGA370/Kconfig | 1 + src/include/cpu/intel/microcode.h | 4 -- 73 files changed, 392 insertions(+), 438 deletions(-) diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 025ad3f..380869a 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_EP80579 bool select SSE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc index 080e2ee..b213c08 100644 --- a/src/cpu/intel/ep80579/Makefile.inc +++ b/src/cpu/intel/ep80579/Makefile.inc @@ -7,3 +7,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index b1c1e22..22166b1 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -29,14 +29,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -static u32 microcode_updates[] = { - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void ep80579_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -45,7 +37,7 @@ static void ep80579_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c new file mode 100644 index 0000000..cb95b1a --- /dev/null +++ b/src/cpu/intel/ep80579/microcode_blob.c @@ -0,0 +1,13 @@ +/* + * We support updating microcode from CBFS, but do not have any microcode + * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in + * CBFS, but this file can be later replaced without needing to recompile the + * coreboot.rom image. + */ +unsigned microcode_updates_ep80579[] = { + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 22655c9..1feb504 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -2,4 +2,4 @@ ## One small file with the awesome super-power of updating the cpu microcode ## directly from CBFS. You have been WARNED!!! ################################################################################ -ramstage-y += microcode.c \ No newline at end of file +ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 83a4126..035d5d2 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -29,16 +29,12 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#ifdef __PRE_RAM__ -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS -#include <arch/cbfs.h> -#endif -#else -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS +#if !defined(__PRE_RAM__) #include <cbfs.h> -#endif #include <smp/spinlock.h> DECLARE_SPIN_LOCK(microcode_lock) +#else +#include <arch/cbfs.h> #endif struct microcode { @@ -82,8 +78,6 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS - #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_microcode_load_unlocked(const void *microcode_patch) @@ -168,7 +162,7 @@ const void *intel_microcode_find(void) update_size = m->total_size; } else { #if !defined(__ROMCC__) - printk(BIOS_WARNING, "Microcode has no valid size field!\n"); + printk(BIOS_SPEW, "Microcode has field 'size'=0\n"); #endif update_size = 2048; } @@ -206,85 +200,3 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } - -#else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */ - -void intel_update_microcode(const void *microcode_updates) -{ - u32 eax; - u32 pf, rev, sig; - unsigned int x86_model, x86_family; - const struct microcode *m; - const char *c; - msr_t msr; - - if (!microcode_updates) { -#if !defined(__ROMCC__) - printk(BIOS_WARNING, "No microcode updates found.\n"); -#endif - return; - } - - /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ - msr.lo = 0; - msr.hi = 0; - wrmsr(0x8B, msr); - eax = cpuid_eax(1); - msr = rdmsr(0x8B); - rev = msr.hi; - x86_model = (eax >>4) & 0x0f; - x86_family = (eax >>8) & 0x0f; - sig = eax; - - pf = 0; - if ((x86_model >= 5)||(x86_family>6)) { - msr = rdmsr(0x17); - pf = 1 << ((msr.hi >> 18) & 7); - } -#if !defined(__ROMCC__) - /* If this code is compiled with ROMCC we're probably in - * the bootblock and don't have console output yet. - */ - printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n", - sig, pf, rev); -#endif -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) - spin_lock(&microcode_lock); -#endif - - m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { - if ((m->sig == sig) && (m->pf & pf)) { - unsigned int new_rev; - msr.lo = (unsigned long)c + sizeof(struct microcode); - msr.hi = 0; - wrmsr(0x79, msr); - - /* Read back the new microcode version */ - new_rev = read_microcode_rev(); - -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "microcode: updated to revision " - "0x%x date=%04x-%02x-%02x\n", new_rev, - m->date & 0xffff, (m->date >> 24) & 0xff, - (m->date >> 16) & 0xff); -#endif - break; - } - - if (m->total_size) { - c += m->total_size; - } else { -#if !defined(__ROMCC__) - printk(BIOS_WARNING, "Microcode has no valid size field!\n"); -#endif - c += 2048; - } - } - -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) - spin_unlock(&microcode_lock); -#endif -} - -#endif diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 852c9cd..7d5bf94 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_1067X select SMP select SSE2 select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index c0e98bc..ccfeb7f 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_1067x_init.c subdirs-y += ../../x86/name +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c new file mode 100644 index 0000000..3b22e70 --- /dev/null +++ b/src/cpu/intel/model_1067x/microcode_blob.c @@ -0,0 +1,17 @@ +unsigned microcode_updates_1067ax[] = { + #include "microcode-m011067660F.h" + #include "microcode-m041067660F.h" + #include "microcode-m101067660F.h" + #include "microcode-m101067770A.h" + #include "microcode-m111067AA0B.h" + #include "microcode-m401067660F.h" + #include "microcode-m441067AA0B.h" + #include "microcode-m801067660F.h" + #include "microcode-mA01067AA0B.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 47d87de..2b151a3 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -36,24 +36,6 @@ #include "chip.h" -static const uint32_t microcode_updates[] = { - #include "microcode-m011067660F.h" - #include "microcode-m041067660F.h" - #include "microcode-m101067660F.h" - #include "microcode-m101067770A.h" - #include "microcode-m111067AA0B.h" - #include "microcode-m401067660F.h" - #include "microcode-m441067AA0B.h" - #include "microcode-m801067660F.h" - #include "microcode-mA01067AA0B.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void init_timer(void) { /* Set the apic timer to no interrupts and periodic mode */ @@ -335,7 +317,7 @@ static void model_1067x_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index e26bf1f..c438008 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,6 +6,7 @@ config CPU_INTEL_MODEL_106CX select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS config CPU_ADDR_BITS int diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 1f217fe..dbc093d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c new file mode 100644 index 0000000..573d41f --- /dev/null +++ b/src/cpu/intel/model_106cx/microcode_blob.c @@ -0,0 +1,15 @@ +unsigned microcode_updates_106cx[] = { + #include "microcode-M01106C2217.h" + #include "microcode-M01106CA107.h" + #include "microcode-M04106C2218.h" + #include "microcode-M04106CA107.h" + #include "microcode-M08106C2219.h" + #include "microcode-M08106CA107.h" + #include "microcode-M10106CA107.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e0aa120..0d96172 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -31,22 +31,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-M01106C2217.h" - #include "microcode-M01106CA107.h" - #include "microcode-M04106C2218.h" - #include "microcode-M04106CA107.h" - #include "microcode-M08106C2219.h" - #include "microcode-M08106CA107.h" - #include "microcode-M10106CA107.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - #define IA32_FEATURE_CONTROL 0x003a #define CPUID_VMX (1 << 5) @@ -135,7 +119,7 @@ static void model_106cx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 1ef4813..e8f0767 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_65X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index 50639e7..9298037 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += model_65x_init.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c new file mode 100644 index 0000000..f14f317 --- /dev/null +++ b/src/cpu/intel/model_65x/microcode_blob.c @@ -0,0 +1,25 @@ +unsigned microcode_updates_65x[] = { + #include "microcode-410-MU16522d.h" + #include "microcode-422-MU26530b.h" + #include "microcode-412-MU16530d.h" + #include "microcode-423-MU26522b.h" + #include "microcode-407-MU16522a.h" + #include "microcode-146-MU16502e.h" + #include "microcode-409-MU16522c.h" + #include "microcode-147-MU16502f.h" + #include "microcode-94-MU265019.h" + #include "microcode-430-MU165041.h" + #include "microcode-452-MU165310.h" + #include "microcode-434-MU165140.h" + #include "microcode-435-MU165141.h" + #include "microcode-433-MU165045.h" + #include "microcode-429-MU165040.h" + #include "microcode-436-MU165142.h" + #include "microcode-411-MU16530c.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 285bacd..6914122 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -29,37 +29,10 @@ #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> -static u32 microcode_updates[] = { - #include "microcode-410-MU16522d.h" - #include "microcode-422-MU26530b.h" - #include "microcode-412-MU16530d.h" - #include "microcode-423-MU26522b.h" - #include "microcode-407-MU16522a.h" - #include "microcode-146-MU16502e.h" - #include "microcode-409-MU16522c.h" - #include "microcode-147-MU16502f.h" - #include "microcode-94-MU265019.h" - #include "microcode-430-MU165041.h" - #include "microcode-452-MU165310.h" - #include "microcode-434-MU165140.h" - #include "microcode-435-MU165141.h" - #include "microcode-433-MU165045.h" - #include "microcode-429-MU165040.h" - #include "microcode-436-MU165142.h" - #include "microcode-411-MU16530c.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_65x_init(device_t dev) { /* Update the microcode */ - intel_update_microcode(microcode_updates); - + intel_update_microcode_from_cbfs(); /* Initialize L2 cache */ p6_configure_l2_cache(); diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index b65081c..74ef8d5 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_67X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index 48cfc15..04970b0 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += model_67x_init.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c new file mode 100644 index 0000000..7840484 --- /dev/null +++ b/src/cpu/intel/model_67x/microcode_blob.c @@ -0,0 +1,13 @@ +unsigned microcode_updates_67x[] = { + /* Include microcode updates here. */ + #include "microcode-293-MU267114.h" + #include "microcode-530-MU16730e.h" + #include "microcode-531-MU26732e.h" + #include "microcode-539-MU167210.h" + #include "microcode-540-MU267238.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 3ebe361..467d3db 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -29,24 +29,10 @@ #include <cpu/x86/msr.h> #include <cpu/intel/l2_cache.h> -static const uint32_t microcode_updates[] = { - /* Include microcode updates here. */ - #include "microcode-293-MU267114.h" - #include "microcode-530-MU16730e.h" - #include "microcode-531-MU26732e.h" - #include "microcode-539-MU167210.h" - #include "microcode-540-MU267238.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_67x_init(device_t cpu) { /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Initialize L2 cache */ p6_configure_l2_cache(); diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index f7f05f6..9d9983e 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -21,3 +21,4 @@ config CPU_INTEL_MODEL_68X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 40bdd43..addee29 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -21,3 +21,4 @@ ramstage-y += model_68x_init.c subdirs-y += ../../x86/name +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c new file mode 100644 index 0000000..78e2e03 --- /dev/null +++ b/src/cpu/intel/model_68x/microcode_blob.c @@ -0,0 +1,25 @@ +unsigned microcode_updates_68x[] = { + #include "microcode-534-MU16810d.h" + #include "microcode-535-MU16810e.h" + #include "microcode-536-MU16810f.h" + #include "microcode-537-MU268110.h" + #include "microcode-538-MU168111.h" + #include "microcode-550-MU168307.h" + #include "microcode-551-MU168308.h" + #include "microcode-727-MU168313.h" + #include "microcode-728-MU168314.h" + #include "microcode-729-MU268310.h" + #include "microcode-611-MU168607.h" + #include "microcode-612-MU168608.h" + #include "microcode-615-MU16860a.h" + #include "microcode-617-MU16860c.h" + #include "microcode-618-MU268602.h" + #include "microcode-662-MU168a01.h" + #include "microcode-691-MU168a04.h" + #include "microcode-692-MU168a05.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index c4bd7ac..4bb9b56 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -32,32 +32,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-534-MU16810d.h" - #include "microcode-535-MU16810e.h" - #include "microcode-536-MU16810f.h" - #include "microcode-537-MU268110.h" - #include "microcode-538-MU168111.h" - #include "microcode-550-MU168307.h" - #include "microcode-551-MU168308.h" - #include "microcode-727-MU168313.h" - #include "microcode-728-MU168314.h" - #include "microcode-729-MU268310.h" - #include "microcode-611-MU168607.h" - #include "microcode-612-MU168608.h" - #include "microcode-615-MU16860a.h" - #include "microcode-617-MU16860c.h" - #include "microcode-618-MU268602.h" - #include "microcode-662-MU168a01.h" - #include "microcode-691-MU168a04.h" - #include "microcode-692-MU168a05.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_68x_init(device_t cpu) { char processor_name[49]; @@ -66,7 +40,7 @@ static void model_68x_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig index 596763c..4e88979 100644 --- a/src/cpu/intel/model_69x/Kconfig +++ b/src/cpu/intel/model_69x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_69X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc index 927bfeb..e9d90ca 100644 --- a/src/cpu/intel/model_69x/Makefile.inc +++ b/src/cpu/intel/model_69x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_69x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c new file mode 100644 index 0000000..e9ca20f --- /dev/null +++ b/src/cpu/intel/model_69x/microcode_blob.c @@ -0,0 +1,13 @@ +/* copyright and license text here */ + +unsigned microcode_updates_69x[] = { + #include "microcode-1376-m8069547.h" + #include "microcode-1373-m1069507.h" + #include "microcode-1374-m2069507.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index cb805ae..9ee7424 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -9,18 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - #include "microcode-1376-m8069547.h" - #include "microcode-1373-m1069507.h" - #include "microcode-1374-m2069507.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_69x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -29,7 +17,7 @@ static void model_69x_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 10661d0..26b5995 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6BX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 2d33f85..5f1f894 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c new file mode 100644 index 0000000..a6f9bc6 --- /dev/null +++ b/src/cpu/intel/model_6bx/microcode_blob.c @@ -0,0 +1,11 @@ +unsigned microcode_updates_6bx[] = { + #include "microcode-737-MU16b11c.h" + #include "microcode-738-MU16b11d.h" + #include "microcode-875-MU16b401.h" + #include "microcode-885-MU16b402.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b7affd9..e06665a 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -32,18 +32,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-737-MU16b11c.h" - #include "microcode-738-MU16b11d.h" - #include "microcode-875-MU16b401.h" - #include "microcode-885-MU16b402.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6bx_init(device_t cpu) { char processor_name[49]; @@ -52,7 +40,7 @@ static void model_6bx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig index 5e70f59..546d9ec 100644 --- a/src/cpu/intel/model_6dx/Kconfig +++ b/src/cpu/intel/model_6dx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6DX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc index cc88a2c..4731de3 100644 --- a/src/cpu/intel/model_6dx/Makefile.inc +++ b/src/cpu/intel/model_6dx/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_6dx_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c new file mode 100644 index 0000000..52489e4 --- /dev/null +++ b/src/cpu/intel/model_6dx/microcode_blob.c @@ -0,0 +1,9 @@ +unsigned microcode_updates_6dx[] = { + #include "microcode-1355-m206d618.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 19b351d..06236a3 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -9,16 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - #include "microcode-1355-m206d618.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6dx_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -27,7 +17,7 @@ static void model_6dx_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index e2b1986..8187838 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6EX select UDELAY_LAPIC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index b515c4f..6d94302 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c new file mode 100644 index 0000000..0798316 --- /dev/null +++ b/src/cpu/intel/model_6ex/microcode_blob.c @@ -0,0 +1,10 @@ +unsigned microcode_updates_6ex[] = { + #include "microcode-1624-m206e839.h" + #include "microcode-1729-m206ec54.h" + #include "microcode-1869-m806ec59.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index e9c63da..4dc642a 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -33,16 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-1624-m206e839.h" - #include "microcode-1729-m206ec54.h" - #include "microcode-1869-m806ec59.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; #define IA32_FEATURE_CONTROL 0x003a @@ -160,7 +150,7 @@ static void model_6ex_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 4517f17..3335a26 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6FX select UDELAY_LAPIC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index b75cde3..6a1bb51 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c new file mode 100644 index 0000000..f17613b --- /dev/null +++ b/src/cpu/intel/model_6fx/microcode_blob.c @@ -0,0 +1,26 @@ +unsigned microcode_updates_6fx[] = { + #include "microcode-m016fbBA.h" + #include "microcode-m046fbBC.h" + #include "microcode-m086fbBB.h" + #include "microcode-m106f76a.h" + #include "microcode-m106fbBA.h" + #include "microcode-m16f25d.h" + #include "microcode-m16f6d0.h" + #include "microcode-m16fda4.h" + #include "microcode-m206f25c.h" + #include "microcode-m206f6d1.h" + #include "microcode-m206fbBA.h" + #include "microcode-m206fda4.h" + #include "microcode-m406f76b.h" + #include "microcode-m406fbBC.h" + #include "microcode-m46f6d2.h" + #include "microcode-m806fa95.h" + #include "microcode-m806fbBA.h" + #include "microcode-m806fda4.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index faf1277..39aa8e9 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -33,33 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-m016fbBA.h" - #include "microcode-m046fbBC.h" - #include "microcode-m086fbBB.h" - #include "microcode-m106f76a.h" - #include "microcode-m106fbBA.h" - #include "microcode-m16f25d.h" - #include "microcode-m16f6d0.h" - #include "microcode-m16fda4.h" - #include "microcode-m206f25c.h" - #include "microcode-m206f6d1.h" - #include "microcode-m206fbBA.h" - #include "microcode-m206fda4.h" - #include "microcode-m406f76b.h" - #include "microcode-m406fbBC.h" - #include "microcode-m46f6d2.h" - #include "microcode-m806fa95.h" - #include "microcode-m806fbBA.h" - #include "microcode-m806fda4.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - #define IA32_FEATURE_CONTROL 0x003a #define CPUID_VMX (1 << 5) @@ -197,7 +170,7 @@ static void model_6fx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index 96c7040..b572385 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6XX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 5fdd71c..0c41cf2 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_6xx_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c new file mode 100644 index 0000000..8a7ef26 --- /dev/null +++ b/src/cpu/intel/model_6xx/microcode_blob.c @@ -0,0 +1,33 @@ +unsigned microcode_updates_6xx[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + +#include "microcode-99-B_c6_612.h" +#include "microcode-43-B_c6_617.h" +#include "microcode-51-B_c6_616.h" +#include "microcode-153-d2_619.h" + +#include "microcode-308-MU163336.h" +#include "microcode-309-MU163437.h" + +#include "microcode-358-MU166d05.h" +#include "microcode-359-MU166d06.h" +#include "microcode-386-MU16600a.h" +#include "microcode-398-MU166503.h" +#include "microcode-399-MU166a0b.h" +#include "microcode-400-MU166a0c.h" +#include "microcode-401-MU166a0d.h" +#include "microcode-402-MU166d07.h" + +#include "microcode-566-mu26a003.h" +#include "microcode-588-mu26a101.h" +#include "microcode-620-MU26a401.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 5724add..e81f9ae 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -9,40 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - -#include "microcode-99-B_c6_612.h" -#include "microcode-43-B_c6_617.h" -#include "microcode-51-B_c6_616.h" -#include "microcode-153-d2_619.h" - -#include "microcode-308-MU163336.h" -#include "microcode-309-MU163437.h" - -#include "microcode-358-MU166d05.h" -#include "microcode-359-MU166d06.h" -#include "microcode-386-MU16600a.h" -#include "microcode-398-MU166503.h" -#include "microcode-399-MU166a0b.h" -#include "microcode-400-MU166a0c.h" -#include "microcode-401-MU166a0d.h" -#include "microcode-402-MU166d07.h" - -#include "microcode-566-mu26a003.h" -#include "microcode-588-mu26a101.h" -#include "microcode-620-MU26a401.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6xx_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -51,7 +17,7 @@ static void model_6xx_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig index 9dd7fd0..0616589 100644 --- a/src/cpu/intel/model_f0x/Kconfig +++ b/src/cpu/intel/model_f0x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F0X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc index 79ea2a0..6c16419 100644 --- a/src/cpu/intel/model_f0x/Makefile.inc +++ b/src/cpu/intel/model_f0x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f0x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c new file mode 100644 index 0000000..079a2cb --- /dev/null +++ b/src/cpu/intel/model_f0x/microcode_blob.c @@ -0,0 +1,14 @@ +/* 256KB cache */ +unsigned microcode_updates_f0x[] = { + #include "microcode-678-2f0708.h" + #include "microcode-965-m01f0a13.h" + #include "microcode-983-m02f0a15.h" + #include "microcode-964-m01f0712.h" + #include "microcode-966-m04f0a14.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ed12b6e..8d81182 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -9,21 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -/* 256KB cache */ -static uint32_t microcode_updates[] = { - #include "microcode-678-2f0708.h" - #include "microcode-965-m01f0a13.h" - #include "microcode-983-m02f0a15.h" - #include "microcode-964-m01f0712.h" - #include "microcode-966-m04f0a14.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f0x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -32,7 +17,7 @@ static void model_f0x_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig index ea75857..fd64920 100644 --- a/src/cpu/intel/model_f1x/Kconfig +++ b/src/cpu/intel/model_f1x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F1X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc index 6449ae9..c706234 100644 --- a/src/cpu/intel/model_f1x/Makefile.inc +++ b/src/cpu/intel/model_f1x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f1x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c new file mode 100644 index 0000000..308402c --- /dev/null +++ b/src/cpu/intel/model_f1x/microcode_blob.c @@ -0,0 +1,17 @@ +/* 256KB cache */ +unsigned microcode_updates_f1x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + #include "microcode-1068-m01f122d.h" + #include "microcode-1069-m04f122e.h" + #include "microcode-1070-m02f122f.h" + #include "microcode-1072-m04f1305.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index feb8410..b294c61 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -9,24 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -/* 256KB cache */ -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - #include "microcode-1068-m01f122d.h" - #include "microcode-1069-m04f122e.h" - #include "microcode-1070-m02f122f.h" - #include "microcode-1072-m04f1305.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f1x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -35,7 +17,7 @@ static void model_f1x_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 50cac79..8483d33 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F2X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 9b366d6..3360611 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f2x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c new file mode 100644 index 0000000..e8c9302 --- /dev/null +++ b/src/cpu/intel/model_f2x/microcode_blob.c @@ -0,0 +1,33 @@ +/* 512KB cache */ +unsigned microcode_updates_f2x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + + /* Old microcode file not present in Intel's microcode.dat. */ +#include "microcode_m02f2203.h" + + /* files from Intel's microcode.dat */ +#include "microcode-1343-m04f252b.h" +#include "microcode-1346-m10f252c.h" +#include "microcode-1338-m02f292d.h" +#include "microcode-1340-m08f292f.h" +#include "microcode-1107-m10f2421.h" +#include "microcode-1339-m04f292e.h" +#include "microcode-1105-m08f2420.h" +#include "microcode-1336-m02f2610.h" +#include "microcode-1101-m02f2738.h" +#include "microcode-1100-m04f2737.h" +#include "microcode-1341-m01f2529.h" +#include "microcode-1102-m08f2739.h" +#include "microcode-1104-m04f241e.h" +#include "microcode-1342-m02f252a.h" +#include "microcode-1106-m02f241f.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 8fd8abc..9e8fbfc 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -10,40 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -/* 512KB cache */ -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - - /* Old microcode file not present in Intel's microcode.dat. */ -#include "microcode_m02f2203.h" - - /* files from Intel's microcode.dat */ -#include "microcode-1343-m04f252b.h" -#include "microcode-1346-m10f252c.h" -#include "microcode-1338-m02f292d.h" -#include "microcode-1340-m08f292f.h" -#include "microcode-1107-m10f2421.h" -#include "microcode-1339-m04f292e.h" -#include "microcode-1105-m08f2420.h" -#include "microcode-1336-m02f2610.h" -#include "microcode-1101-m02f2738.h" -#include "microcode-1100-m04f2737.h" -#include "microcode-1341-m01f2529.h" -#include "microcode-1102-m08f2739.h" -#include "microcode-1104-m04f241e.h" -#include "microcode-1342-m02f252a.h" -#include "microcode-1106-m02f241f.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f2x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -55,7 +21,7 @@ static void model_f2x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 4cfca83..8ae2dcf 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F3X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index cf8f918..ebd47cf 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f3x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c new file mode 100644 index 0000000..0bd2a5b --- /dev/null +++ b/src/cpu/intel/model_f3x/microcode_blob.c @@ -0,0 +1,16 @@ +unsigned microcode_updates_f3x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + +#include "microcode-1290-m0df320a.h" +#include "microcode-1467-m0df330c.h" +#include "microcode-1468-m1df3417.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 2504ba9..5752347 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -10,23 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - -#include "microcode-1290-m0df320a.h" -#include "microcode-1467-m0df330c.h" -#include "microcode-1468-m1df3417.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -38,7 +21,7 @@ static void model_f3x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 97c909a..c21a274 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F4X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index ac99095..6ade9f3 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f4x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c new file mode 100644 index 0000000..4f1147c --- /dev/null +++ b/src/cpu/intel/model_f4x/microcode_blob.c @@ -0,0 +1,24 @@ +unsigned microcode_updates_f4x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + + #include "microcode-1735-m01f480c.h" + #include "microcode-1460-m9df4305.h" + #include "microcode-2492-m02f480e.h" + #include "microcode-1470-m9df4703.h" + #include "microcode-1521-m5ff4807.h" + #include "microcode-1466-m02f4116.h" + #include "microcode-1469-m9df4406.h" + #include "microcode-1471-mbdf4117.h" + #include "microcode-1637-m5cf4a04.h" + #include "microcode-1462-mbdf4903.h" + #include "microcode-1498-m5df4a02.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index f3f0b2a..80d7dc8 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -10,31 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - - #include "microcode-1735-m01f480c.h" - #include "microcode-1460-m9df4305.h" - #include "microcode-2492-m02f480e.h" - #include "microcode-1470-m9df4703.h" - #include "microcode-1521-m5ff4807.h" - #include "microcode-1466-m02f4116.h" - #include "microcode-1469-m9df4406.h" - #include "microcode-1471-mbdf4117.h" - #include "microcode-1637-m5cf4a04.h" - #include "microcode-1462-mbdf4903.h" - #include "microcode-1498-m5df4a02.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f4x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -46,7 +21,7 @@ static void model_f4x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 92775aa..e3e6fb2 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -19,10 +19,20 @@ config CPU_INTEL_SLOT_1 bool + +if CPU_INTEL_SLOT_1 + +config SLOT_SPECIFIC_OPTIONS # dummy + def_bool y select CACHE_AS_RAM + select CPU_INTEL_MODEL_65X + select CPU_INTEL_MODEL_67X + select CPU_INTEL_MODEL_68X + select CPU_INTEL_MODEL_6BX + select CPU_INTEL_MODEL_6XX config DCACHE_RAM_SIZE hex default 0x01000 - depends on CPU_INTEL_SLOT_1 +endif diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 7ab2933..c8a4b59 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -19,6 +19,7 @@ config CPU_INTEL_SOCKET_PGA370 bool + select CPU_INTEL_MODEL_6XX select MMX select UDELAY_TSC select CACHE_AS_RAM diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 460bafb..3d1c23a 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,6 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); /* Find a microcode that matches the revision and platform family returning * NULL if none found. */ @@ -30,9 +29,6 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); -#else -void intel_update_microcode(const void *microcode_updates); -#endif #endif #endif

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coreboot-gerrit December 2013