coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

1 participants
1377 discussions

New patch to review for coreboot: 7b6f060 Asus F2A85-M: show POST codes
by Idwer Vollering 22 Dec '13

22 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4561 -gerrit commit 7b6f0608cb18ae50480a0210f7f9c258c5510b30 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:01:51 2013 +0000 Asus F2A85-M: show POST codes Add conditional POST code output, toggled by CONFIG_IO_POST_PORT. Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index fe66dde..df21ede 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,7 +64,9 @@ static void sbxxx_enable_48mhzout(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { +#if CONFIG_IO_POST_PORT hudson_pci_port80(); +#endif u32 val; u8 byte;

1 0

New patch to review for coreboot: 5210897 Asus F2a85-M: show POST
by Idwer Vollering 22 Dec '13

22 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4560 -gerrit commit 5210897c76e87a32fcff54389e23bd1b1054b4c6 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:00:28 2013 +0000 Asus F2a85-M: show POST Change-Id: Ie88fd84df1ed43597741f7d5272d0ec86fa93b44 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..fe66dde 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,6 +64,8 @@ static void sbxxx_enable_48mhzout(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { + hudson_pci_port80(); + u32 val; u8 byte; device_t dev;

1 0

New patch to review for coreboot: 7d39934 AMD Hudson: show POST codes on a PCI device
by Idwer Vollering 22 Dec '13

22 Dec '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4559 -gerrit commit 7d39934c91b911bf751517fd7bd33e93b46085ca Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 20:55:41 2013 +0000 AMD Hudson: show POST codes on a PCI device Show POST codes on a PCI device: implement hudson_pci_port80();. This shares much code with sb600/sb700/sb800. Tested on an Asus F2A85-M. Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/southbridge/amd/agesa/hudson/early_setup.c | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 96861c9..690e987 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -29,6 +29,51 @@ #include <cbmem.h> #include "hudson.h" +void hudson_pci_port80(void) +{ + u8 byte; + device_t dev; + + /* P2P Bridge */ + dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); + + /* Chip Control: Enable subtractive decoding */ + byte = pci_read_config8(dev, 0x40); + byte |= 1 << 5; + pci_write_config8(dev, 0x40, byte); + + /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ + byte = pci_read_config8(dev, 0x4B); + byte |= 1 << 7; + pci_write_config8(dev, 0x4B, byte); + + /* The same IO Base and IO Limit here is meaningful because we set the + * bridge to be subtractive. During early setup stage, we have to make + * sure that data can go through port 0x80. + */ + /* IO Base: 0xf000 */ + byte = pci_read_config8(dev, 0x1C); + byte |= 0xF << 4; + pci_write_config8(dev, 0x1C, byte); + + /* IO Limit: 0xf000 */ + byte = pci_read_config8(dev, 0x1D); + byte |= 0xF << 4; + pci_write_config8(dev, 0x1D, byte); + + /* PCI Command: Enable IO response */ + byte = pci_read_config8(dev, 0x04); + byte |= 1 << 0; + pci_write_config8(dev, 0x04, byte); + + /* LPC controller */ + dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + + byte = pci_read_config8(dev, 0x4A); + byte &= ~(1 << 5); /* disable lpc port 80 */ + pci_write_config8(dev, 0x4A, byte); +} + void hudson_lpc_port80(void) { u8 byte;

1 0

New patch to review for coreboot: 82676eb AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
by Kyösti Mälkki 22 Dec '13

22 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4558 -gerrit commit 82676ebeb6237f11ed42f2ddd86509961aaeec2d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 20:48:40 2013 +0200 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/model_fxx/init_cpus.c | 3 ++- src/cpu/amd/model_fxx/model_fxx_init.c | 2 ++ src/mainboard/asus/a8n_e/Kconfig | 4 ---- src/mainboard/msi/ms7135/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 8 ++++---- 5 files changed, 8 insertions(+), 13 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 7121642..6ba5025 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -293,11 +293,12 @@ static u32 init_cpus(u32 cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); +#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); #endif - +#endif STOP_CAR_AND_CPU(); } diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 4beecab..260e83e 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -31,11 +31,13 @@ #if CONFIG_WAIT_BEFORE_CPUS_INIT void cpus_ready_for_init(void) { +#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif +#endif } #endif diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index acb528b..ba2e5b1 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 14c0f49..76b6625 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -24,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7135" diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 294002e..ce2460e 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -37,10 +37,6 @@ config WAIT_BEFORE_CPUS_INIT bool default n -config MEM_TRAIN_SEQ - int - default 0 - # Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and # single DIMM is indeed unreliable without it). config K8_FORCE_2T_DRAM_TIMING @@ -99,6 +95,10 @@ if DIMM_DDR2 endif endif #DIMM_DDR2 +config MEM_TRAIN_SEQ + int + default 0 + endif #K8_REV_F_SUPPORT config IOMMU

1 0

New patch to review for coreboot: d845e3a AMD K8: Socket implies K8_REV_F_SUPPORT
by Kyösti Mälkki 22 Dec '13

22 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4557 -gerrit commit d845e3ae7d1dcfd655768e20225f33f3c0bb6d9a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 20:42:58 2013 +0200 AMD K8: Socket implies K8_REV_F_SUPPORT Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/Kconfig | 4 ---- src/mainboard/asus/m2n-e/Kconfig | 1 - src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 1 - src/mainboard/gigabyte/m57sli/Kconfig | 1 - src/mainboard/msi/ms7260/Kconfig | 1 - src/mainboard/msi/ms9282/Kconfig | 1 - src/mainboard/newisys/khepri/Kconfig | 4 ---- src/mainboard/nvidia/l1_2pvv/Kconfig | 1 - src/mainboard/sunw/ultra40/Kconfig | 4 ---- src/mainboard/tyan/s2912/Kconfig | 1 - src/mainboard/tyan/s4880/Kconfig | 4 ---- src/mainboard/tyan/s4882/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 4 ++++ 13 files changed, 4 insertions(+), 27 deletions(-) diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index dd78ca9..5603f41 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -1,7 +1,3 @@ -config K8_REV_F_SUPPORT - bool - default n - source src/cpu/amd/socket_754/Kconfig source src/cpu/amd/socket_939/Kconfig source src/cpu/amd/socket_940/Kconfig diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 8d60e0c..8d01e32 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select K8_ALLOCATE_IO_RANGE diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index 1c57840..e3166a0 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index d7483b7..ef2811c 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select LIFT_BSP_APIC_ID select HAVE_ACPI_TABLES - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 437c062..72249aa 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index 63d4c60..f267b96 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 04c8ed3..94de54b 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config K8_REV_F_SUPPORT - bool - default n - config SB_HT_CHAIN_ON_BUS0 int default 0 diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index aba4cbd..28da2d9 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index ba7aaa4..80e08c4 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -32,10 +32,6 @@ config APIC_ID_OFFSET hex default 0x10 -config K8_REV_F_SUPPORT - bool - default n - config CK804_NUM int default 2 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index cad352b..a55586b 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index 1299e33..449aa39 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x10 -config K8_REV_F_SUPPORT - bool - default n - config SB_HT_CHAIN_ON_BUS0 int default 0 diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2dd3a44..ec1f7a9 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x10 -config K8_REV_F_SUPPORT - bool - default n - config SB_HT_CHAIN_ON_BUS0 int default 0 diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 2f3660b..294002e 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -71,6 +71,10 @@ config K8_ALLOCATE_IO_RANGE bool default n +config K8_REV_F_SUPPORT + bool + default n + if K8_REV_F_SUPPORT config DIMM_DDR2

1 0

New patch to review for coreboot: 1968572 AMD AGESA: Drop MEM_TRAIN_SEQ
by Kyösti Mälkki 22 Dec '13

22 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4556 -gerrit commit 1968572ccde2937245125bbc54d58de1f1270979 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 18:00:22 2013 +0200 AMD AGESA: Drop MEM_TRAIN_SEQ This config was for AMD K8 only. Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/inagua/Kconfig | 4 ---- src/mainboard/amd/olivehill/Kconfig | 4 ---- src/mainboard/amd/parmer/Kconfig | 4 ---- src/mainboard/amd/persimmon/Kconfig | 4 ---- src/mainboard/amd/south_station/Kconfig | 4 ---- src/mainboard/amd/thatcher/Kconfig | 4 ---- src/mainboard/amd/torpedo/Kconfig | 4 ---- src/mainboard/amd/union_station/Kconfig | 4 ---- src/mainboard/asrock/e350m1/Kconfig | 4 ---- src/mainboard/asrock/imb-a180/Kconfig | 4 ---- src/mainboard/asus/f2a85-m/Kconfig | 4 ---- src/mainboard/lippert/frontrunner-af/Kconfig | 4 ---- src/mainboard/lippert/toucan-af/Kconfig | 4 ---- src/mainboard/supermicro/h8qgi/Kconfig | 4 ---- src/mainboard/supermicro/h8scm/Kconfig | 4 ---- 15 files changed, 60 deletions(-) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index cf868fe..b3b63cc 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -66,10 +66,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index fdd0d6c..60ca8eb 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -65,10 +65,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index e0787be..a772d50 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -66,10 +66,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 5781a25..febd8dd 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -66,10 +66,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 81d631f..08298f0 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -66,10 +66,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index b58514b..11d2d9b 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -66,10 +66,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index cfcf3cb..351f19a 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -68,10 +68,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 848fd36..5047793 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -65,10 +65,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 026deeb..a5a878b 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -66,10 +66,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 91e83b1..d031838 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -65,10 +65,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 1192868..b4fdf50 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -91,10 +91,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 945d9cb..a0dbaf9 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -70,10 +70,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index be016fb..904c7c8 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -72,10 +72,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 5ee9a19..6371d9e 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -62,10 +62,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index a7f40be..86395e4 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -65,10 +65,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config IRQ_SLOT_COUNT int default 11

1 0

New patch to review for coreboot: f41c0bc AMD fam10: Drop MEM_TRAIN_SEQ
by Kyösti Mälkki 22 Dec '13

22 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4555 -gerrit commit f41c0bc5dc5ce55088ce6c346cf5109031436624 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 18:00:22 2013 +0200 AMD fam10: Drop MEM_TRAIN_SEQ This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 4 ---- src/mainboard/amd/bimini_fam10/Kconfig | 4 ---- src/mainboard/amd/mahogany_fam10/Kconfig | 4 ---- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 4 ---- src/mainboard/amd/tilapia_fam10/Kconfig | 4 ---- src/mainboard/asus/m4a78-em/Kconfig | 4 ---- src/mainboard/asus/m4a785-m/Kconfig | 4 ---- src/mainboard/asus/m4a785t-m/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Kconfig | 4 ---- src/mainboard/avalue/eax-785e/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gm/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gmt/Kconfig | 4 ---- src/mainboard/gigabyte/ma78gm/Kconfig | 4 ---- src/mainboard/iei/kino-780am2-fam10/Kconfig | 4 ---- src/mainboard/jetway/pa78vm5/Kconfig | 4 ---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 4 ---- src/mainboard/supermicro/h8qme_fam10/Kconfig | 4 ---- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ---- src/mainboard/tyan/s2912_fam10/Kconfig | 4 ---- src/northbridge/amd/amdfam10/Kconfig | 4 ---- src/northbridge/amd/amdfam10/amdfam10.h | 8 +------- 22 files changed, 1 insertion(+), 91 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index fdf08aa..c5d2f15 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 09e731c..5535980 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index 6691ce3..7efc33f 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 4ea8aca..4984b43 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -45,10 +45,6 @@ config MAX_PHYSICAL_CPUS int default 8 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 3c2fc52..7d51968 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index d8a3191..7ba70bd 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index c2ed696..13e30c9 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 6816d58..d9badee 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -46,10 +46,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 942a81d..256add4 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -54,10 +54,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 99b9c67..bfae1ee 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 8ff88b2..282387c 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 15032f6..f4c5fff 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 20be00f..1582786 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 4c02a62..891ed82 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index 11dd1e5..f1108e0 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index b6baac3..f060fee 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -137,10 +137,6 @@ config RAMTOP hex default 0x1000000 -config MEM_TRAIN_SEQ - int - default 2 - config AMD_UCODE_PATCH_FILE string default "mc_patch_01000096.h" diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 94b56ea..4c9d3ea 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -49,10 +49,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 89675d3..2a5441a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -48,10 +48,6 @@ config APIC_ID_OFFSET hex default 0x0 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 5e28aea..021ba87 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 1 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 085148f..eb083a6 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -37,10 +37,6 @@ config APIC_ID_OFFSET hex default 0 -config MEM_TRAIN_SEQ - int - default 2 - config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 73da579..d26b05e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -38,10 +38,6 @@ config AMDMCT bool default y -config MEM_TRAIN_SEQ - int - default 0 - config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index eded515..aef2ad6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1038,13 +1038,7 @@ struct nodes_info_t { //#define MEM_CS_COPY 1 #define MEM_CS_COPY NODE_NUMS - -#if CONFIG_MEM_TRAIN_SEQ == 0 - #define DQS_DELAY_COPY NODE_NUMS -#else -// #define DQS_DELAY_COPY 1 - #define DQS_DELAY_COPY NODE_NUMS -#endif +#define DQS_DELAY_COPY NODE_NUMS #endif

1 0

Patch merged into coreboot/master: 8af3b84 Fix linking microcode with more than one microcode file
by gerrit＠coreboot.org 22 Dec '13

22 Dec '13

the following patch was just integrated into master: commit 8af3b84292e9f901fc92f310fad3458e0de49fc7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Dec 7 18:57:02 2013 -0600 Fix linking microcode with more than one microcode file When assembling microcode , the rule to link individual object files into one larger file only passed the first dependency to the linker. As a results only microcode from one object file would actually get linked. This is fixed by replacing $^ with $+ inside the make rule. Change-Id: I65c0565f2e03777af23e530c08d1241804ca19b1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4500 for details. -gerrit

1 0

Patch set updated for coreboot: 9b1277d Implement proper IT8728F PNP ops
by Patrick Georgi 22 Dec '13

22 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4498 -gerrit commit 9b1277db22f05abd02b299c02b639360df65787b Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat Dec 7 22:34:24 2013 +0100 Implement proper IT8728F PNP ops The Asus F2A85-M has IT8306E which is a stripped down version of this SIO. Implement the PNP SIO ops and do the HWM setup. If there is future user implement some config option for devicetree.cb. Implement missing early calls needed for F2A85-M. Change-Id: Ibc4f3fafc3ffb1cd799948e63be01e6924b45d6c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/superio/ite/it8728f/Makefile.inc | 2 + src/superio/ite/it8728f/chip.h | 33 ++++++++ src/superio/ite/it8728f/early_serial.c | 23 ++++++ src/superio/ite/it8728f/early_serial.h | 3 + src/superio/ite/it8728f/it8728f.h | 2 + src/superio/ite/it8728f/superio.c | 141 +++++++++++++++++++++++++++++++++ 6 files changed, 204 insertions(+) diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index d8d4f6a..46fd40a 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -19,3 +19,5 @@ ## romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c + diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h new file mode 100644 index 0000000..8013531 --- /dev/null +++ b/src/superio/ite/it8728f/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_CHIP_H +#define SUPERIO_ITE_IT8728F_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct superio_ite_it8728f_config { + + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/ite/it8728f/early_serial.c b/src/superio/ite/it8728f/early_serial.c index 7fbd061..78a49aa 100644 --- a/src/superio/ite/it8728f/early_serial.c +++ b/src/superio/ite/it8728f/early_serial.c @@ -69,3 +69,26 @@ void it8728f_enable_serial(device_t dev, u16 iobase) /* (3) Exit the configuration state (MB PnP mode). */ it8728f_exit_conf(dev); } + +/* + * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! + * + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ +void it8728f_enable_3vsbsw(device_t dev) +{ + it8728f_enter_conf(dev); + it8728f_sio_write(dev, IT8728F_CONFIG_REG_MFC, 0x80); + it8728f_exit_conf(dev); +} + +void it8728f_kill_watchdog(device_t dev) +{ + it8728f_enter_conf(dev); + it8728f_sio_write(dev, IT8728F_CONFIG_REG_WATCHDOG, 0x00); + it8728f_exit_conf(dev); +} diff --git a/src/superio/ite/it8728f/early_serial.h b/src/superio/ite/it8728f/early_serial.h index a146f4c..3443e0d 100644 --- a/src/superio/ite/it8728f/early_serial.h +++ b/src/superio/ite/it8728f/early_serial.h @@ -37,4 +37,7 @@ void it8728f_24mhz_clkin(device_t dev); /* Enable the serial port(s). */ void it8728f_enable_serial(device_t dev, u16 iobase); +void it8728f_kill_watchdog(device_t dev); +void it8728f_enable_3vsbsw(device_t dev); + #endif diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 603e467..9a92f5a 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -38,5 +38,7 @@ #define IT8728F_CONFIG_REG_CHIPVERS 0x22 /* Chip version */ #define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ +#define IT8728F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ +#define IT8728F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #endif diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c new file mode 100644 index 0000000..67699fa --- /dev/null +++ b/src/superio/ite/it8728f/superio.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include "chip.h" +#include "it8728f.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev->path.pnp.port; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + pnp_write_config(dev, 0x02, 0x02); +} + +static u8 hwm_read(u16 base, u8 reg) +{ + outb(reg, base + 5); + return inb(base + 6); +} + +static void hwm_write(u16 base, u8 reg, u8 val) +{ + outb(reg, base + 5); + outb(val, base + 6); +} + +static void it8728f_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8728F_FDC: /* TODO. */ + break; + case IT8728F_PP: /* TODO. */ + break; + case IT8728F_EC: + { + /* keep it simple for now, configuration options may come later */ + u8 tmp; + u16 base; + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + /* there must be better way to read the I/O base */ + base = ((u16) pnp_read_config(dev, 0x60) << 8); + base |= pnp_read_config(dev, 0x61); + tmp = hwm_read(base, 0x14); + /* setup fan polarity */ + hwm_write(base, 0x14, tmp | (1 << 7)); + /* enable fans 1-3 */ + tmp = hwm_read(base, 0x13); + hwm_write(base, 0x13, tmp | (7 << 4)); + /* enable termistor temps for temp1-temp3 */ + tmp = hwm_read(base, 0x51); + hwm_write(base, 0x51, tmp | (7 << 3)); + /* fan2 is using temp1 */ + hwm_write(base, 0x16, 0x80); + pnp_exit_ext_func_mode(dev); + break; + } + case IT8728F_KBCK: + set_kbc_ps2_mode(); + pc_keyboard_init(&conf->keyboard); + break; + case IT8728F_KBCM: /* TODO. */ + break; + case IT8728F_IR: /* TODO. */ + break; + } +} + +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8728f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, IT8728F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, IT8728F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, IT8728F_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, IT8728F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ffc, 0}, }, + { &ops, IT8728F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, }, + { &ops, IT8728F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, IT8728F_KBCM, PNP_IRQ0, }, + { &ops, IT8728F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0x0fff, 0}, {0x0ff8, 0}, {0x0ff8, 0}, }, + { &ops, IT8728F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8728f_ops = { + CHIP_NAME("ITE IT8728F Super I/O") + .enable_dev = enable_dev, +};

1 0

Patch set updated for coreboot: 7fc372e Implement PNP resource setup in LPC bridge
by Patrick Georgi 22 Dec '13

22 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4497 -gerrit commit 7fc372e1c7c9413da67d03ab6f0b44e493c19119 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat Dec 7 22:29:36 2013 +0100 Implement PNP resource setup in LPC bridge The previous SBxxx generations were setting up LPC bridge based on the PNP resources. Implement it also for AGESA Hudson. The AGESA itself opens one big region DFLT_SIO_PME_BASE_ADDRESS (512 bytes). Make the code smart enough to detect already used region and if any resource fits into AGESA defined region, do nothing. Change-Id: I718d034bc4c778697a7bd0506d4550c8f5a43159 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/southbridge/amd/agesa/hudson/lpc.c | 174 ++++++++++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 3af3eb8..a0dc072 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -129,8 +129,180 @@ static void hudson_lpc_set_resources(struct device *dev) */ static void hudson_lpc_enable_childrens_resources(device_t dev) { - printk(BIOS_DEBUG, "hudson_lpc_enable_childrens_resources\n"); + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + u16 reg_size[1] = {512}; + u8 wiosize = pci_read_config8(dev, 0x74); + /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit, + * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes + * it must be 512 bytes to be able to allocate the fresh LPC window. + * + * AGESA likes to enable already one LPC region in wide port base 0x64-0x65, + * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size + * The code tries to check if resource can fit into this region + */ + + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + /* check if ranges are free and not use them if entry is just already taken */ + if (reg_x & (1 << 2)) + var_num = 1; + /* just in case check if someone did not manually set other ranges too */ + if (reg_x & (1 << 24)) + var_num = 2; + + if (reg_x & (1 << 25)) + var_num = 3; + + /* check AGESA region size */ + if (wiosize & (1 << 0)) + reg_size[0] = 16; + + reg_var[2] = pci_read_config16(dev, 0x90); + reg_var[1] = pci_read_config16(dev, 0x66); + reg_var[0] = pci_read_config16(dev, 0x64); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + u32 rsize, set = 0, set_x = 0; + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); + /* find a resource size */ + printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + set |= (1 << 29); + rsize = 1; + break; + case 0x3f8: /* COM1 */ + set |= (1 << 6); + rsize = 8; + break; + case 0x2f8: /* COM2 */ + set |= (1 << 7); + rsize = 8; + break; + case 0x378: /* Parallel 1 */ + set |= (1 << 0); + set |= (1 << 1); /* + 0x778 for ECP */ + rsize = 8; + break; + case 0x3f0: /* FD0 */ + set |= (1 << 26); + rsize = 8; + break; + case 0x220: /* 0x220 - 0x227 */ + set |= (1 << 8); + rsize = 8; + break; + case 0x228: /* 0x228 - 0x22f */ + set |= (1 << 9); + rsize = 8; + break; + case 0x238: /* 0x238 - 0x23f */ + set |= (1 << 10); + rsize = 8; + break; + case 0x300: /* 0x300 -0x301 */ + set |= (1 << 18); + rsize = 2; + break; + case 0x400: + set_x |= (1 << 16); + rsize = 0x40; + break; + case 0x480: + set_x |= (1 << 17); + rsize = 0x40; + case 0x500: + set_x |= (1 << 18); + rsize = 0x40; + break; + case 0x580: + set_x |= (1 << 19); + rsize = 0x40; + break; + case 0x4700: + set_x |= (1 << 22); + rsize = 0xc; + break; + case 0xfd60: + set_x |= (1 << 23); + rsize = 16; + break; + default: + rsize = 0; + /* try AGESA allocated region in region 0 */ + if ((var_num > 0) && ((base >=reg_var[0]) && + ((base + res->size) <= (reg_var[0] + reg_size[0])))) + rsize = reg_size[0]; + } + /* check if region found and matches the enable */ + if (res->size <= rsize) { + reg |= set; + reg_x |= set_x; + /* check if we can fit resource in variable range */ + } else if ((var_num < 3) && + ((res->size <= 16) || (res->size == 512))) { + /* use variable ranges if pre-defined do not match */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + if (res->size <= 16) { + wiosize |= (1 << 0); + } + break; + case 1: + reg_x |= (1 << 24); + if (res->size <= 16) + wiosize |= (1 << 2); + break; + case 2: + reg_x |= (1 << 25); + if (res->size <= 16) + wiosize |= (1 << 3); + break; + } + reg_var[var_num++] = + base & 0xffff; + } else { + printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 3: + pci_write_config16(dev, 0x90, reg_var[2]); + /* fall through */ + case 2: + pci_write_config16(dev, 0x66, reg_var[1]); + /* fall through */ + case 1: + pci_write_config16(dev, 0x64, reg_var[0]); + break; + } + pci_write_config8(dev, 0x74, wiosize); } static void hudson_lpc_enable_resources(device_t dev)

1 0

← Newer
1
...
9
10
11
12
13
14
15
...
138
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2013