coreboot-gerrit December 2013

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Patch set updated for coreboot: b236be8 lynxpoint: Fix issues with XHCI init
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4408 -gerrit commit b236be8b410d5e6924a68a0b74f83dbaac16edd9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 15:58:18 2013 -0700 lynxpoint: Fix issues with XHCI init - Put the device into D0 and not D3 so memory bar is available and the subsequent commands actually do something useful - Remove set of 818Ch[7:0]=FFh (gone in ref code) - Fix reg 0x40/0x44 mixup Verify that expected bits are set: localhost ~ # pci_read32 0 0x14 0 0x10 0xe0500004 localhost ~ # mmio_read32 0xe0508144 0x000003ff localhost ~ # mmio_read32 0xe050816c 0x000f0038 Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63801 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/usb_xhci.c | 39 +++++++++++++----------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index dbf0f40..f866c4f 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -235,6 +235,7 @@ void usb_xhci_route_all(void) static void usb_xhci_clock_gating(device_t dev) { u32 reg32; + u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); @@ -258,9 +259,9 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ - reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1 << 9) | (1 << 7) | (1 << 3); - pci_write_config32(dev, 0x44, reg32); + reg16 = pci_read_config16(dev, 0x44); + reg16 |= (1 << 9) | (1 << 7) | (1 << 3); + pci_write_config16(dev, 0x44, reg16); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { @@ -323,21 +324,20 @@ static void usb_xhci_enable_ports_usb3(device_t dev) static void usb_xhci_init(device_t dev) { - struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); u32 reg32; + u16 reg16; + u32 mem_base = usb_xhci_mem_base(dev); - if (!bar0 || bar0->base == 0 || bar0->base == 0xffffffff) - return; + /* D20:F0:74h[1:0] = 00b (set D0 state) */ + reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Enable clock gating first */ usb_xhci_clock_gating(dev); - /* D20:F0:74h[1:0] = 11b (set D3Hot state) */ - reg32 = pci_read_config16(dev, 0x74); - reg32 |= (1 << 1) | (1 << 0); - pci_write_config16(dev, 0x74, reg32); - - reg32 = read32(bar0->base + 0x8144); + reg32 = read32(mem_base + 0x8144); if (pch_is_lp()) { /* XHCIBAR + 8144h[8,7,6] = 111b */ reg32 |= (1 << 8) | (1 << 7) | (1 << 6); @@ -346,25 +346,20 @@ static void usb_xhci_init(device_t dev) reg32 &= ~((1 << 7) | (1 << 6)); reg32 |= (1 << 8); } - write32(bar0->base + 0x8144, reg32); + write32(mem_base + 0x8144, reg32); if (pch_is_lp()) { /* XHCIBAR + 816Ch[19:0] = 000f0038h */ - reg32 = read32(bar0->base + 0x816c); + reg32 = read32(mem_base + 0x816c); reg32 &= ~0x000fffff; reg32 |= 0x000f0038; - write32(bar0->base + 0x816c, reg32); + write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); reg32 |= (1 << 17); pci_write_config32(dev, 0xb0, reg32); - - /* XHCIBAR + 818Ch[7:0] = FFh */ - reg32 = read32(bar0->base + 0x818c); - reg32 |= 0xff; - write32(bar0->base + 0x818c, reg32); } reg32 = pci_read_config32(dev, 0x50); @@ -380,9 +375,9 @@ static void usb_xhci_init(device_t dev) pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ - reg32 = pci_read_config32(dev, 0x40); + reg32 = pci_read_config32(dev, 0x44); reg32 |= (1 << 31); - pci_write_config32(dev, 0x40, reg32); + pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40);

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Patch set updated for coreboot: cbd0ac8 lynxpoint: Route all USB ports to XHCI in finalize step
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4407 -gerrit commit cbd0ac892d4ced844899f96db8de9ac8eaec8bc9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 16:05:55 2013 -0700 lynxpoint: Route all USB ports to XHCI in finalize step This commit adds a new Kconfig option for the LynxPoint southbridge that will have coreboot route all of the USB ports to the XHCI controller in the finalize step (i.e. after the bootloader) and disable the EHCI controller(s). Additionally when doing this the XHCI USB3 ports need to be put into an expected state on resume in order to make the kernel state machine happy. Part of this could also be done in depthcharge but there are also some resume-time steps required so it makes sense to keep it all together in coreboot. This can theoretically save ~100mW at runtime. Verify that the EHCI controller is not found in Linux and that booting from USB still works. Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63802 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/smm.h | 1 + src/southbridge/intel/lynxpoint/Kconfig | 7 ++ src/southbridge/intel/lynxpoint/pch.h | 1 + src/southbridge/intel/lynxpoint/smihandler.c | 7 ++ src/southbridge/intel/lynxpoint/usb_xhci.c | 102 ++++++++++++++++++++++++--- 5 files changed, 108 insertions(+), 10 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 607c0f0..feb50ec 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -372,6 +372,7 @@ typedef struct { #define APM_CNT_ACPI_ENABLE 0xe1 #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_GNVS_UPDATE 0xea +#define APM_CNT_FINALIZE 0xcb #define APM_STS 0xb3 /* SMI handler function prototypes */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 28ebdb6..5ff00db 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -76,4 +76,11 @@ config ME_MBP_CLEAR_LATE finalize step. This can speed up boot time if the ME takes a long time to indicate this status. +config FINALIZE_USB_ROUTE_XHCI + bool "Route all ports to XHCI controller in finalize step" + default y + help + If you set this option to y, the USB ports will be routed + to the XHCI controller during the finalize SMM callback. + endif diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c16c009..6e1b10c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -92,6 +92,7 @@ void intel_pch_finalize_smm(void); void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); void usb_ehci_disable(device_t dev); void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_route_all(void); #endif diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e920cfe..d1e9bbc 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -135,8 +135,10 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ-2); /* USB sleep preparations */ +#if !CONFIG_FINALIZE_USB_ROUTE_XHCI usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); +#endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); #if CONFIG_ELOG_GSMI @@ -314,6 +316,11 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; + case APM_CNT_FINALIZE: +#if CONFIG_FINALIZE_USB_ROUTE_XHCI + usb_xhci_route_all(); +#endif + break; #if CONFIG_ELOG_GSMI case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index df264e3..dbf0f40 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -26,8 +26,6 @@ #include <arch/io.h> #include "pch.h" -#ifdef __SMM__ - static u32 usb_xhci_mem_base(device_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -39,10 +37,6 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -#endif - -#if 0 - static int usb_xhci_port_count_usb3(device_t dev) { if (pch_is_lp()) { @@ -76,6 +70,8 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); } +#ifdef __SMM__ + #define XHCI_RESET_DELAY_US 1000 /* 1ms */ #define XHCI_RESET_TIMEOUT 100 /* 100ms */ @@ -155,10 +151,6 @@ static void usb_xhci_reset_usb3(device_t dev, int all) usb_xhci_reset_status_usb3(mem_base, port); } -#endif - -#ifdef __SMM__ - /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) { @@ -197,6 +189,47 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); } +/* Route all ports to XHCI controller */ +void usb_xhci_route_all(void) +{ + u32 port_mask, route; + u16 reg16; + + /* Skip if EHCI is already disabled */ + if (RCBA32(FD) & PCH_DISABLE_EHCI1) + return; + + /* Set D0 state */ + reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); + + /* Set USB3 superspeed enable */ + port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); + route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR); + route &= ~XHCI_USB3PR_SSEN; + route |= XHCI_USB3PR_SSEN & port_mask; + pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route); + + /* Route USB2 ports to XHCI controller */ + port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM); + route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR); + route &= ~XHCI_USB2PR_HCSEL; + route |= XHCI_USB2PR_HCSEL & port_mask; + pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route); + + /* Disable EHCI controller */ + usb_ehci_disable(PCH_EHCI1_DEV); + + /* LynxPoint-H has a second EHCI controller */ + if (!pch_is_lp()) + usb_ehci_disable(PCH_EHCI2_DEV); + + /* Reset and clear port change status */ + usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); +} + #else /* !__SMM__ */ static void usb_xhci_clock_gating(device_t dev) @@ -245,6 +278,49 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config32(dev, 0xa4, reg32); } +/* Re-enable ports that are disabled */ +static void usb_xhci_enable_ports_usb3(device_t dev) +{ +#if CONFIG_FINALIZE_USB_ROUTE_XHCI + int port; + u32 portsc, status, disabled; + u32 mem_base = usb_xhci_mem_base(dev); + int port_count = usb_xhci_port_count_usb3(dev); + + if (!mem_base || !port_count) + return; + + /* Get port disable override map */ + disabled = pci_read_config32(dev, XHCI_USB3PDO); + + for (port = 0; port < port_count; port++) { + /* Skip overridden ports */ + if (disabled & (1 << port)) + continue; + portsc = mem_base + XHCI_USB3_PORTSC(port); + status = read32(portsc) & XHCI_USB3_PORTSC_PLS; + + switch (status) { + case XHCI_PLSR_RXDETECT: + /* Clear change status */ + printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port); + usb_xhci_reset_status_usb3(mem_base, port); + break; + case XHCI_PLSR_DISABLED: + default: + /* Transition to enabled */ + printk(BIOS_DEBUG, "usb_xhci enable port %d\n", port); + usb_xhci_reset_port_usb3(mem_base, port); + status = read32(portsc); + status &= ~XHCI_USB3_PORTSC_PLS; + status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS; + write32(portsc, status); + break; + } + } +#endif +} + static void usb_xhci_init(device_t dev) { struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -313,6 +389,12 @@ static void usb_xhci_init(device_t dev) reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); + +#if CONFIG_HAVE_ACPI_RESUME + /* Enable ports that are disabled before returning to OS */ + if (acpi_slp_type == 3) + usb_xhci_enable_ports_usb3(dev); +#endif } static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,

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Patch set updated for coreboot: b13799f lynxpoint: Move USB SMI sleep code to separate USB files
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4406 -gerrit commit b13799f370e997d56d3ed733f903ef94f5bafd00 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 15:53:45 2013 -0700 lynxpoint: Move USB SMI sleep code to separate USB files Move this to the existing USB source files so they can share some helper functions and keep the main smihandler code cleaner. The XHCI sleep prepare code now implements the actual sleep preparation steps from the ref code instead of the docs. Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63800 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/pch.h | 51 +++++++- src/southbridge/intel/lynxpoint/smihandler.c | 97 +-------------- src/southbridge/intel/lynxpoint/usb_ehci.c | 115 ++++++++++++++++- src/southbridge/intel/lynxpoint/usb_xhci.c | 176 +++++++++++++++++++++++++++ 5 files changed, 340 insertions(+), 101 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 1689132..7be2d03 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -49,7 +49,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-y += reset.c early_spi.c rcba.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 32c7d9b..c16c009 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -89,6 +89,9 @@ #if defined (__SMM__) && !defined(__ASSEMBLER__) void intel_pch_finalize_smm(void); +void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_ehci_disable(device_t dev); +void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); #endif @@ -356,11 +359,49 @@ int early_pch_init(const void *gpio_map, #define SATA_DTLE_DATA_SHIFT 24 #define SATA_DTLE_EDGE_SHIFT 16 -/* USB Registers */ -#define EHCI_PWR_CNTL_STS 0x54 -#define EHCI_PWR_STS_MASK 0x3 -#define EHCI_PWR_STS_SET_D0 0x0 -#define EHCI_PWR_STS_SET_D3 0x3 +/* EHCI PCI Registers */ +#define EHCI_PWR_CTL_STS 0x54 +#define PWR_CTL_SET_MASK 0x3 +#define PWR_CTL_SET_D0 0x0 +#define PWR_CTL_SET_D3 0x3 +#define PWR_CTL_ENABLE_PME (1 << 8) + +/* EHCI Memory Registers */ +#define EHCI_USB_CMD 0x20 +#define EHCI_USB_CMD_RUN (1 << 0) +#define EHCI_USB_CMD_PSE (1 << 4) +#define EHCI_USB_CMD_ASE (1 << 5) +#define EHCI_PORTSC(port) (0x64 + (port * 4)) +#define EHCI_PORTSC_ENABLED (1 << 2) +#define EHCI_PORTSC_SUSPEND (1 << 7) + +/* XHCI PCI Registers */ +#define XHCI_PWR_CTL_STS 0x74 +#define XHCI_USB2PR 0xd0 +#define XHCI_USB2PRM 0xd4 +#define XHCI_USB2PR_HCSEL 0x7fff +#define XHCI_USB3PR 0xd8 +#define XHCI_USB3PR_SSEN 0x3f +#define XHCI_USB3PRM 0xdc +#define XHCI_USB3FUS 0xe0 +#define XHCI_USB3FUS_SS_MASK 3 +#define XHCI_USB3FUS_SS_SHIFT 3 +#define XHCI_USB3PDO 0xe8 + +/* XHCI Memory Registers */ +#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10)) +#define XHCI_USB3_PORTSC_CHST (0x7f << 17) +#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ +#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ +#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ +#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ +#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ +#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ +#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ +#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ +#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ /* Serial IO IOBP Registers */ #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index add53ed..e920cfe 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -106,97 +106,6 @@ static void busmaster_disable_on_bus(int bus) } } -/* Handler for EHCI controller on entry to S3/S4/S5 */ -static void ehci_sleep_prepare(device_t dev, u8 slp_typ) -{ - u32 reg32; - u32 bar0_base; - u16 pwr_state; - u16 pci_cmd; - - /* Check if the controller is disabled or not present */ - bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (bar0_base == 0 || bar0_base == 0xffffffff) - return; - pci_cmd = pci_read_config32(dev, PCI_COMMAND); - - switch (slp_typ) { - case SLP_TYP_S4: - case SLP_TYP_S5: - /* Check if controller is in D3 power state */ - pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); - if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { - /* Put in D0 */ - pwr_state &= ~EHCI_PWR_STS_MASK; - pwr_state |= EHCI_PWR_STS_SET_D0; - pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); - - /* Make sure memory bar is set */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); - - /* Make sure memory space is enabled */ - pci_write_config16(dev, PCI_COMMAND, pci_cmd | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - } - - /* - * If Run/Stop (bit0) is clear in USB2.0_CMD: - * - Clear Async Schedule Enable (bit5) and - * - Clear Periodic Schedule Enable (bit4) and - * - Set Run/Stop (bit0) - */ - reg32 = read32(bar0_base + 0x20); - if (reg32 & (1 << 0)) { - reg32 &= ~((1 << 5) | (1 << 4)); - reg32 |= (1 << 0); - write32(bar0_base + 0x20, reg32); - } - - /* Check for Port Enabled in PORTSC */ - reg32 = read32(bar0_base + 0x64); - if (reg32 & (1 << 2)) { - /* Set suspend bit in PORTSC if not already set */ - if (!(reg32 & (1 << 7))) { - reg32 |= (1 << 7); - write32(bar0_base + 0x64, reg32); - } - - /* Delay 25ms !! */ - udelay(25 * 1000); - - /* Clear Run/Stop bit */ - reg32 = read32(bar0_base + 0x20); - reg32 &= (1 << 0); - write32(bar0_base + 0x20, reg32); - } - - pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); - if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { - /* Restore pci command reg */ - pci_write_config16(dev, PCI_COMMAND, pci_cmd); - - /* Enable D3 */ - pwr_state |= EHCI_PWR_STS_SET_D3; - pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); - } - } -} - -/* Handler for XHCI controller on entry to S3/S4/S5 */ -static void xhci_sleep_prepare(device_t dev, u8 slp_typ) -{ - u16 reg16; - - switch (slp_typ) { - case SLP_TYP_S3: - case SLP_TYP_S4: - case SLP_TYP_S5: - /* Set D3Hot state and PME enable bit */ - reg16 = pci_read_config16(dev, 0x74); - reg16 |= (1 << 8) | (1 << 1) | (1 << 0); - pci_write_config16(dev, 0x74, reg16); - } -} static void southbridge_smi_sleep(void) { @@ -226,9 +135,9 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ-2); /* USB sleep preparations */ - ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); - ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); - xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); + usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); + usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); + usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index f06151b..4382611 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -19,12 +19,123 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "pch.h" #include <usbdebug.h> #include <arch/io.h> +#include "pch.h" + +#ifdef __SMM__ + +void usb_ehci_disable(device_t dev) +{ + u16 reg16; + u32 reg32; + + /* Set 0xDC[0]=1 */ + pci_or_config32(dev, 0xdc, (1 << 0)); + + /* Set D3Hot state and disable PME */ + reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS); + reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK); + reg16 |= PWR_CTL_SET_D3; + pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16); + + /* Clear memory and bus master */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable device */ + switch (dev) { + case PCH_EHCI1_DEV: + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCH_EHCI2_DEV: + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + } +} + +/* Handler for EHCI controller on entry to S3/S4/S5 */ +void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u32 reg32; + u32 bar0_base; + u16 pwr_state; + u16 pci_cmd; + + /* Check if the controller is disabled or not present */ + bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (bar0_base == 0 || bar0_base == 0xffffffff) + return; + pci_cmd = pci_read_config32(dev, PCI_COMMAND); + + switch (slp_typ) { + case SLP_TYP_S4: + case SLP_TYP_S5: + /* Check if controller is in D3 power state */ + pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS); + if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { + /* Put in D0 */ + u32 new_state = pwr_state & ~PWR_CTL_SET_MASK; + new_state |= PWR_CTL_SET_D0; + pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state); + + /* Make sure memory bar is set */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); + + /* Make sure memory space is enabled */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } + + /* + * If Run/Stop (bit0) is clear in USB2.0_CMD: + * - Clear Async Schedule Enable (bit5) and + * - Clear Periodic Schedule Enable (bit4) and + * - Set Run/Stop (bit0) + */ + reg32 = read32(bar0_base + EHCI_USB_CMD); + if (reg32 & EHCI_USB_CMD_RUN) { + reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE); + reg32 |= EHCI_USB_CMD_RUN; + write32(bar0_base + EHCI_USB_CMD, reg32); + } + + /* Check for Port Enabled in PORTSC(0) (RMH) */ + reg32 = read32(bar0_base + EHCI_PORTSC(0)); + if (reg32 & EHCI_PORTSC_ENABLED) { + /* Set suspend bit in PORTSC if not already set */ + if (!(reg32 & EHCI_PORTSC_SUSPEND)) { + reg32 |= EHCI_PORTSC_SUSPEND; + write32(bar0_base + EHCI_PORTSC(0), reg32); + } + + /* Delay 25ms !! */ + udelay(25 * 1000); + + /* Clear Run/Stop bit */ + reg32 = read32(bar0_base + EHCI_USB_CMD); + reg32 &= EHCI_USB_CMD_RUN; + write32(bar0_base + EHCI_USB_CMD, reg32); + } + + /* Restore state to D3 if that is what it was at the start */ + if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { + /* Restore pci command reg */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd); + + /* Enable D3 */ + pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state); + } + } +} + +#else /* !__SMM__ */ static void usb_ehci_clock_gating(struct device *dev) { @@ -98,3 +209,5 @@ static const struct pci_driver pch_usb_ehci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 33f33f4..df264e3 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -18,12 +18,187 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <arch/io.h> #include "pch.h" +#ifdef __SMM__ + +static u32 usb_xhci_mem_base(device_t dev) +{ + u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + + /* Check if the controller is disabled or not present */ + if (mem_base == 0 || mem_base == 0xffffffff) + return 0; + + return mem_base & ~0xf; +} + +#endif + +#if 0 + +static int usb_xhci_port_count_usb3(device_t dev) +{ + if (pch_is_lp()) { + /* LynxPoint-LP has 4 SS ports */ + return 4; + } else { + /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ + u32 mem_base = usb_xhci_mem_base(dev); + u32 fus = read32(mem_base + XHCI_USB3FUS); + fus >>= XHCI_USB3FUS_SS_SHIFT; + fus &= XHCI_USB3FUS_SS_MASK; + switch (fus) { + case 3: return 0; + case 2: return 2; + case 1: return 4; + case 0: default: return 6; + } + } + return 0; +} + +static void usb_xhci_reset_status_usb3(u32 mem_base, int port) +{ + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_CHST); +} + +static void usb_xhci_reset_port_usb3(u32 mem_base, int port) +{ + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); +} + +#define XHCI_RESET_DELAY_US 1000 /* 1ms */ +#define XHCI_RESET_TIMEOUT 100 /* 100ms */ + +/* + * 1) Wait until port is done polling + * 2) If port is disconnected + * a) Issue warm port reset + * b) Poll for warm reset complete + * c) Write 1 to port change status bits + */ +static void usb_xhci_reset_usb3(device_t dev, int all) +{ + u32 status, port_disabled; + int timeout, port; + int port_count = usb_xhci_port_count_usb3(dev); + u32 mem_base = usb_xhci_mem_base(dev); + + if (!mem_base || !port_count) + return; + + /* Get mask of disabled ports */ + port_disabled = pci_read_config32(dev, XHCI_USB3PDO); + + /* Wait until all enabled ports are done polling */ + for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { + int complete = 1; + for (port = 0; port < port_count; port++) { + /* Skip disabled ports */ + if (port_disabled & (1 << port)) + continue; + /* Read port link status field */ + status = read32(mem_base + XHCI_USB3_PORTSC(port)); + status &= XHCI_USB3_PORTSC_PLS; + if (status == XHCI_PLSR_POLLING) + complete = 0; + } + /* Exit if all ports not polling */ + if (complete) + break; + udelay(XHCI_RESET_DELAY_US); + } + + /* Reset all requested ports */ + for (port = 0; port < port_count; port++) { + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + /* Skip disabled ports */ + if (port_disabled & (1 << port)) + continue; + status = read32(portsc) & XHCI_USB3_PORTSC_PLS; + /* Reset all or only disconnected ports */ + if (all || status == XHCI_PLSR_RXDETECT) + usb_xhci_reset_port_usb3(mem_base, port); + else + port_disabled |= 1 << port; /* No reset */ + } + + /* Wait for warm reset complete on all reset ports */ + for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { + int complete = 1; + for (port = 0; port < port_count; port++) { + /* Only check ports that were reset */ + if (port_disabled & (1 << port)) + continue; + /* Check if warm reset is complete */ + status = read32(mem_base + XHCI_USB3_PORTSC(port)); + if (!(status & XHCI_USB3_PORTSC_WRC)) + complete = 0; + } + /* Check for warm reset complete in any port */ + if (complete) + break; + udelay(XHCI_RESET_DELAY_US); + } + + /* Clear port change status bits */ + for (port = 0; port < port_count; port++) + usb_xhci_reset_status_usb3(mem_base, port); +} + +#endif + +#ifdef __SMM__ + +/* Handler for XHCI controller on entry to S3/S4/S5 */ +void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u16 reg16; + u32 reg32; + u32 mem_base = usb_xhci_mem_base(dev); + + if (!mem_base || slp_typ < 3) + return; + + if (pch_is_lp()) { + /* Set D0 state */ + reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + + /* Clear PCI 0xB0[14:13] */ + reg32 = pci_read_config32(dev, 0xb0); + reg32 &= ~((1 << 14) | (1 << 13)); + pci_write_config32(dev, 0xb0, reg32); + + /* Clear MMIO 0x816c[14,2] */ + reg32 = read32(mem_base + 0x816c); + reg32 &= ~((1 << 14) | (1 << 2)); + write32(mem_base + 0x816c, reg32); + + /* Set MMIO 0x80e0[15] */ + reg32 = read32(mem_base + 0x80e0); + reg32 |= (1 << 15); + write32(mem_base + 0x80e0, reg32); + } + + /* Set D3Hot state and enable PME */ + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); +} + +#else /* !__SMM__ */ + static void usb_xhci_clock_gating(device_t dev) { u32 reg32; @@ -173,3 +348,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; +#endif /* !__SMM__ */

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Patch set updated for coreboot: 0d1694f lynxpoint: XHCI: Don't put device in D3 in _PS0 Method
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4448 -gerrit commit 0d1694fd6a1431940f8a1d9dc8b4746babd203e6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 8 14:12:20 2013 -0700 lynxpoint: XHCI: Don't put device in D3 in _PS0 Method The end of the _PS0 method that is supposed to transition the XHCI device to D0 state is instead putting it in D3 state. This triggers a PME_B0 GPE which causes a Notify to the XHCI ACPI Device in the kernel and that increments the wakeup counter and causes aborted suspends. Instead if we just leave the device in D0 where it should be after executing this function then the PME_B0 is not generated and the kernel does not see a wakeup on XHCI. Similarly I changed the _PS3 method to always put the device in D3 at the end of the method, rather than depending on the state to be D3 at the start. Before this change the kernel would see the following sequence when trying to suspend when the XHCI controller is in D3cold: kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8 kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: PM: Wakeup pending, aborting suspend kernel: last active wakeup source: 0000:00:14.0 Now it does not get a notification (due to PME_B0) when going to D0 on the way into suspend. XHCI goes from D3cold to D0 (in order to be able to read mmio) and then back to D3hot before suspend. kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000) kernel: xhci_hcd 0000:00:14.0: PME# enabled kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65236 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/usb.asl | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 2fe6750..9c9b6b0 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -309,11 +309,6 @@ Device (XHCI) Store (1, AX15) } - // Put device in D3 if it was there originally - If (LEqual (Local0, 3)) { - Store (3, ^D0D3) - } - Return () } @@ -371,9 +366,7 @@ Device (XHCI) } // Put device in D3 - If (LEqual (Local0, 3)) { - Store (3, ^D0D3) - } + Store (3, ^D0D3) Return () }

1 0

Patch set updated for coreboot: 12845d8 lynxpoint: Fix an issue clearing port change status bits
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4473 -gerrit commit 12845d880eccb0df53cb04c9702de88f9af461e9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Aug 13 13:32:28 2013 -0700 lynxpoint: Fix an issue clearing port change status bits The coreboot and ACPI code that clears USB3 PORTSC change status bits was not properly preserving the state of the PED (port enabled or disabled) status bit, and it could write 0 back to this field which would disable the port. Additionally add back the code that resets disconnected USB3 ports on the way into suspend (as stated in the BWG) but take care to clear the PME status bit so we don't immediately wake. suspend/resume with USB3 devices 1) suspend with no devices, plug in while suspended, then resume and verify that the devices are detected 2) suspend with USB3 devices inserted, then suspend and resume and verify that the devices are detected 3) suspend with USB3 devices inserted, then remove the devices while suspended, resume and ensure they can be detected again when inserted after resume Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65733 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/usb.asl | 37 +++++++++++++++++++--------- src/southbridge/intel/lynxpoint/pch.h | 2 ++ src/southbridge/intel/lynxpoint/usb_xhci.c | 11 ++++++++- 3 files changed, 37 insertions(+), 13 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index c22dbb8..2fe6750 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -106,23 +106,36 @@ Device (XHCI) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3[0] - , 17, - CLR1, 7, // Status Change bits 23:17 + PSC0, 32, Offset (0x520), // PORTSCNUSB3[1] - , 17, - CLR2, 7, // Status Change Bits 23:17 + PSC1, 32, Offset (0x530), // PORTSCNUSB3[2] - , 17, - CLR3, 7, // Status Change Bits 23:17 + PSC2, 32, Offset (0x540), // PORTSCNUSB3[3] - , 17, - CLR4, 7, // Status Change Bits 23:17 + PSC3, 32, } - Store (0x7f, CLR1) - Store (0x7f, CLR2) - Store (0x7f, CLR3) - Store (0x7f, CLR4) + // Port Enabled/Disabled (Bit 1) + Name (PEDB, ShiftLeft (1, 1)) + + // Change Status (Bits 23:17) + Name (CHST, ShiftLeft (0x7f, 17)) + + // Port 0 + And (PSC0, Not (PEDB), Local0) + Or (Local0, CHST, PSC0) + + // Port 1 + And (PSC1, Not (PEDB), Local0) + Or (Local0, CHST, PSC1) + + // Port 2 + And (PSC2, Not (PEDB), Local0) + Or (Local0, CHST, PSC2) + + // Port 3 + And (PSC3, Not (PEDB), Local0) + Or (Local0, CHST, PSC3) } Method (LPS0, 0, Serialized) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6e1b10c..3396367 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -366,6 +366,7 @@ int early_pch_init(const void *gpio_map, #define PWR_CTL_SET_D0 0x0 #define PWR_CTL_SET_D3 0x3 #define PWR_CTL_ENABLE_PME (1 << 8) +#define PWR_CTL_STATUS_PME (1 << 15) /* EHCI Memory Registers */ #define EHCI_USB_CMD 0x20 @@ -397,6 +398,7 @@ int early_pch_init(const void *gpio_map, #define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ #define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 1e81065..212dec6 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -63,7 +63,12 @@ static int usb_xhci_port_count_usb3(device_t dev) static void usb_xhci_reset_status_usb3(u32 mem_base, int port) { u32 portsc = mem_base + XHCI_USB3_PORTSC(port); - write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_CHST); + u32 status = read32(portsc); + /* Do not set Port Enabled/Disabled field */ + status &= ~XHCI_USB3_PORTSC_PED; + /* Clear all change status bits */ + status |= XHCI_USB3_PORTSC_CHST; + write32(portsc, status); } static void usb_xhci_reset_port_usb3(u32 mem_base, int port) @@ -178,6 +183,9 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) reg32 &= ~((1 << 14) | (1 << 2)); write32(mem_base + 0x816c, reg32); + /* Reset disconnected USB3 ports */ + usb_xhci_reset_usb3(dev, 0); + /* Set MMIO 0x80e0[15] */ reg32 = read32(mem_base + 0x80e0); reg32 |= (1 << 15); @@ -186,6 +194,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) /* Set D3Hot state and enable PME */ pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME); pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); }

1 0

Patch set updated for coreboot: ed1eec1 lynxpoint: XHCI: Advertise D3 as lowest wake state
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4409 -gerrit commit ed1eec1a20b1602b0c8cf104eab64860c99b3f6a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 16:15:14 2013 -0700 lynxpoint: XHCI: Advertise D3 as lowest wake state The recommended value in docs is D2, but lynxpoint XHCI does not even support D2 state which causes the kernel to think this device cannot be used as a wake source: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Device does not support D2 kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI Additionally this means the kernel will never put the device into D3 state by itself. There is SMI code that will put the device into D3 before suspend so advertising D3 here should be correct. With this change the kernel will put the controller into D3 on suspend and back to D0 on resume, including executing the ACPI methods for _PS0/_PS3 that contain chipset specific workarounds. In addition add a _PSC method to directly return the D state from the device registers. With ALL USB devices removed the XHCI controller goes into D3 state and the kernel can have a hard time determining the state of the device at boot. A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see what ACPI methods are executed: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50) kernel: ACPI: Preparing to enter system sleep state S3 ... kernel: ACPI: Waking up from system sleep state S3 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> meld with s3d Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472 Reviewed-on: https://gerrit.chromium.org/gerrit/63916 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/usb.asl | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 1a0ad34..c22dbb8 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -238,6 +238,11 @@ Device (XHCI) LPCL () } + Method (_PSC, 0, NotSerialized) + { + Return (^D0D3) + } + Method (_PS0, 0, Serialized) { If (LEqual (^DVID, 0xFFFF)) { @@ -375,12 +380,12 @@ Device (XHCI) Method(_S3D,0) // Highest D State in S3 State { - Return (2) + Return (3) } Method(_S4D,0) // Highest D State in S4 State { - Return (2) + Return (3) } Device (HUB7)

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Patch set updated for coreboot: b814220 lynxpoint: Fix issues with XHCI init
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4408 -gerrit commit b8142207016043faa8db53163f62adb281f71076 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 15:58:18 2013 -0700 lynxpoint: Fix issues with XHCI init - Put the device into D0 and not D3 so memory bar is available and the subsequent commands actually do something useful - Remove set of 818Ch[7:0]=FFh (gone in ref code) - Fix reg 0x40/0x44 mixup Verify that expected bits are set: localhost ~ # pci_read32 0 0x14 0 0x10 0xe0500004 localhost ~ # mmio_read32 0xe0508144 0x000003ff localhost ~ # mmio_read32 0xe050816c 0x000f0038 Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63801 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/usb_xhci.c | 39 +++++++++++++----------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index e7f7039..1e81065 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -235,6 +235,7 @@ void usb_xhci_route_all(void) static void usb_xhci_clock_gating(device_t dev) { u32 reg32; + u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); @@ -258,9 +259,9 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ - reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1 << 9) | (1 << 7) | (1 << 3); - pci_write_config32(dev, 0x44, reg32); + reg16 = pci_read_config16(dev, 0x44); + reg16 |= (1 << 9) | (1 << 7) | (1 << 3); + pci_write_config16(dev, 0x44, reg16); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { @@ -323,21 +324,20 @@ static void usb_xhci_enable_ports_usb3(device_t dev) static void usb_xhci_init(device_t dev) { - struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); u32 reg32; + u16 reg16; + u32 mem_base = usb_xhci_mem_base(dev); - if (!bar0 || bar0->base == 0 || bar0->base == 0xffffffff) - return; + /* D20:F0:74h[1:0] = 00b (set D0 state) */ + reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Enable clock gating first */ usb_xhci_clock_gating(dev); - /* D20:F0:74h[1:0] = 11b (set D3Hot state) */ - reg32 = pci_read_config16(dev, 0x74); - reg32 |= (1 << 1) | (1 << 0); - pci_write_config16(dev, 0x74, reg32); - - reg32 = read32(bar0->base + 0x8144); + reg32 = read32(mem_base + 0x8144); if (pch_is_lp()) { /* XHCIBAR + 8144h[8,7,6] = 111b */ reg32 |= (1 << 8) | (1 << 7) | (1 << 6); @@ -346,25 +346,20 @@ static void usb_xhci_init(device_t dev) reg32 &= ~((1 << 7) | (1 << 6)); reg32 |= (1 << 8); } - write32(bar0->base + 0x8144, reg32); + write32(mem_base + 0x8144, reg32); if (pch_is_lp()) { /* XHCIBAR + 816Ch[19:0] = 000f0038h */ - reg32 = read32(bar0->base + 0x816c); + reg32 = read32(mem_base + 0x816c); reg32 &= ~0x000fffff; reg32 |= 0x000f0038; - write32(bar0->base + 0x816c, reg32); + write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); reg32 |= (1 << 17); pci_write_config32(dev, 0xb0, reg32); - - /* XHCIBAR + 818Ch[7:0] = FFh */ - reg32 = read32(bar0->base + 0x818c); - reg32 |= 0xff; - write32(bar0->base + 0x818c, reg32); } reg32 = pci_read_config32(dev, 0x50); @@ -380,9 +375,9 @@ static void usb_xhci_init(device_t dev) pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ - reg32 = pci_read_config32(dev, 0x40); + reg32 = pci_read_config32(dev, 0x44); reg32 |= (1 << 31); - pci_write_config32(dev, 0x40, reg32); + pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40);

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Patch set updated for coreboot: 3674484 lynxpoint: Route all USB ports to XHCI in finalize step
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4407 -gerrit commit 3674484fff17c8bed24800482590fad436bdcc7f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 16:05:55 2013 -0700 lynxpoint: Route all USB ports to XHCI in finalize step This commit adds a new Kconfig option for the LynxPoint southbridge that will have coreboot route all of the USB ports to the XHCI controller in the finalize step (i.e. after the bootloader) and disable the EHCI controller(s). Additionally when doing this the XHCI USB3 ports need to be put into an expected state on resume in order to make the kernel state machine happy. Part of this could also be done in depthcharge but there are also some resume-time steps required so it makes sense to keep it all together in coreboot. This can theoretically save ~100mW at runtime. Verify that the EHCI controller is not found in Linux and that booting from USB still works. Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63802 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/smm.h | 1 + src/southbridge/intel/lynxpoint/Kconfig | 7 +++ src/southbridge/intel/lynxpoint/pch.h | 1 + src/southbridge/intel/lynxpoint/smihandler.c | 7 +++ src/southbridge/intel/lynxpoint/usb_xhci.c | 90 ++++++++++++++++++++++++++++ 5 files changed, 106 insertions(+) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 607c0f0..feb50ec 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -372,6 +372,7 @@ typedef struct { #define APM_CNT_ACPI_ENABLE 0xe1 #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_GNVS_UPDATE 0xea +#define APM_CNT_FINALIZE 0xcb #define APM_STS 0xb3 /* SMI handler function prototypes */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 28ebdb6..5ff00db 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -76,4 +76,11 @@ config ME_MBP_CLEAR_LATE finalize step. This can speed up boot time if the ME takes a long time to indicate this status. +config FINALIZE_USB_ROUTE_XHCI + bool "Route all ports to XHCI controller in finalize step" + default y + help + If you set this option to y, the USB ports will be routed + to the XHCI controller during the finalize SMM callback. + endif diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c16c009..6e1b10c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -92,6 +92,7 @@ void intel_pch_finalize_smm(void); void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); void usb_ehci_disable(device_t dev); void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_route_all(void); #endif diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e920cfe..d1e9bbc 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -135,8 +135,10 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ-2); /* USB sleep preparations */ +#if !CONFIG_FINALIZE_USB_ROUTE_XHCI usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); +#endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); #if CONFIG_ELOG_GSMI @@ -314,6 +316,11 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; + case APM_CNT_FINALIZE: +#if CONFIG_FINALIZE_USB_ROUTE_XHCI + usb_xhci_route_all(); +#endif + break; #if CONFIG_ELOG_GSMI case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index b699916..e7f7039 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -189,6 +189,47 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); } +/* Route all ports to XHCI controller */ +void usb_xhci_route_all(void) +{ + u32 port_mask, route; + u16 reg16; + + /* Skip if EHCI is already disabled */ + if (RCBA32(FD) & PCH_DISABLE_EHCI1) + return; + + /* Set D0 state */ + reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); + + /* Set USB3 superspeed enable */ + port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); + route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR); + route &= ~XHCI_USB3PR_SSEN; + route |= XHCI_USB3PR_SSEN & port_mask; + pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route); + + /* Route USB2 ports to XHCI controller */ + port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM); + route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR); + route &= ~XHCI_USB2PR_HCSEL; + route |= XHCI_USB2PR_HCSEL & port_mask; + pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route); + + /* Disable EHCI controller */ + usb_ehci_disable(PCH_EHCI1_DEV); + + /* LynxPoint-H has a second EHCI controller */ + if (!pch_is_lp()) + usb_ehci_disable(PCH_EHCI2_DEV); + + /* Reset and clear port change status */ + usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); +} + #else /* !__SMM__ */ static void usb_xhci_clock_gating(device_t dev) @@ -237,6 +278,49 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config32(dev, 0xa4, reg32); } +/* Re-enable ports that are disabled */ +static void usb_xhci_enable_ports_usb3(device_t dev) +{ +#if CONFIG_FINALIZE_USB_ROUTE_XHCI + int port; + u32 portsc, status, disabled; + u32 mem_base = usb_xhci_mem_base(dev); + int port_count = usb_xhci_port_count_usb3(dev); + + if (!mem_base || !port_count) + return; + + /* Get port disable override map */ + disabled = pci_read_config32(dev, XHCI_USB3PDO); + + for (port = 0; port < port_count; port++) { + /* Skip overridden ports */ + if (disabled & (1 << port)) + continue; + portsc = mem_base + XHCI_USB3_PORTSC(port); + status = read32(portsc) & XHCI_USB3_PORTSC_PLS; + + switch (status) { + case XHCI_PLSR_RXDETECT: + /* Clear change status */ + printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port); + usb_xhci_reset_status_usb3(mem_base, port); + break; + case XHCI_PLSR_DISABLED: + default: + /* Transition to enabled */ + printk(BIOS_DEBUG, "usb_xhci enable port %d\n", port); + usb_xhci_reset_port_usb3(mem_base, port); + status = read32(portsc); + status &= ~XHCI_USB3_PORTSC_PLS; + status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS; + write32(portsc, status); + break; + } + } +#endif +} + static void usb_xhci_init(device_t dev) { struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -305,6 +389,12 @@ static void usb_xhci_init(device_t dev) reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); + +#if CONFIG_HAVE_ACPI_RESUME + /* Enable ports that are disabled before returning to OS */ + if (acpi_slp_type == 3) + usb_xhci_enable_ports_usb3(dev); +#endif } static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,

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Patch set updated for coreboot: 68da9b2 lynxpoint: Move USB SMI sleep code to separate USB files
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4406 -gerrit commit 68da9b2884ba8b6a7a7f99d9065b4df441e8cf01 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 15:53:45 2013 -0700 lynxpoint: Move USB SMI sleep code to separate USB files Move this to the existing USB source files so they can share some helper functions and keep the main smihandler code cleaner. The XHCI sleep prepare code now implements the actual sleep preparation steps from the ref code instead of the docs. Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63800 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/pch.h | 51 +++++++- src/southbridge/intel/lynxpoint/smihandler.c | 97 +--------------- src/southbridge/intel/lynxpoint/usb_ehci.c | 113 ++++++++++++++++++ src/southbridge/intel/lynxpoint/usb_xhci.c | 168 +++++++++++++++++++++++++++ 5 files changed, 331 insertions(+), 100 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 1689132..7be2d03 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -49,7 +49,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-y += reset.c early_spi.c rcba.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 32c7d9b..c16c009 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -89,6 +89,9 @@ #if defined (__SMM__) && !defined(__ASSEMBLER__) void intel_pch_finalize_smm(void); +void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_ehci_disable(device_t dev); +void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); #endif @@ -356,11 +359,49 @@ int early_pch_init(const void *gpio_map, #define SATA_DTLE_DATA_SHIFT 24 #define SATA_DTLE_EDGE_SHIFT 16 -/* USB Registers */ -#define EHCI_PWR_CNTL_STS 0x54 -#define EHCI_PWR_STS_MASK 0x3 -#define EHCI_PWR_STS_SET_D0 0x0 -#define EHCI_PWR_STS_SET_D3 0x3 +/* EHCI PCI Registers */ +#define EHCI_PWR_CTL_STS 0x54 +#define PWR_CTL_SET_MASK 0x3 +#define PWR_CTL_SET_D0 0x0 +#define PWR_CTL_SET_D3 0x3 +#define PWR_CTL_ENABLE_PME (1 << 8) + +/* EHCI Memory Registers */ +#define EHCI_USB_CMD 0x20 +#define EHCI_USB_CMD_RUN (1 << 0) +#define EHCI_USB_CMD_PSE (1 << 4) +#define EHCI_USB_CMD_ASE (1 << 5) +#define EHCI_PORTSC(port) (0x64 + (port * 4)) +#define EHCI_PORTSC_ENABLED (1 << 2) +#define EHCI_PORTSC_SUSPEND (1 << 7) + +/* XHCI PCI Registers */ +#define XHCI_PWR_CTL_STS 0x74 +#define XHCI_USB2PR 0xd0 +#define XHCI_USB2PRM 0xd4 +#define XHCI_USB2PR_HCSEL 0x7fff +#define XHCI_USB3PR 0xd8 +#define XHCI_USB3PR_SSEN 0x3f +#define XHCI_USB3PRM 0xdc +#define XHCI_USB3FUS 0xe0 +#define XHCI_USB3FUS_SS_MASK 3 +#define XHCI_USB3FUS_SS_SHIFT 3 +#define XHCI_USB3PDO 0xe8 + +/* XHCI Memory Registers */ +#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10)) +#define XHCI_USB3_PORTSC_CHST (0x7f << 17) +#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ +#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ +#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ +#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ +#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ +#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ +#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ +#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ +#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ /* Serial IO IOBP Registers */ #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index add53ed..e920cfe 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -106,97 +106,6 @@ static void busmaster_disable_on_bus(int bus) } } -/* Handler for EHCI controller on entry to S3/S4/S5 */ -static void ehci_sleep_prepare(device_t dev, u8 slp_typ) -{ - u32 reg32; - u32 bar0_base; - u16 pwr_state; - u16 pci_cmd; - - /* Check if the controller is disabled or not present */ - bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (bar0_base == 0 || bar0_base == 0xffffffff) - return; - pci_cmd = pci_read_config32(dev, PCI_COMMAND); - - switch (slp_typ) { - case SLP_TYP_S4: - case SLP_TYP_S5: - /* Check if controller is in D3 power state */ - pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); - if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { - /* Put in D0 */ - pwr_state &= ~EHCI_PWR_STS_MASK; - pwr_state |= EHCI_PWR_STS_SET_D0; - pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); - - /* Make sure memory bar is set */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); - - /* Make sure memory space is enabled */ - pci_write_config16(dev, PCI_COMMAND, pci_cmd | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - } - - /* - * If Run/Stop (bit0) is clear in USB2.0_CMD: - * - Clear Async Schedule Enable (bit5) and - * - Clear Periodic Schedule Enable (bit4) and - * - Set Run/Stop (bit0) - */ - reg32 = read32(bar0_base + 0x20); - if (reg32 & (1 << 0)) { - reg32 &= ~((1 << 5) | (1 << 4)); - reg32 |= (1 << 0); - write32(bar0_base + 0x20, reg32); - } - - /* Check for Port Enabled in PORTSC */ - reg32 = read32(bar0_base + 0x64); - if (reg32 & (1 << 2)) { - /* Set suspend bit in PORTSC if not already set */ - if (!(reg32 & (1 << 7))) { - reg32 |= (1 << 7); - write32(bar0_base + 0x64, reg32); - } - - /* Delay 25ms !! */ - udelay(25 * 1000); - - /* Clear Run/Stop bit */ - reg32 = read32(bar0_base + 0x20); - reg32 &= (1 << 0); - write32(bar0_base + 0x20, reg32); - } - - pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); - if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { - /* Restore pci command reg */ - pci_write_config16(dev, PCI_COMMAND, pci_cmd); - - /* Enable D3 */ - pwr_state |= EHCI_PWR_STS_SET_D3; - pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); - } - } -} - -/* Handler for XHCI controller on entry to S3/S4/S5 */ -static void xhci_sleep_prepare(device_t dev, u8 slp_typ) -{ - u16 reg16; - - switch (slp_typ) { - case SLP_TYP_S3: - case SLP_TYP_S4: - case SLP_TYP_S5: - /* Set D3Hot state and PME enable bit */ - reg16 = pci_read_config16(dev, 0x74); - reg16 |= (1 << 8) | (1 << 1) | (1 << 0); - pci_write_config16(dev, 0x74, reg16); - } -} static void southbridge_smi_sleep(void) { @@ -226,9 +135,9 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ-2); /* USB sleep preparations */ - ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); - ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); - xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); + usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); + usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); + usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index f06151b..7a3698c 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -19,6 +19,7 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -26,6 +27,116 @@ #include <usbdebug.h> #include <arch/io.h> +#ifdef __SMM__ + +void usb_ehci_disable(device_t dev) +{ + u16 reg16; + u32 reg32; + + /* Set 0xDC[0]=1 */ + pci_or_config32(dev, 0xdc, (1 << 0)); + + /* Set D3Hot state and disable PME */ + reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS); + reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK); + reg16 |= PWR_CTL_SET_D3; + pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16); + + /* Clear memory and bus master */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable device */ + switch (dev) { + case PCH_EHCI1_DEV: + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCH_EHCI2_DEV: + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + } +} + +/* Handler for EHCI controller on entry to S3/S4/S5 */ +void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u32 reg32; + u32 bar0_base; + u16 pwr_state; + u16 pci_cmd; + + /* Check if the controller is disabled or not present */ + bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (bar0_base == 0 || bar0_base == 0xffffffff) + return; + pci_cmd = pci_read_config32(dev, PCI_COMMAND); + + switch (slp_typ) { + case SLP_TYP_S4: + case SLP_TYP_S5: + /* Check if controller is in D3 power state */ + pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS); + if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { + /* Put in D0 */ + u32 new_state = pwr_state & ~PWR_CTL_SET_MASK; + new_state |= PWR_CTL_SET_D0; + pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state); + + /* Make sure memory bar is set */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); + + /* Make sure memory space is enabled */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } + + /* + * If Run/Stop (bit0) is clear in USB2.0_CMD: + * - Clear Async Schedule Enable (bit5) and + * - Clear Periodic Schedule Enable (bit4) and + * - Set Run/Stop (bit0) + */ + reg32 = read32(bar0_base + EHCI_USB_CMD); + if (reg32 & EHCI_USB_CMD_RUN) { + reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE); + reg32 |= EHCI_USB_CMD_RUN; + write32(bar0_base + EHCI_USB_CMD, reg32); + } + + /* Check for Port Enabled in PORTSC(0) (RMH) */ + reg32 = read32(bar0_base + EHCI_PORTSC(0)); + if (reg32 & EHCI_PORTSC_ENABLED) { + /* Set suspend bit in PORTSC if not already set */ + if (!(reg32 & EHCI_PORTSC_SUSPEND)) { + reg32 |= EHCI_PORTSC_SUSPEND; + write32(bar0_base + EHCI_PORTSC(0), reg32); + } + + /* Delay 25ms !! */ + udelay(25 * 1000); + + /* Clear Run/Stop bit */ + reg32 = read32(bar0_base + EHCI_USB_CMD); + reg32 &= EHCI_USB_CMD_RUN; + write32(bar0_base + EHCI_USB_CMD, reg32); + } + + /* Restore state to D3 if that is what it was at the start */ + if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { + /* Restore pci command reg */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd); + + /* Enable D3 */ + pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state); + } + } +} + +#else /* !__SMM__ */ + static void usb_ehci_clock_gating(struct device *dev) { u32 reg32; @@ -98,3 +209,5 @@ static const struct pci_driver pch_usb_ehci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 33f33f4..b699916 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -18,12 +18,179 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <arch/io.h> #include "pch.h" +static u32 usb_xhci_mem_base(device_t dev) +{ + u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + + /* Check if the controller is disabled or not present */ + if (mem_base == 0 || mem_base == 0xffffffff) + return 0; + + return mem_base & ~0xf; +} + +#ifdef __SMM__ + +static int usb_xhci_port_count_usb3(device_t dev) +{ + if (pch_is_lp()) { + /* LynxPoint-LP has 4 SS ports */ + return 4; + } else { + /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ + u32 mem_base = usb_xhci_mem_base(dev); + u32 fus = read32(mem_base + XHCI_USB3FUS); + fus >>= XHCI_USB3FUS_SS_SHIFT; + fus &= XHCI_USB3FUS_SS_MASK; + switch (fus) { + case 3: return 0; + case 2: return 2; + case 1: return 4; + case 0: default: return 6; + } + } + return 0; +} + +static void usb_xhci_reset_status_usb3(u32 mem_base, int port) +{ + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_CHST); +} + +static void usb_xhci_reset_port_usb3(u32 mem_base, int port) +{ + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); +} + +#define XHCI_RESET_DELAY_US 1000 /* 1ms */ +#define XHCI_RESET_TIMEOUT 100 /* 100ms */ + +/* + * 1) Wait until port is done polling + * 2) If port is disconnected + * a) Issue warm port reset + * b) Poll for warm reset complete + * c) Write 1 to port change status bits + */ +static void usb_xhci_reset_usb3(device_t dev, int all) +{ + u32 status, port_disabled; + int timeout, port; + int port_count = usb_xhci_port_count_usb3(dev); + u32 mem_base = usb_xhci_mem_base(dev); + + if (!mem_base || !port_count) + return; + + /* Get mask of disabled ports */ + port_disabled = pci_read_config32(dev, XHCI_USB3PDO); + + /* Wait until all enabled ports are done polling */ + for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { + int complete = 1; + for (port = 0; port < port_count; port++) { + /* Skip disabled ports */ + if (port_disabled & (1 << port)) + continue; + /* Read port link status field */ + status = read32(mem_base + XHCI_USB3_PORTSC(port)); + status &= XHCI_USB3_PORTSC_PLS; + if (status == XHCI_PLSR_POLLING) + complete = 0; + } + /* Exit if all ports not polling */ + if (complete) + break; + udelay(XHCI_RESET_DELAY_US); + } + + /* Reset all requested ports */ + for (port = 0; port < port_count; port++) { + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + /* Skip disabled ports */ + if (port_disabled & (1 << port)) + continue; + status = read32(portsc) & XHCI_USB3_PORTSC_PLS; + /* Reset all or only disconnected ports */ + if (all || status == XHCI_PLSR_RXDETECT) + usb_xhci_reset_port_usb3(mem_base, port); + else + port_disabled |= 1 << port; /* No reset */ + } + + /* Wait for warm reset complete on all reset ports */ + for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { + int complete = 1; + for (port = 0; port < port_count; port++) { + /* Only check ports that were reset */ + if (port_disabled & (1 << port)) + continue; + /* Check if warm reset is complete */ + status = read32(mem_base + XHCI_USB3_PORTSC(port)); + if (!(status & XHCI_USB3_PORTSC_WRC)) + complete = 0; + } + /* Check for warm reset complete in any port */ + if (complete) + break; + udelay(XHCI_RESET_DELAY_US); + } + + /* Clear port change status bits */ + for (port = 0; port < port_count; port++) + usb_xhci_reset_status_usb3(mem_base, port); +} + +/* Handler for XHCI controller on entry to S3/S4/S5 */ +void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u16 reg16; + u32 reg32; + u32 mem_base = usb_xhci_mem_base(dev); + + if (!mem_base || slp_typ < 3) + return; + + if (pch_is_lp()) { + /* Set D0 state */ + reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + + /* Clear PCI 0xB0[14:13] */ + reg32 = pci_read_config32(dev, 0xb0); + reg32 &= ~((1 << 14) | (1 << 13)); + pci_write_config32(dev, 0xb0, reg32); + + /* Clear MMIO 0x816c[14,2] */ + reg32 = read32(mem_base + 0x816c); + reg32 &= ~((1 << 14) | (1 << 2)); + write32(mem_base + 0x816c, reg32); + + /* Set MMIO 0x80e0[15] */ + reg32 = read32(mem_base + 0x80e0); + reg32 |= (1 << 15); + write32(mem_base + 0x80e0, reg32); + } + + /* Set D3Hot state and enable PME */ + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); +} + +#else /* !__SMM__ */ + static void usb_xhci_clock_gating(device_t dev) { u32 reg32; @@ -173,3 +340,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; +#endif /* !__SMM__ */

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Patch set updated for coreboot: 1a6b8f7 lynxpoint: XHCI: Don't put device in D3 in _PS0 Method
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4448 -gerrit commit 1a6b8f72c85eda47829777c2665fa220385f7cb4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 8 14:12:20 2013 -0700 lynxpoint: XHCI: Don't put device in D3 in _PS0 Method The end of the _PS0 method that is supposed to transition the XHCI device to D0 state is instead putting it in D3 state. This triggers a PME_B0 GPE which causes a Notify to the XHCI ACPI Device in the kernel and that increments the wakeup counter and causes aborted suspends. Instead if we just leave the device in D0 where it should be after executing this function then the PME_B0 is not generated and the kernel does not see a wakeup on XHCI. Similarly I changed the _PS3 method to always put the device in D3 at the end of the method, rather than depending on the state to be D3 at the start. Before this change the kernel would see the following sequence when trying to suspend when the XHCI controller is in D3cold: kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8 kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: PM: Wakeup pending, aborting suspend kernel: last active wakeup source: 0000:00:14.0 Now it does not get a notification (due to PME_B0) when going to D0 on the way into suspend. XHCI goes from D3cold to D0 (in order to be able to read mmio) and then back to D3hot before suspend. kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000) kernel: xhci_hcd 0000:00:14.0: PME# enabled kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65236 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/usb.asl | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 2fe6750..9c9b6b0 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -309,11 +309,6 @@ Device (XHCI) Store (1, AX15) } - // Put device in D3 if it was there originally - If (LEqual (Local0, 3)) { - Store (3, ^D0D3) - } - Return () } @@ -371,9 +366,7 @@ Device (XHCI) } // Put device in D3 - If (LEqual (Local0, 3)) { - Store (3, ^D0D3) - } + Store (3, ^D0D3) Return () }

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coreboot-gerrit December 2013