coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

1 participants
1377 discussions

Patch set updated for coreboot: 5f9c3de lynxpoint: XHCI: Advertise D3 as lowest wake state
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4409 -gerrit commit 5f9c3deabc6df025d528c25cabb67e5a3ccca25e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 16:15:14 2013 -0700 lynxpoint: XHCI: Advertise D3 as lowest wake state The recommended value in docs is D2, but lynxpoint XHCI does not even support D2 state which causes the kernel to think this device cannot be used as a wake source: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Device does not support D2 kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI Additionally this means the kernel will never put the device into D3 state by itself. There is SMI code that will put the device into D3 before suspend so advertising D3 here should be correct. With this change the kernel will put the controller into D3 on suspend and back to D0 on resume, including executing the ACPI methods for _PS0/_PS3 that contain chipset specific workarounds. In addition add a _PSC method to directly return the D state from the device registers. With ALL USB devices removed the XHCI controller goes into D3 state and the kernel can have a hard time determining the state of the device at boot. A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see what ACPI methods are executed: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50) kernel: ACPI: Preparing to enter system sleep state S3 ... kernel: ACPI: Waking up from system sleep state S3 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> meld with s3d Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472 Reviewed-on: https://gerrit.chromium.org/gerrit/63916 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/usb.asl | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 1a0ad34..c22dbb8 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -238,6 +238,11 @@ Device (XHCI) LPCL () } + Method (_PSC, 0, NotSerialized) + { + Return (^D0D3) + } + Method (_PS0, 0, Serialized) { If (LEqual (^DVID, 0xFFFF)) { @@ -375,12 +380,12 @@ Device (XHCI) Method(_S3D,0) // Highest D State in S3 State { - Return (2) + Return (3) } Method(_S4D,0) // Highest D State in S4 State { - Return (2) + Return (3) } Device (HUB7)

1 0

Patch set updated for coreboot: 8f533ae lynxpoint: Fix issues with XHCI init
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4408 -gerrit commit 8f533aea29a59d5d7c91a09e21525aef497c4934 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 15:58:18 2013 -0700 lynxpoint: Fix issues with XHCI init - Put the device into D0 and not D3 so memory bar is available and the subsequent commands actually do something useful - Remove set of 818Ch[7:0]=FFh (gone in ref code) - Fix reg 0x40/0x44 mixup Verify that expected bits are set: localhost ~ # pci_read32 0 0x14 0 0x10 0xe0500004 localhost ~ # mmio_read32 0xe0508144 0x000003ff localhost ~ # mmio_read32 0xe050816c 0x000f0038 Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63801 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/usb_xhci.c | 39 +++++++++++++----------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index dbf0f40..f866c4f 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -235,6 +235,7 @@ void usb_xhci_route_all(void) static void usb_xhci_clock_gating(device_t dev) { u32 reg32; + u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); @@ -258,9 +259,9 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ - reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1 << 9) | (1 << 7) | (1 << 3); - pci_write_config32(dev, 0x44, reg32); + reg16 = pci_read_config16(dev, 0x44); + reg16 |= (1 << 9) | (1 << 7) | (1 << 3); + pci_write_config16(dev, 0x44, reg16); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { @@ -323,21 +324,20 @@ static void usb_xhci_enable_ports_usb3(device_t dev) static void usb_xhci_init(device_t dev) { - struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); u32 reg32; + u16 reg16; + u32 mem_base = usb_xhci_mem_base(dev); - if (!bar0 || bar0->base == 0 || bar0->base == 0xffffffff) - return; + /* D20:F0:74h[1:0] = 00b (set D0 state) */ + reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Enable clock gating first */ usb_xhci_clock_gating(dev); - /* D20:F0:74h[1:0] = 11b (set D3Hot state) */ - reg32 = pci_read_config16(dev, 0x74); - reg32 |= (1 << 1) | (1 << 0); - pci_write_config16(dev, 0x74, reg32); - - reg32 = read32(bar0->base + 0x8144); + reg32 = read32(mem_base + 0x8144); if (pch_is_lp()) { /* XHCIBAR + 8144h[8,7,6] = 111b */ reg32 |= (1 << 8) | (1 << 7) | (1 << 6); @@ -346,25 +346,20 @@ static void usb_xhci_init(device_t dev) reg32 &= ~((1 << 7) | (1 << 6)); reg32 |= (1 << 8); } - write32(bar0->base + 0x8144, reg32); + write32(mem_base + 0x8144, reg32); if (pch_is_lp()) { /* XHCIBAR + 816Ch[19:0] = 000f0038h */ - reg32 = read32(bar0->base + 0x816c); + reg32 = read32(mem_base + 0x816c); reg32 &= ~0x000fffff; reg32 |= 0x000f0038; - write32(bar0->base + 0x816c, reg32); + write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); reg32 |= (1 << 17); pci_write_config32(dev, 0xb0, reg32); - - /* XHCIBAR + 818Ch[7:0] = FFh */ - reg32 = read32(bar0->base + 0x818c); - reg32 |= 0xff; - write32(bar0->base + 0x818c, reg32); } reg32 = pci_read_config32(dev, 0x50); @@ -380,9 +375,9 @@ static void usb_xhci_init(device_t dev) pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ - reg32 = pci_read_config32(dev, 0x40); + reg32 = pci_read_config32(dev, 0x44); reg32 |= (1 << 31); - pci_write_config32(dev, 0x40, reg32); + pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40);

1 0

Patch set updated for coreboot: 64aaa1d lynxpoint: Route all USB ports to XHCI in finalize step
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4407 -gerrit commit 64aaa1ddd2e0740d67d485bc5c88a8a22c33ed15 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 16:05:55 2013 -0700 lynxpoint: Route all USB ports to XHCI in finalize step This commit adds a new Kconfig option for the LynxPoint southbridge that will have coreboot route all of the USB ports to the XHCI controller in the finalize step (i.e. after the bootloader) and disable the EHCI controller(s). Additionally when doing this the XHCI USB3 ports need to be put into an expected state on resume in order to make the kernel state machine happy. Part of this could also be done in depthcharge but there are also some resume-time steps required so it makes sense to keep it all together in coreboot. This can theoretically save ~100mW at runtime. Verify that the EHCI controller is not found in Linux and that booting from USB still works. Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63802 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/smm.h | 1 + src/southbridge/intel/lynxpoint/Kconfig | 7 +++ src/southbridge/intel/lynxpoint/pch.h | 1 + src/southbridge/intel/lynxpoint/smihandler.c | 7 +++ src/southbridge/intel/lynxpoint/usb_xhci.c | 90 ++++++++++++++++++++++++++++ 5 files changed, 106 insertions(+) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 607c0f0..feb50ec 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -372,6 +372,7 @@ typedef struct { #define APM_CNT_ACPI_ENABLE 0xe1 #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_GNVS_UPDATE 0xea +#define APM_CNT_FINALIZE 0xcb #define APM_STS 0xb3 /* SMI handler function prototypes */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 28ebdb6..5ff00db 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -76,4 +76,11 @@ config ME_MBP_CLEAR_LATE finalize step. This can speed up boot time if the ME takes a long time to indicate this status. +config FINALIZE_USB_ROUTE_XHCI + bool "Route all ports to XHCI controller in finalize step" + default y + help + If you set this option to y, the USB ports will be routed + to the XHCI controller during the finalize SMM callback. + endif diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c16c009..6e1b10c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -92,6 +92,7 @@ void intel_pch_finalize_smm(void); void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); void usb_ehci_disable(device_t dev); void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_route_all(void); #endif diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e920cfe..d1e9bbc 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -135,8 +135,10 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ-2); /* USB sleep preparations */ +#if !CONFIG_FINALIZE_USB_ROUTE_XHCI usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); +#endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); #if CONFIG_ELOG_GSMI @@ -314,6 +316,11 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; + case APM_CNT_FINALIZE: +#if CONFIG_FINALIZE_USB_ROUTE_XHCI + usb_xhci_route_all(); +#endif + break; #if CONFIG_ELOG_GSMI case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 5adf88c..dbf0f40 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -189,6 +189,47 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); } +/* Route all ports to XHCI controller */ +void usb_xhci_route_all(void) +{ + u32 port_mask, route; + u16 reg16; + + /* Skip if EHCI is already disabled */ + if (RCBA32(FD) & PCH_DISABLE_EHCI1) + return; + + /* Set D0 state */ + reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); + + /* Set USB3 superspeed enable */ + port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); + route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR); + route &= ~XHCI_USB3PR_SSEN; + route |= XHCI_USB3PR_SSEN & port_mask; + pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route); + + /* Route USB2 ports to XHCI controller */ + port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM); + route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR); + route &= ~XHCI_USB2PR_HCSEL; + route |= XHCI_USB2PR_HCSEL & port_mask; + pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route); + + /* Disable EHCI controller */ + usb_ehci_disable(PCH_EHCI1_DEV); + + /* LynxPoint-H has a second EHCI controller */ + if (!pch_is_lp()) + usb_ehci_disable(PCH_EHCI2_DEV); + + /* Reset and clear port change status */ + usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); +} + #else /* !__SMM__ */ static void usb_xhci_clock_gating(device_t dev) @@ -237,6 +278,49 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config32(dev, 0xa4, reg32); } +/* Re-enable ports that are disabled */ +static void usb_xhci_enable_ports_usb3(device_t dev) +{ +#if CONFIG_FINALIZE_USB_ROUTE_XHCI + int port; + u32 portsc, status, disabled; + u32 mem_base = usb_xhci_mem_base(dev); + int port_count = usb_xhci_port_count_usb3(dev); + + if (!mem_base || !port_count) + return; + + /* Get port disable override map */ + disabled = pci_read_config32(dev, XHCI_USB3PDO); + + for (port = 0; port < port_count; port++) { + /* Skip overridden ports */ + if (disabled & (1 << port)) + continue; + portsc = mem_base + XHCI_USB3_PORTSC(port); + status = read32(portsc) & XHCI_USB3_PORTSC_PLS; + + switch (status) { + case XHCI_PLSR_RXDETECT: + /* Clear change status */ + printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port); + usb_xhci_reset_status_usb3(mem_base, port); + break; + case XHCI_PLSR_DISABLED: + default: + /* Transition to enabled */ + printk(BIOS_DEBUG, "usb_xhci enable port %d\n", port); + usb_xhci_reset_port_usb3(mem_base, port); + status = read32(portsc); + status &= ~XHCI_USB3_PORTSC_PLS; + status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS; + write32(portsc, status); + break; + } + } +#endif +} + static void usb_xhci_init(device_t dev) { struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -305,6 +389,12 @@ static void usb_xhci_init(device_t dev) reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); + +#if CONFIG_HAVE_ACPI_RESUME + /* Enable ports that are disabled before returning to OS */ + if (acpi_slp_type == 3) + usb_xhci_enable_ports_usb3(dev); +#endif } static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,

1 0

Patch set updated for coreboot: 6131c50 lynxpoint: Move USB SMI sleep code to separate USB files
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4406 -gerrit commit 6131c50fa43da238bc0ed4459205c841f7680e34 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 30 15:53:45 2013 -0700 lynxpoint: Move USB SMI sleep code to separate USB files Move this to the existing USB source files so they can share some helper functions and keep the main smihandler code cleaner. The XHCI sleep prepare code now implements the actual sleep preparation steps from the ref code instead of the docs. Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63800 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/pch.h | 51 +++++++- src/southbridge/intel/lynxpoint/smihandler.c | 97 +--------------- src/southbridge/intel/lynxpoint/usb_ehci.c | 113 ++++++++++++++++++ src/southbridge/intel/lynxpoint/usb_xhci.c | 168 +++++++++++++++++++++++++++ 5 files changed, 331 insertions(+), 100 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 1689132..7be2d03 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -49,7 +49,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-y += reset.c early_spi.c rcba.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 32c7d9b..c16c009 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -89,6 +89,9 @@ #if defined (__SMM__) && !defined(__ASSEMBLER__) void intel_pch_finalize_smm(void); +void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_ehci_disable(device_t dev); +void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); #endif @@ -356,11 +359,49 @@ int early_pch_init(const void *gpio_map, #define SATA_DTLE_DATA_SHIFT 24 #define SATA_DTLE_EDGE_SHIFT 16 -/* USB Registers */ -#define EHCI_PWR_CNTL_STS 0x54 -#define EHCI_PWR_STS_MASK 0x3 -#define EHCI_PWR_STS_SET_D0 0x0 -#define EHCI_PWR_STS_SET_D3 0x3 +/* EHCI PCI Registers */ +#define EHCI_PWR_CTL_STS 0x54 +#define PWR_CTL_SET_MASK 0x3 +#define PWR_CTL_SET_D0 0x0 +#define PWR_CTL_SET_D3 0x3 +#define PWR_CTL_ENABLE_PME (1 << 8) + +/* EHCI Memory Registers */ +#define EHCI_USB_CMD 0x20 +#define EHCI_USB_CMD_RUN (1 << 0) +#define EHCI_USB_CMD_PSE (1 << 4) +#define EHCI_USB_CMD_ASE (1 << 5) +#define EHCI_PORTSC(port) (0x64 + (port * 4)) +#define EHCI_PORTSC_ENABLED (1 << 2) +#define EHCI_PORTSC_SUSPEND (1 << 7) + +/* XHCI PCI Registers */ +#define XHCI_PWR_CTL_STS 0x74 +#define XHCI_USB2PR 0xd0 +#define XHCI_USB2PRM 0xd4 +#define XHCI_USB2PR_HCSEL 0x7fff +#define XHCI_USB3PR 0xd8 +#define XHCI_USB3PR_SSEN 0x3f +#define XHCI_USB3PRM 0xdc +#define XHCI_USB3FUS 0xe0 +#define XHCI_USB3FUS_SS_MASK 3 +#define XHCI_USB3FUS_SS_SHIFT 3 +#define XHCI_USB3PDO 0xe8 + +/* XHCI Memory Registers */ +#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10)) +#define XHCI_USB3_PORTSC_CHST (0x7f << 17) +#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ +#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ +#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ +#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ +#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ +#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ +#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ +#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ +#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ /* Serial IO IOBP Registers */ #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index add53ed..e920cfe 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -106,97 +106,6 @@ static void busmaster_disable_on_bus(int bus) } } -/* Handler for EHCI controller on entry to S3/S4/S5 */ -static void ehci_sleep_prepare(device_t dev, u8 slp_typ) -{ - u32 reg32; - u32 bar0_base; - u16 pwr_state; - u16 pci_cmd; - - /* Check if the controller is disabled or not present */ - bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (bar0_base == 0 || bar0_base == 0xffffffff) - return; - pci_cmd = pci_read_config32(dev, PCI_COMMAND); - - switch (slp_typ) { - case SLP_TYP_S4: - case SLP_TYP_S5: - /* Check if controller is in D3 power state */ - pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); - if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { - /* Put in D0 */ - pwr_state &= ~EHCI_PWR_STS_MASK; - pwr_state |= EHCI_PWR_STS_SET_D0; - pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); - - /* Make sure memory bar is set */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); - - /* Make sure memory space is enabled */ - pci_write_config16(dev, PCI_COMMAND, pci_cmd | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - } - - /* - * If Run/Stop (bit0) is clear in USB2.0_CMD: - * - Clear Async Schedule Enable (bit5) and - * - Clear Periodic Schedule Enable (bit4) and - * - Set Run/Stop (bit0) - */ - reg32 = read32(bar0_base + 0x20); - if (reg32 & (1 << 0)) { - reg32 &= ~((1 << 5) | (1 << 4)); - reg32 |= (1 << 0); - write32(bar0_base + 0x20, reg32); - } - - /* Check for Port Enabled in PORTSC */ - reg32 = read32(bar0_base + 0x64); - if (reg32 & (1 << 2)) { - /* Set suspend bit in PORTSC if not already set */ - if (!(reg32 & (1 << 7))) { - reg32 |= (1 << 7); - write32(bar0_base + 0x64, reg32); - } - - /* Delay 25ms !! */ - udelay(25 * 1000); - - /* Clear Run/Stop bit */ - reg32 = read32(bar0_base + 0x20); - reg32 &= (1 << 0); - write32(bar0_base + 0x20, reg32); - } - - pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); - if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { - /* Restore pci command reg */ - pci_write_config16(dev, PCI_COMMAND, pci_cmd); - - /* Enable D3 */ - pwr_state |= EHCI_PWR_STS_SET_D3; - pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); - } - } -} - -/* Handler for XHCI controller on entry to S3/S4/S5 */ -static void xhci_sleep_prepare(device_t dev, u8 slp_typ) -{ - u16 reg16; - - switch (slp_typ) { - case SLP_TYP_S3: - case SLP_TYP_S4: - case SLP_TYP_S5: - /* Set D3Hot state and PME enable bit */ - reg16 = pci_read_config16(dev, 0x74); - reg16 |= (1 << 8) | (1 << 1) | (1 << 0); - pci_write_config16(dev, 0x74, reg16); - } -} static void southbridge_smi_sleep(void) { @@ -226,9 +135,9 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ-2); /* USB sleep preparations */ - ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); - ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); - xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); + usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); + usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); + usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index f06151b..7a3698c 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -19,6 +19,7 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -26,6 +27,116 @@ #include <usbdebug.h> #include <arch/io.h> +#ifdef __SMM__ + +void usb_ehci_disable(device_t dev) +{ + u16 reg16; + u32 reg32; + + /* Set 0xDC[0]=1 */ + pci_or_config32(dev, 0xdc, (1 << 0)); + + /* Set D3Hot state and disable PME */ + reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS); + reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK); + reg16 |= PWR_CTL_SET_D3; + pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16); + + /* Clear memory and bus master */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable device */ + switch (dev) { + case PCH_EHCI1_DEV: + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCH_EHCI2_DEV: + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + } +} + +/* Handler for EHCI controller on entry to S3/S4/S5 */ +void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u32 reg32; + u32 bar0_base; + u16 pwr_state; + u16 pci_cmd; + + /* Check if the controller is disabled or not present */ + bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (bar0_base == 0 || bar0_base == 0xffffffff) + return; + pci_cmd = pci_read_config32(dev, PCI_COMMAND); + + switch (slp_typ) { + case SLP_TYP_S4: + case SLP_TYP_S5: + /* Check if controller is in D3 power state */ + pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS); + if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { + /* Put in D0 */ + u32 new_state = pwr_state & ~PWR_CTL_SET_MASK; + new_state |= PWR_CTL_SET_D0; + pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state); + + /* Make sure memory bar is set */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); + + /* Make sure memory space is enabled */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } + + /* + * If Run/Stop (bit0) is clear in USB2.0_CMD: + * - Clear Async Schedule Enable (bit5) and + * - Clear Periodic Schedule Enable (bit4) and + * - Set Run/Stop (bit0) + */ + reg32 = read32(bar0_base + EHCI_USB_CMD); + if (reg32 & EHCI_USB_CMD_RUN) { + reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE); + reg32 |= EHCI_USB_CMD_RUN; + write32(bar0_base + EHCI_USB_CMD, reg32); + } + + /* Check for Port Enabled in PORTSC(0) (RMH) */ + reg32 = read32(bar0_base + EHCI_PORTSC(0)); + if (reg32 & EHCI_PORTSC_ENABLED) { + /* Set suspend bit in PORTSC if not already set */ + if (!(reg32 & EHCI_PORTSC_SUSPEND)) { + reg32 |= EHCI_PORTSC_SUSPEND; + write32(bar0_base + EHCI_PORTSC(0), reg32); + } + + /* Delay 25ms !! */ + udelay(25 * 1000); + + /* Clear Run/Stop bit */ + reg32 = read32(bar0_base + EHCI_USB_CMD); + reg32 &= EHCI_USB_CMD_RUN; + write32(bar0_base + EHCI_USB_CMD, reg32); + } + + /* Restore state to D3 if that is what it was at the start */ + if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { + /* Restore pci command reg */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd); + + /* Enable D3 */ + pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state); + } + } +} + +#else /* !__SMM__ */ + static void usb_ehci_clock_gating(struct device *dev) { u32 reg32; @@ -98,3 +209,5 @@ static const struct pci_driver pch_usb_ehci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 33f33f4..5adf88c 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -18,12 +18,179 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <arch/io.h> #include "pch.h" +static u32 usb_xhci_mem_base(device_t dev) +{ + u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + + /* Check if the controller is disabled or not present */ + if (mem_base == 0 || mem_base == 0xffffffff) + return 0; + + return mem_base & ~0xf; +} + +static int usb_xhci_port_count_usb3(device_t dev) +{ + if (pch_is_lp()) { + /* LynxPoint-LP has 4 SS ports */ + return 4; + } else { + /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ + u32 mem_base = usb_xhci_mem_base(dev); + u32 fus = read32(mem_base + XHCI_USB3FUS); + fus >>= XHCI_USB3FUS_SS_SHIFT; + fus &= XHCI_USB3FUS_SS_MASK; + switch (fus) { + case 3: return 0; + case 2: return 2; + case 1: return 4; + case 0: default: return 6; + } + } + return 0; +} + +static void usb_xhci_reset_status_usb3(u32 mem_base, int port) +{ + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_CHST); +} + +static void usb_xhci_reset_port_usb3(u32 mem_base, int port) +{ + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); +} + +#ifdef __SMM__ + +#define XHCI_RESET_DELAY_US 1000 /* 1ms */ +#define XHCI_RESET_TIMEOUT 100 /* 100ms */ + +/* + * 1) Wait until port is done polling + * 2) If port is disconnected + * a) Issue warm port reset + * b) Poll for warm reset complete + * c) Write 1 to port change status bits + */ +static void usb_xhci_reset_usb3(device_t dev, int all) +{ + u32 status, port_disabled; + int timeout, port; + int port_count = usb_xhci_port_count_usb3(dev); + u32 mem_base = usb_xhci_mem_base(dev); + + if (!mem_base || !port_count) + return; + + /* Get mask of disabled ports */ + port_disabled = pci_read_config32(dev, XHCI_USB3PDO); + + /* Wait until all enabled ports are done polling */ + for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { + int complete = 1; + for (port = 0; port < port_count; port++) { + /* Skip disabled ports */ + if (port_disabled & (1 << port)) + continue; + /* Read port link status field */ + status = read32(mem_base + XHCI_USB3_PORTSC(port)); + status &= XHCI_USB3_PORTSC_PLS; + if (status == XHCI_PLSR_POLLING) + complete = 0; + } + /* Exit if all ports not polling */ + if (complete) + break; + udelay(XHCI_RESET_DELAY_US); + } + + /* Reset all requested ports */ + for (port = 0; port < port_count; port++) { + u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + /* Skip disabled ports */ + if (port_disabled & (1 << port)) + continue; + status = read32(portsc) & XHCI_USB3_PORTSC_PLS; + /* Reset all or only disconnected ports */ + if (all || status == XHCI_PLSR_RXDETECT) + usb_xhci_reset_port_usb3(mem_base, port); + else + port_disabled |= 1 << port; /* No reset */ + } + + /* Wait for warm reset complete on all reset ports */ + for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { + int complete = 1; + for (port = 0; port < port_count; port++) { + /* Only check ports that were reset */ + if (port_disabled & (1 << port)) + continue; + /* Check if warm reset is complete */ + status = read32(mem_base + XHCI_USB3_PORTSC(port)); + if (!(status & XHCI_USB3_PORTSC_WRC)) + complete = 0; + } + /* Check for warm reset complete in any port */ + if (complete) + break; + udelay(XHCI_RESET_DELAY_US); + } + + /* Clear port change status bits */ + for (port = 0; port < port_count; port++) + usb_xhci_reset_status_usb3(mem_base, port); +} + +/* Handler for XHCI controller on entry to S3/S4/S5 */ +void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u16 reg16; + u32 reg32; + u32 mem_base = usb_xhci_mem_base(dev); + + if (!mem_base || slp_typ < 3) + return; + + if (pch_is_lp()) { + /* Set D0 state */ + reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); + reg16 &= ~PWR_CTL_SET_MASK; + reg16 |= PWR_CTL_SET_D0; + pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + + /* Clear PCI 0xB0[14:13] */ + reg32 = pci_read_config32(dev, 0xb0); + reg32 &= ~((1 << 14) | (1 << 13)); + pci_write_config32(dev, 0xb0, reg32); + + /* Clear MMIO 0x816c[14,2] */ + reg32 = read32(mem_base + 0x816c); + reg32 &= ~((1 << 14) | (1 << 2)); + write32(mem_base + 0x816c, reg32); + + /* Set MMIO 0x80e0[15] */ + reg32 = read32(mem_base + 0x80e0); + reg32 |= (1 << 15); + write32(mem_base + 0x80e0, reg32); + } + + /* Set D3Hot state and enable PME */ + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); + pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); +} + +#else /* !__SMM__ */ + static void usb_xhci_clock_gating(device_t dev) { u32 reg32; @@ -173,3 +340,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; +#endif /* !__SMM__ */

1 0

Patch merged into coreboot/master: c0ab219 pit: disable LCD FETs before doing any graphics init
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit c0ab219040be9329a5b233da7513e54be5ec3c60 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 1 19:09:21 2013 -0700 pit: disable LCD FETs before doing any graphics init This ensures that the LCD FETs are off before we do graphics init. FIXME: The location of the code is sub-optimal and should probably be done in romstage, but there are __PRE_RAM__ considerations to take into account. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df Reviewed-on: https://gerrit.chromium.org/gerrit/64305 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> See http://review.coreboot.org/4470 for details. -gerrit

1 0

Patch merged into coreboot/master: b1b9e4e exynos5420: Assign corect parent PLLs
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit b1b9e4e583a451b97fbd379e2b1f8ecc16e12119 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 12 14:52:45 2013 -0700 exynos5420: Assign corect parent PLLs Assign correct parent PLL's for the following clocks: ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz) PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz) MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz) ACLK_266 (DPLL->MPLL) (300 -> 266MHz) ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz) ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz) ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz) MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz) MUX_MPHY_REFCLK (MPLL->OSC) MUX_UNIPRO (MPLL->OSC) MUX_MIPI1 (EPLL->OSC) MUX_DP1_EXT_VID (EPLL->OSC) MUX_FIMD1_OPT (EPLL->OSC) MUX_IPLL(IPLL->OSC) This also corrects the clock dividers for few of the clocks, as the clock parent changes affect the final frequency of the clocks. This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/ Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8 Reviewed-on: https://gerrit.chromium.org/gerrit/65620 Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> See http://review.coreboot.org/4469 for details. -gerrit

1 0

Patch merged into coreboot/master: 50214f8 exynos5420: don't assume MPLL for i2c parent clock
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 50214f893dd0dd58911bcf3760265c4a58c92d3d Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 12 13:24:24 2013 -0700 exynos5420: don't assume MPLL for i2c parent clock This reads the clock select field for MUX_ACLK_66_SEL in the CLK_SRC_TOP1 register in order to obtain the source clock rate for I2C peripherals. Before we were always assuming that the source was the MPLL. Unfortunately not all fields in the CLK_SRC_TOPn registers are enumerated the same with regard to clock select. So this is just a one-off for now. This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f Reviewed-on: https://gerrit.chromium.org/gerrit/65611 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/4468 for details. -gerrit

1 0

Patch merged into coreboot/master: c31eb36 exynos5420: Set SPLL to 400MHz
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit c31eb3619d09671960d6fa2614c53fc5dfa2e4cf Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 9 18:59:02 2013 -0700 exynos5420: Set SPLL to 400MHz Increase SPLL to 400MHz from 300MHz as we set SPLL as the switching parent for ARM and KFC. This value is as per recommendation of the hardware team. This is ported from https://gerrit.chromium.org/gerrit/62618 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223 Reviewed-on: https://gerrit.chromium.org/gerrit/65432 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4464 for details. -gerrit

1 0

Patch merged into coreboot/master: 21c908b exynos5420: re-factor clock_get_periph_rate()
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 21c908bf6280b4c52dc983f0deb25b3439f75b27 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 20:45:53 2013 -0700 exynos5420: re-factor clock_get_periph_rate() This re-factors clock_get_periph_rate() to be a simpler and also make a few corrections along the way. To summarize: - clk_bit_info is no longer used. It had numerous errors and was really painful anyway since it was just a bunch of opaque magic numbers that made bugs non-obvious. - Clock source bitfields for peripherals handled in the switch statement are 3 bits, not 4. Some divider values are 3 bits, some are 4. The earlier code always assumed 4 bits for both which included reserved bits in many cases. - UART source clock and divider shift values were wrong. - PWM clock divider was being read from the wrong register. - SPI3 divider value was being read from the wrong register. - There was a really confusing calculation for SDMMC0 and SDMMC2 clock rates, but it was never actually used since the switch statement never handled PERIPH_ID_SDMMC{0,2} and would thus return if they were ever passed into this function. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b Reviewed-on: https://gerrit.chromium.org/gerrit/65284 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4463 for details. -gerrit

1 0

Patch merged into coreboot/master: 568a2b0 exynos5420: add a peripheral clock select --> PLL decoder
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 568a2b0f9800e31e28465191801b9f36194b1e3a Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 19:03:03 2013 -0700 exynos5420: add a peripheral clock select --> PLL decoder This adds a helper function to translate between peripheral clock select fields in clock source registers and PLLs. Some of this was already done to handle a few special cases, this generalizes the earlier work so that follow-up patches can do further clean-up. Unfortunately, the PLLs represented by clock select fields in various modules are not uniformly ordered. So for now we focus on peripheral clock sources only. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff Reviewed-on: https://gerrit.chromium.org/gerrit/65283 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4462 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2013