coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: c2e15ba qemu-armv7: Drop additional console_init()
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4257 -gerrit commit c2e15bae2d1bb88896c08af00e350b5b9d429b51 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 12 17:18:03 2013 -0700 qemu-armv7: Drop additional console_init() It's done in bootblock_simple.c just after returning from the mainboard specific bootblock function. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I96cab5e406132a9f7dc30d48ff99f524773a1a14 Reviewed-on: https://gerrit.chromium.org/gerrit/58473 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/emulation/qemu-armv7/Kconfig | 4 ---- src/mainboard/emulation/qemu-armv7/bootblock.c | 23 ----------------------- 2 files changed, 27 deletions(-) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 9bee946..e4327d6 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -45,10 +45,6 @@ config MAINBOARD_VENDOR string default "ARM Ltd." -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/emulation/qemu-armv7/bootblock.c" - config DRAM_SIZE_MB int default 1024 diff --git a/src/mainboard/emulation/qemu-armv7/bootblock.c b/src/mainboard/emulation/qemu-armv7/bootblock.c deleted file mode 100644 index 5654667..0000000 --- a/src/mainboard/emulation/qemu-armv7/bootblock.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> - -void bootblock_mainboard_init(void); -void bootblock_mainboard_init(void) -{ - console_init(); - printk(BIOS_INFO, "\n\n\n%s: ARMv7 Emulation Started.\n", __func__); -}

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Patch set updated for coreboot: ea14d6b Drop obsolete CONSOLE_LOGBUF
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4256 -gerrit commit ea14d6b6d408b1f2207317e27f36f414fb575a68 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 13:47:46 2013 -0700 Drop obsolete CONSOLE_LOGBUF This was used by Ron 13ys ago and was never used again ever since. Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59320 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- payloads/libpayload/include/coreboot_tables.h | 2 +- src/console/Kconfig | 4 ---- src/console/Makefile.inc | 1 - src/console/logbuf_console.c | 21 --------------------- src/include/boot/coreboot_tables.h | 2 +- src/lib/coreboot_table.c | 6 ++---- 6 files changed, 4 insertions(+), 32 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 375d33b..26838e8 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -133,7 +133,7 @@ struct cb_console { #define CB_TAG_CONSOLE_SERIAL8250 0 #define CB_TAG_CONSOLE_VGA 1 // OBSOLETE #define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE -#define CB_TAG_CONSOLE_LOGBUF 3 +#define CB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE #define CB_TAG_CONSOLE_SROM 4 // OBSOLETE #define CB_TAG_CONSOLE_EHCI 5 diff --git a/src/console/Kconfig b/src/console/Kconfig index c23f862..12b942d 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -377,10 +377,6 @@ config DEFAULT_CONSOLE_LOGLEVEL help Map the log level config names to an integer. -config CONSOLE_LOGBUF - bool - default n - config NO_POST bool "Don't show any POST codes" default n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 9edec3c..62be1d2 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c -ramstage-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c diff --git a/src/console/logbuf_console.c b/src/console/logbuf_console.c deleted file mode 100644 index a76791d..0000000 --- a/src/console/logbuf_console.c +++ /dev/null @@ -1,21 +0,0 @@ -#include <console/console.h> - -#define LOGBUF_SIZE 1024 - -// KEEP THIS GLOBAL. -// I need the address so I can watch it with the ARIUM hardware. RGM. -char logbuf[LOGBUF_SIZE]; -int logbuf_offset = 0; - -static void logbuf_tx_byte(unsigned char byte) -{ - logbuf[logbuf_offset] = byte; - logbuf_offset = (logbuf_offset +1) % LOGBUF_SIZE; -} - -static const struct console_driver __console = { - .init = 0, - .tx_byte = logbuf_tx_byte, - .rx_byte = 0, - .tst_byte = 0, -};} diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 87819ce..aa8409a 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -163,7 +163,7 @@ struct lb_console { #define LB_TAG_CONSOLE_SERIAL8250 0 #define LB_TAG_CONSOLE_VGA 1 // OBSOLETE #define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE -#define LB_TAG_CONSOLE_LOGBUF 3 +#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE #define LB_TAG_CONSOLE_SROM 4 // OBSOLETE #define LB_TAG_CONSOLE_EHCI 5 #define LB_TAG_CONSOLE_SERIAL8250MEM 6 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index a0a806d..772729a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -137,7 +137,8 @@ static struct lb_serial *lb_serial(struct lb_header *header) #endif } -#if CONFIG_CONSOLE_SERIAL || CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ + CONFIG_CONSOLE_SERIAL_UART || CONFIG_USBDEBUG static void add_console(struct lb_header *header, u16 consoletype) { struct lb_console *console; @@ -157,9 +158,6 @@ static void lb_console(struct lb_header *header) #if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); #endif -#if CONFIG_CONSOLE_LOGBUF - add_console(header, LB_TAG_CONSOLE_LOGBUF); -#endif #if CONFIG_USBDEBUG add_console(header, LB_TAG_CONSOLE_EHCI); #endif

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Patch set updated for coreboot: b8eb94f libpayload: ARM: Don't leave alignment checking on after the exception test
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4255 -gerrit commit b8eb94f8da6fa858f7bd9bdde56b4cf3f2eb603a Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 20:48:06 2013 -0700 libpayload: ARM: Don't leave alignment checking on after the exception test Currently, the exception handling code on ARM in libpayload turns on alignment checks as an easy way to generate an exception for testing purposes. It was leaving it on which disabled unaligned accesses for other, unlreated code running later. This change adjusts the code so the original value of the alignment bit is restored after the test exception. Built and booted into depthcharge on pit with an unaligned accesses added after the call to exception_init in the depthcharge's main. Before this change, the access caused an exception. After this change, the access completed successfully. Change-Id: If92cab3cc8eabca7c5b0560ce88a8796a27fe3b2 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59372 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/exception.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/armv7/exception.c b/payloads/libpayload/arch/armv7/exception.c index 5e4e23d..9efc312 100644 --- a/payloads/libpayload/arch/armv7/exception.c +++ b/payloads/libpayload/arch/armv7/exception.c @@ -143,9 +143,8 @@ void exception_init(void) sctlr &= ~sctlr_te; /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ sctlr &= ~sctlr_v; - /* Enforce alignment. */ - sctlr |= sctlr_a; - set_sctlr(sctlr); + /* Enforce alignment temporarily. */ + set_sctlr(sctlr | sctlr_a); extern uint32_t exception_table[]; set_vbar((uintptr_t)exception_table); @@ -153,4 +152,7 @@ void exception_init(void) test_abort = 1; exception_test(); test_abort = 0; + + /* Restore alignment settings. */ + set_sctlr(sctlr); }

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Patch set updated for coreboot: 81e793b libpayload: Make the region to scan for the cb tables configurable.
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4254 -gerrit commit 81e793b93f45cdc47444f28df2930892ae7e12b4 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 04:54:38 2013 -0700 libpayload: Make the region to scan for the cb tables configurable. The address range to scan for the coreboot tables varies from machine to machine based on the range memory occupies on the SOC being booted and on the amount of memory installed on the machine. To make libpayload work on different ARM systems with different needs, this change makes the region to scan configurable. In the future, we might want to come up with a more automatic mechanism like on x86, although there's less consistency on ARM as far as what ranges are even memory in the first place. Change-Id: Ib50efe25a6152171b0fbd0e324dbc5e89c527d6e Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59242 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/Config.in | 8 ++++++++ payloads/libpayload/arch/armv7/coreboot.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/Config.in b/payloads/libpayload/arch/armv7/Config.in index 6c1bf44..79cd676 100644 --- a/payloads/libpayload/arch/armv7/Config.in +++ b/payloads/libpayload/arch/armv7/Config.in @@ -33,4 +33,12 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config COREBOOT_INFO_RANGE_BASE + hex "Base of the range to search for the coreboot tables" + +config COREBOOT_INFO_RANGE_SIZE + hex "Size of the range to search for the coreboot tables" + default 0x4000000 + + endif diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index b6178f7..bc9b47e 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -284,7 +284,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0xbc000000), 0x4000000, info); + int ret = cb_parse_header(phys_to_virt(CONFIG_COREBOOT_INFO_RANGE_BASE), + CONFIG_COREBOOT_INFO_RANGE_SIZE, info); return (ret == 1) ? 0 : -1; }

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Patch set updated for coreboot: 61ea38e lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4253 -gerrit commit 61ea38ebb618c6330145993775678b02014c1c8c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 19 10:49:29 2013 -0700 lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects LynxPoint-LP has a lot of GPEs and the "default" set has been moved to register 4 starting at bit offset 96. This means that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP but still bit 13 in LPT-H. suspend on falco and wake from usb 4 | 2013-06-19 10:49:17 | ACPI Enter | S3 5 | 2013-06-19 10:49:22 | ACPI Wake | S3 6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0 Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59265 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/audio.asl | 15 ++++++++++----- src/southbridge/intel/lynxpoint/acpi/usb.asl | 22 ++++++++++++++++++++-- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index a455328..2bc1168 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -27,10 +27,15 @@ Device (HDEF) { Name (_ADR, 0x001b0000) - // Power Resources for Wake - Name (_PRW, Package(){ - 13, // Bit 13 of GPE - 4 // Can wake from S4 state. - }) + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } } diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 5c1f6a5..6583cb3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -27,7 +27,16 @@ Device (EHCI) { Name(_ADR, 0x001d0000) - Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } // Leave USB ports on for to allow Wake from USB @@ -61,7 +70,16 @@ Device (XHCI) { Name(_ADR, 0x00140000) - Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } // Leave USB ports on for to allow Wake from USB

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Patch set updated for coreboot: 66536eb libpayload: Add missing break statement in coreboot table parsing
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4252 -gerrit commit 66536eba1453d9fc69ae28940a8daf023971920e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 12:06:50 2013 -0700 libpayload: Add missing break statement in coreboot table parsing Otherwise the code would try to parse GPIOs when encountering a mainboard entry in the coreboot table. This never caused any problems because the mainboard entry is parsed before the GPIO entry. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I1443bda8585a990a39115743d48304ec4b54bccb Reviewed-on: https://gerrit.chromium.org/gerrit/59292 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/arch/armv7/coreboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index 414b7fa..b6178f7 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -250,6 +250,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) #endif case CB_TAG_MAINBOARD: info->mainboard = (struct cb_mainboard *)ptr; + break; #ifdef CONFIG_CHROMEOS case CB_TAG_GPIO: cb_parse_gpios(ptr, info);

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Patch set updated for coreboot: a81d959 lynxpoint: move all pcie device handling to pcie.c
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4251 -gerrit commit a81d959e8c0e2db528a419651d1ffbc21bb27dc4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:28:04 2013 -0500 lynxpoint: move all pcie device handling to pcie.c Some of the pcie logic was located in pch.c as well as pcie.c. Move all pcie logic to the same pcie.c file. This is a straight cut-and-paste (no logic changes) except for a rename from pch_pcie_enable() -> pch_pcie_enable_dev(). Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59277 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 187 +-------------------------------- src/southbridge/intel/lynxpoint/pch.h | 1 + src/southbridge/intel/lynxpoint/pcie.c | 185 ++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+), 186 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index f13efb0..b4605f5 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -289,198 +289,13 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) pch_iobp_write(address, data); } -/* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) -{ - device_t port; - int port_func; - int dev_func = PCI_FUNC(dev->path.pci.devfn); - - printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); - - /* Go through static device tree list of devices - * because enumeration is still in progress */ - for (port = all_devices; port; port = port->next) { - /* Only care about PCIe root ports */ - if (PCI_SLOT(port->path.pci.devfn) != - PCI_SLOT(dev->path.pci.devfn)) - continue; - - /* Check if port is in range and enabled */ - port_func = PCI_FUNC(port->path.pci.devfn); - if (port_func >= dev_func && - port_func < (dev_func + 4) && - port->enabled) - return 1; - } - - /* None of the ports in this set are enabled */ - return 0; -} - -/* RPFN is a write-once register so keep a copy until it is written */ -static u32 new_rpfn; - -/* Swap function numbers assigned to two PCIe Root Ports */ -static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) -{ - u32 old_rpfn = new_rpfn; - - printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); - - new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); - - /* Old function set to new function and disabled */ - new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); - new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); -} - -/* Update devicetree with new Root Port function number assignment */ -static void pch_pcie_devicetree_update(void) -{ - device_t dev; - - /* Update the function numbers in the static devicetree */ - for (dev = all_devices; dev; dev = dev->next) { - u8 new_devfn; - - /* Only care about PCH PCIe root ports */ - if (PCI_SLOT(dev->path.pci.devfn) != - PCH_PCIE_DEV_SLOT) - continue; - - /* Determine the new devfn for this port */ - new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, - PCI_FUNC(dev->path.pci.devfn))); - - if (dev->path.pci.devfn != new_devfn) { - printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), - PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); - - dev->path.pci.devfn = new_devfn; - } - } -} - -/* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) -{ - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - u32 reg32; - - /* - * Save a copy of the Root Port Function Number map when - * starting to walk the list of PCIe Root Ports so it can - * be updated locally and written out when the last port - * has been processed. - */ - if (PCI_FUNC(dev->path.pci.devfn) == 0) { - new_rpfn = RCBA32(RPFN); - - /* - * Enable Root Port coalescing if the first port is disabled - * or the other devices will not be enumerated by the OS. - */ - if (!dev->enabled) - config->pcie_port_coalesce = 1; - - if (config->pcie_port_coalesce) - printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); - } - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* - * PCIE Power Savings for PantherPoint and CougarPoint/B1+ - * - * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 - * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 - * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not - * called unless the device is enabled. - */ - if ((PCI_FUNC(dev->path.pci.devfn) == 0 || - PCI_FUNC(dev->path.pci.devfn) == 4)) { - /* Handle workaround for PPT and CPT/B1+ */ - if (!pch_pcie_check_set_enabled(dev)) { - u8 reg8 = pci_read_config8(dev, 0xe2); - reg8 |= 1; - pci_write_config8(dev, 0xe2, reg8); - } - - /* - * Enable Clock Gating for shared PCIe resources - * before disabling this particular port. - */ - pci_write_config8(dev, 0xe1, 0x3c); - } - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Do not claim downstream transactions for PCIe ports */ - new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); - - /* Disable this device if possible */ - pch_disable_devfn(dev); - } else { - int fn; - - /* - * Check if there is a lower disabled port to swap with this - * port in order to maintain linear order starting at zero. - */ - if (config->pcie_port_coalesce) { - for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { - if (!(new_rpfn & RPFN_HIDE(fn))) - continue; - - /* Swap places with this function */ - pch_pcie_function_swap( - PCI_FUNC(dev->path.pci.devfn), fn); - break; - } - } - - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } - - /* - * When processing the last PCIe root port we can now - * update the Root Port Function Number and Hide register. - */ - if (PCI_FUNC(dev->path.pci.devfn) == 7) { - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); - RCBA32(RPFN) = new_rpfn; - - /* Update static devictree with new function numbers */ - if (config->pcie_port_coalesce) - pch_pcie_devicetree_update(); - } -} - void pch_enable(device_t dev) { u32 reg32; /* PCH PCIe Root Ports get special handling */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) - return pch_pcie_enable(dev); + return pch_pcie_enable_dev(dev); if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7c18705..9acdd1f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -166,6 +166,7 @@ void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void pch_pcie_enable_dev(device_t dev); #if CONFIG_ELOG void pch_log_state(void); #endif diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a3b84e3..28f4b6a 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -25,6 +25,191 @@ #include <device/pci_ids.h> #include "pch.h" +/* Check if any port in set X to X+3 is enabled */ +static int pch_pcie_check_set_enabled(device_t dev) +{ + device_t port; + int port_func; + int dev_func = PCI_FUNC(dev->path.pci.devfn); + + printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); + + /* Go through static device tree list of devices + * because enumeration is still in progress */ + for (port = all_devices; port; port = port->next) { + /* Only care about PCIe root ports */ + if (PCI_SLOT(port->path.pci.devfn) != + PCI_SLOT(dev->path.pci.devfn)) + continue; + + /* Check if port is in range and enabled */ + port_func = PCI_FUNC(port->path.pci.devfn); + if (port_func >= dev_func && + port_func < (dev_func + 4) && + port->enabled) + return 1; + } + + /* None of the ports in this set are enabled */ + return 0; +} + +/* RPFN is a write-once register so keep a copy until it is written */ +static u32 new_rpfn; + +/* Swap function numbers assigned to two PCIe Root Ports */ +static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) +{ + u32 old_rpfn = new_rpfn; + + printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", + old_fn, new_fn); + + new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); + + /* Old function set to new function and disabled */ + new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); + new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); +} + +/* Update devicetree with new Root Port function number assignment */ +static void pch_pcie_devicetree_update(void) +{ + device_t dev; + + /* Update the function numbers in the static devicetree */ + for (dev = all_devices; dev; dev = dev->next) { + u8 new_devfn; + + /* Only care about PCH PCIe root ports */ + if (PCI_SLOT(dev->path.pci.devfn) != + PCH_PCIE_DEV_SLOT) + continue; + + /* Determine the new devfn for this port */ + new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, + RPFN_FNGET(new_rpfn, + PCI_FUNC(dev->path.pci.devfn))); + + if (dev->path.pci.devfn != new_devfn) { + printk(BIOS_DEBUG, + "PCH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), + PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); + + dev->path.pci.devfn = new_devfn; + } + } +} + +/* Special handling for PCIe Root Port devices */ +void pch_pcie_enable_dev(device_t dev) +{ + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + u32 reg32; + + /* + * Save a copy of the Root Port Function Number map when + * starting to walk the list of PCIe Root Ports so it can + * be updated locally and written out when the last port + * has been processed. + */ + if (PCI_FUNC(dev->path.pci.devfn) == 0) { + new_rpfn = RCBA32(RPFN); + + /* + * Enable Root Port coalescing if the first port is disabled + * or the other devices will not be enumerated by the OS. + */ + if (!dev->enabled) + config->pcie_port_coalesce = 1; + + if (config->pcie_port_coalesce) + printk(BIOS_INFO, + "PCH: PCIe Root Port coalescing is enabled\n"); + } + + if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + /* + * PCIE Power Savings for PantherPoint and CougarPoint/B1+ + * + * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 + * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 + * + * This check is done here instead of pcie driver + * because the pcie driver enable() handler is not + * called unless the device is enabled. + */ + if ((PCI_FUNC(dev->path.pci.devfn) == 0 || + PCI_FUNC(dev->path.pci.devfn) == 4)) { + /* Handle workaround for PPT and CPT/B1+ */ + if (!pch_pcie_check_set_enabled(dev)) { + u8 reg8 = pci_read_config8(dev, 0xe2); + reg8 |= 1; + pci_write_config8(dev, 0xe2, reg8); + } + + /* + * Enable Clock Gating for shared PCIe resources + * before disabling this particular port. + */ + pci_write_config8(dev, 0xe1, 0x3c); + } + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Do not claim downstream transactions for PCIe ports */ + new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); + + /* Disable this device if possible */ + pch_disable_devfn(dev); + } else { + int fn; + + /* + * Check if there is a lower disabled port to swap with this + * port in order to maintain linear order starting at zero. + */ + if (config->pcie_port_coalesce) { + for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { + if (!(new_rpfn & RPFN_HIDE(fn))) + continue; + + /* Swap places with this function */ + pch_pcie_function_swap( + PCI_FUNC(dev->path.pci.devfn), fn); + break; + } + } + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } + + /* + * When processing the last PCIe root port we can now + * update the Root Port Function Number and Hide register. + */ + if (PCI_FUNC(dev->path.pci.devfn) == 7) { + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", + RCBA32(RPFN), new_rpfn); + RCBA32(RPFN) = new_rpfn; + + /* Update static devictree with new function numbers */ + if (config->pcie_port_coalesce) + pch_pcie_devicetree_update(); + } +} + static void pch_pcie_pm_early(struct device *dev) { /* RPC has been moved. It is in PCI config space now. */

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Patch set updated for coreboot: 06747f2 lynxpoint: expose pch_disable_devfn()
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4250 -gerrit commit 06747f21a2d8451f8579b70dbf5d04f11a096ca3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:20:37 2013 -0500 lynxpoint: expose pch_disable_devfn() The function to disable devices was formerly named pch_hide_devfn(). This routine was doing more than hiding devices. It was disabling them, i.e. turning them off. Therefore, rename it to pch_disable_devfn(). Also, allow external callers to this function. Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59276 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 10 +++++----- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 05462c5..f13efb0 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -92,7 +92,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -static void pch_hide_devfn(device_t dev) +void pch_disable_devfn(device_t dev) { switch (dev->path.pci.devfn) { case PCI_DEVFN(19, 0): /* Audio DSP */ @@ -432,8 +432,8 @@ static void pch_pcie_enable(device_t dev) /* Do not claim downstream transactions for PCIe ports */ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); - /* Hide this device if possible */ - pch_hide_devfn(dev); + /* Disable this device if possible */ + pch_disable_devfn(dev); } else { int fn; @@ -491,8 +491,8 @@ void pch_enable(device_t dev) PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); - /* Hide this device if possible */ - pch_hide_devfn(dev); + /* Disable this device if possible */ + pch_disable_devfn(dev); } else { /* Enable SERR */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c46153c..7c18705 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -162,6 +162,7 @@ void disable_gpe(u32 mask); #include <arch/acpi.h> #include "chip.h" void pch_enable(device_t dev); +void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);

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Patch set updated for coreboot: 6e2655b lynxpoint: expose iobp functions
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4249 -gerrit commit 6e2655b33c14c11d0cbd4abb694d7564fd248035 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:12:48 2013 -0500 lynxpoint: expose iobp functions The iobp functions are useful to may of the southbridge devices as certain values need to be updated to properly initialize the devices. Therefore expose read, write, and updated iobp functions. Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59275 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 25 +++++++++++++++++++------ src/southbridge/intel/lynxpoint/pch.h | 2 ++ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 58c68cd..05462c5 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -201,7 +201,7 @@ static inline int iobp_poll(void) return 0; } -static u32 pch_iobp_read(u32 address) +u32 pch_iobp_read(u32 address) { u16 status; @@ -239,10 +239,15 @@ static u32 pch_iobp_read(u32 address) return RCBA32(IOBPD); } -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +void pch_iobp_write(u32 address, u32 data) { u16 status; - u32 data = pch_iobp_read(address); + + if (!iobp_poll()) + return; + + /* Set the address */ + RCBA32(IOBPIRI) = address; /* WRITE OPCODE */ status = RCBA16(IOBPS); @@ -250,9 +255,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) status |= IOBPS_WRITE; RCBA16(IOBPS) = status; - /* Update the data */ - data &= andvalue; - data |= orvalue; RCBA32(IOBPD) = data; /* Undocumented magic */ @@ -276,6 +278,17 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); } +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} + /* Check if any port in set X to X+3 is enabled */ static int pch_pcie_check_set_enabled(device_t dev) { diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6ee81d1..c46153c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -162,6 +162,8 @@ void disable_gpe(u32 mask); #include <arch/acpi.h> #include "chip.h" void pch_enable(device_t dev); +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void);

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Patch set updated for coreboot: 2dcb373 Add description to MAINBOARD_VENDOR string so it can be overridden
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4248 -gerrit commit 2dcb373dd6f033323ab87651bb0f24edb3a5e9ef Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 18 13:19:26 2013 -0700 Add description to MAINBOARD_VENDOR string so it can be overridden A quirk of the Kconfig used in coreboot is that config options cannot be overriden by local config changes unless they have a description string. 1) Add CONFIG_MAINBOARD_VENDOR="Custom" to local config 2) Build and flash coreboot 3) cat /sys/class/dmi/id/sys_vendor and look for "Custom" Change-Id: I1b5f2124cd4a22c056c025143ae5bcaafa6b03f0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59088 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 4c36932..9ed615d 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -58,7 +58,7 @@ source "src/mainboard/google/snow/Kconfig" source "src/mainboard/google/stout/Kconfig" config MAINBOARD_VENDOR - string + string "Mainboard Vendor" default "Google" endif # VENDOR_GOOGLE

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coreboot-gerrit November 2013