coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 595f87e slippy/falco/peppy: Fix SPD GPIO initialization.
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4237 -gerrit commit 595f87e0ecef610601b28aaf7ccf9c73fde76aae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jun 13 17:29:36 2013 -0700 slippy/falco/peppy: Fix SPD GPIO initialization. SPD GPIOs were being read prior to initialization in romstage_common. To fix, pass the copy_spd function to romstage_common, to be called at the appropriate time (after PCH init, before DRAM init). Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58608 --- src/cpu/intel/haswell/haswell.h | 1 + src/cpu/intel/haswell/romstage.c | 3 +++ src/mainboard/google/falco/romstage.c | 4 +--- src/mainboard/google/peppy/romstage.c | 4 +--- src/mainboard/google/slippy/romstage.c | 4 +--- src/mainboard/intel/baskingridge/romstage.c | 2 ++ src/mainboard/intel/wtm2/romstage.c | 2 ++ 7 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7dfba86..cd007c1 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -151,6 +151,7 @@ struct romstage_params { const void *gpio_map; const struct rcba_config_instruction *rcba_config; unsigned long bist; + void (*copy_spd)(struct pei_data *); }; void mainboard_romstage_entry(unsigned long bist); void romstage_common(const struct romstage_params *params); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 757cc34..35b51c5 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -246,6 +246,9 @@ void romstage_common(const struct romstage_params *params) report_platform_info(); + if (params->copy_spd != NULL) + params->copy_spd(params->pei_data); + sdram_initialize(params->pei_data); timestamp_add_now(TS_AFTER_INITRAM); diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index ef6a849..74ace9b 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -155,11 +155,9 @@ void mainboard_romstage_entry(unsigned long bist) .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, + .copy_spd = copy_spd, }; - /* Prepare SPD data */ - copy_spd(&pei_data); - /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); } diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 8679adb..d979203 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -183,11 +183,9 @@ void mainboard_romstage_entry(unsigned long bist) .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, + .copy_spd = copy_spd, }; - /* Prepare SPD data */ - copy_spd(&pei_data); - /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 8679adb..d979203 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -183,11 +183,9 @@ void mainboard_romstage_entry(unsigned long bist) .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, + .copy_spd = copy_spd, }; - /* Prepare SPD data */ - copy_spd(&pei_data); - /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 8b18e6d..1dc4960 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -19,6 +19,7 @@ */ #include <stdint.h> +#include <stddef.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" @@ -126,6 +127,7 @@ void mainboard_romstage_entry(unsigned long bist) .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, + .copy_spd = NULL, }; /* Call into the real romstage main with this board's attributes. */ diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index f38389c..0a24e48 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -19,6 +19,7 @@ */ #include <stdint.h> +#include <stddef.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" @@ -123,6 +124,7 @@ void mainboard_romstage_entry(unsigned long bist) .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, + .copy_spd = NULL, }; /* Call into the real romstage main with this board's attributes. */

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Patch set updated for coreboot: 2d6797b amd/car/post_cache_as_ram: Switch stack in assembly rather than in C
by Vladimir Serbinenko 26 Nov '13

26 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4286 -gerrit commit 2d6797b8222938f2c28e60b9d930d78bd458c431 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 17:49:29 2013 +0100 amd/car/post_cache_as_ram: Switch stack in assembly rather than in C Compiler may do loads of optimisations around stack switch and so it's allowed to break stack switch as it sees fit. Do it in assembly instead. Not tested. Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 12 ++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 25 ++++++++++--------------- 2 files changed, 22 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..8f0abce 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -414,10 +414,22 @@ CAR_FAM10_ap_out: pushl %ebx /* Init detected. */ pushl %eax /* BIST */ call cache_as_ram_main + /* We will not go back. */ post_code(0xaf) /* Should never see this POST code. */ + .globl cache_as_ram_switch_stack + +cache_as_ram_switch_stack: + /* Return address. */ + popl %eax + /* Resume memory. */ + popl %eax + subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp + pushl %eax + call cache_as_ram_new_stack + all_mtrr_msrs: /* fixed MTRR MSRs */ .long MTRRfix64K_00000_MSR diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index eca7673..3fe496e 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -75,11 +75,11 @@ static void vErrata343(void) #endif } +void cache_as_ram_switch_stack(void *resume_backup_memory); + static void post_cache_as_ram(void) { -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif + void *resume_backup_memory = NULL; #if 1 { /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ @@ -92,9 +92,6 @@ static void post_cache_as_ram(void) } #endif - unsigned testx = 0x5a5a5a5a; - print_debug_pcar("testx = ", testx); - /* copy data from cache as ram to ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. */ @@ -112,21 +109,19 @@ static void post_cache_as_ram(void) vErrata343(); memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline + cache_as_ram_switch_stack(resume_backup_memory); +} - __asm__ volatile ( - /* set new esp */ /* before CONFIG_RAMBASE */ - "subl %0, %%esp\n\t" - ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) - /* discard all registers (eax is used for %0), so gcc redoes everything - after the stack is moved */ - : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" - ); +void +cache_as_ram_new_stack (void *resume_backup_memory); +void +cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) +{ /* We can put data to stack again */ /* only global variable sysinfo in cache need to be offset */ print_debug("Done\n"); - print_debug_pcar("testx = ", testx); print_debug("Disabling cache as ram now \n");

1 0

Patch set updated for coreboot: 434f804 Replace all occurences of sprintf with snprintf
by Vladimir Serbinenko 26 Nov '13

26 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4279 -gerrit commit 434f8047e85e209ffe801ef75d1d867f17350edb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:41:26 2013 +0100 Replace all occurences of sprintf with snprintf THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 3 +- src/device/device_util.c | 83 ++++++++++++---------- src/device/oprom/x86emu/debug.c | 8 +-- src/mainboard/google/link/i915.c | 2 +- src/mainboard/google/stout/i915.c | 2 +- src/mainboard/intel/wtm2/i915.c | 2 +- src/mainboard/lenovo/x60/i915.c | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 4 +- src/northbridge/amd/amdk8/northbridge.c | 4 +- 16 files changed, 67 insertions(+), 57 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 121cb22..6496d75 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -274,7 +274,8 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(0x83); len = acpigen_write_len_f(); - sprintf(pscope, "\\_PR.CPU%x", (unsigned int) cpuindex); + snprintf(pscope, sizeof (pscope), + "\\_PR.CPU%x", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/device/device_util.c b/src/device/device_util.c index d2c99e1..b35911b 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -176,48 +176,52 @@ const char *dev_path(device_t dev) break; case DEVICE_PATH_PCI: #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary >> 8, - dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); + snprintf(buffer, sizeof (buffer), + "PCI: %04x:%02x:%02x.%01x", + dev->bus->secondary >> 8, + dev->bus->secondary & 0xff, + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #else - sprintf(buffer, "PCI: %02x:%02x.%01x", - dev->bus->secondary, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); + snprintf(buffer, sizeof (buffer), + "PCI: %02x:%02x.%01x", + dev->bus->secondary, + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #endif break; case DEVICE_PATH_PNP: - sprintf(buffer, "PNP: %04x.%01x", - dev->path.pnp.port, dev->path.pnp.device); + snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x", + dev->path.pnp.port, dev->path.pnp.device); break; case DEVICE_PATH_I2C: - sprintf(buffer, "I2C: %02x:%02x", - dev->bus->secondary, - dev->path.i2c.device); + snprintf(buffer, sizeof (buffer), "I2C: %02x:%02x", + dev->bus->secondary, + dev->path.i2c.device); break; case DEVICE_PATH_APIC: - sprintf(buffer, "APIC: %02x", - dev->path.apic.apic_id); + snprintf(buffer, sizeof (buffer), "APIC: %02x", + dev->path.apic.apic_id); break; case DEVICE_PATH_IOAPIC: - sprintf(buffer, "IOAPIC: %02x", - dev->path.ioapic.ioapic_id); + snprintf(buffer, sizeof (buffer), "IOAPIC: %02x", + dev->path.ioapic.ioapic_id); break; case DEVICE_PATH_DOMAIN: - sprintf(buffer, "DOMAIN: %04x", + snprintf(buffer, sizeof (buffer), "DOMAIN: %04x", dev->path.domain.domain); break; case DEVICE_PATH_CPU_CLUSTER: - sprintf(buffer, "CPU_CLUSTER: %01x", + snprintf(buffer, sizeof (buffer), "CPU_CLUSTER: %01x", dev->path.cpu_cluster.cluster); break; case DEVICE_PATH_CPU: - sprintf(buffer, "CPU: %02x", dev->path.cpu.id); + snprintf(buffer, sizeof (buffer), + "CPU: %02x", dev->path.cpu.id); break; case DEVICE_PATH_CPU_BUS: - sprintf(buffer, "CPU_BUS: %02x", dev->path.cpu_bus.id); + snprintf(buffer, sizeof (buffer), + "CPU_BUS: %02x", dev->path.cpu_bus.id); break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", @@ -241,7 +245,8 @@ const char *dev_name(device_t dev) const char *bus_path(struct bus *bus) { static char buffer[BUS_PATH_MAX]; - sprintf(buffer, "%s,%d", dev_path(bus->dev), bus->link_num); + snprintf(buffer, sizeof (buffer), + "%s,%d", dev_path(bus->dev), bus->link_num); return buffer; } @@ -529,15 +534,15 @@ resource_t resource_max(struct resource *resource) const char *resource_type(struct resource *resource) { static char buffer[RESOURCE_TYPE_MAX]; - sprintf(buffer, "%s%s%s%s", - ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""), - ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""), - ((resource->flags == 0) ? "unused" : - (resource->flags & IORESOURCE_IO) ? "io" : - (resource->flags & IORESOURCE_DRQ) ? "drq" : - (resource->flags & IORESOURCE_IRQ) ? "irq" : - (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"), - ((resource->flags & IORESOURCE_PCI64) ? "64" : "")); + snprintf(buffer, sizeof (buffer), "%s%s%s%s", + ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""), + ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""), + ((resource->flags == 0) ? "unused" : + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_DRQ) ? "drq" : + (resource->flags & IORESOURCE_IRQ) ? "irq" : + (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"), + ((resource->flags & IORESOURCE_PCI64) ? "64" : "")); return buffer; } @@ -563,10 +568,12 @@ void report_resource_stored(device_t dev, struct resource *resource, if (resource->flags & IORESOURCE_PCI_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, + snprintf(buf, sizeof (buf), + "bus %04x:%02x ", dev->bus->secondary >> 8, dev->link_list->secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link_list->secondary); + snprintf(buf, sizeof (buf), + "bus %02x ", dev->link_list->secondary); #endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " @@ -775,10 +782,12 @@ void show_one_resource(int debug_level, struct device *dev, /* if (resource->flags & IORESOURCE_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, - dev->link[0].secondary & 0xff); + snprintf(buf, sizeof (buf), "bus %04x:%02x ", + dev->bus->secondary >> 8, + dev->link[0].secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link[0].secondary); + snprintf(buf, sizeof (buf), + "bus %02x ", dev->link[0].secondary); #endif } */ diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index b3f4b6e..e7a111b 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -163,15 +163,15 @@ void x86emu_inc_decoded_inst_len (int x) void x86emu_decode_printf (const char *x) { - sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",x); + strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,x); M.x86.enc_str_pos += strlen(x); } void x86emu_decode_printf2 (const char *x, int y) { char temp[100]; - sprintf(temp,x,y); - sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",temp); + snprintf(temp, sizeof (temp), x,y); + strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,temp); M.x86.enc_str_pos += strlen(temp); } @@ -186,7 +186,7 @@ static void print_encoded_bytes (u16 s, u16 o) int i; char buf1[64]; for (i=0; i< M.x86.enc_pos; i++) { - sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); + snprintf(buf1+2*i, 64 - 2 * i, "%02x", fetch_data_byte_abs(s,o+i)); } printf("%-20s ",buf1); } diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 42b9c0f..079ae02 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -78,7 +78,7 @@ const u32 link_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 89a8594..8085de6 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -88,7 +88,7 @@ setgtt(int start, int end, unsigned long base, int inc) static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c index df88138..b664c35 100644 --- a/src/mainboard/intel/wtm2/i915.c +++ b/src/mainboard/intel/wtm2/i915.c @@ -88,7 +88,7 @@ static int ioread = 0, iowrite = 0; static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index f130c5c..93f60a8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -81,7 +81,7 @@ const u32 x60_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - sprintf(name, "0x%lx", addr); + snprintf(name, sizeof (name), "0x%lx", addr); return name; } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1c7e547..60f3951 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -657,7 +657,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index e6be598..9757d96 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -402,7 +402,7 @@ static void set_resource(device_t dev, struct resource *resource, set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7cc812b..847e6dd 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -402,7 +402,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) rbase >> 8, rend >> 8, 1); // [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a8cc1cc..aa9ec56 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -400,7 +400,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index b55d52b..2b5549d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b8bba50..6feabf4 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -380,7 +380,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index ee842d5..abba0ce 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -313,7 +313,7 @@ static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex) CONTROL = sspr + 0x8d; STATUS = sspr + 0x8f; - sprintf((char*)CPU, "%02x", (char)cpuindex); + snprintf((char*)CPU, 3, "%02x", (char)cpuindex); *CPUIN = (u8) cpuindex; for(i=0;i<sysconf.p_state_num;i++) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6bcab41..26e040f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -541,8 +541,8 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", - nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 8f0a11b..b0acdf7 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -479,8 +479,8 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %x link %x>", - nodeid, link_num); + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); }

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Patch set updated for coreboot: f139a7d Remove sprintf
by Vladimir Serbinenko 26 Nov '13

26 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4280 -gerrit commit f139a7d26f4c12f7e82f9b9218a39d61e6aafc20 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:42:52 2013 +0100 Remove sprintf Remove sprintf as if you can't easily use snprintf then you probably have buffer overflow. Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/console/vsprintf.c | 14 -------------- src/include/string.h | 1 - 2 files changed, 15 deletions(-) diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 3d085e9..99e3dc8 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -57,20 +57,6 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) return i; } -int sprintf(char *buf, const char *fmt, ...) -{ - va_list args; - int i; - - va_start(args, fmt); - /* A trick: we have at most (size_t)-1 adressable space anyway, so - if we output so much we'll crash anyway. */ - i = vsnprintf(buf, -1, fmt, args); - va_end(args); - - return i; -} - int snprintf(char *buf, size_t size, const char *fmt, ...) { va_list args; diff --git a/src/include/string.h b/src/include/string.h index dc125e1..b4d0268 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -16,7 +16,6 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) -int sprintf(char * buf, const char *fmt, ...); int snprintf(char * buf, size_t size, const char *fmt, ...); #endif

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Patch set updated for coreboot: 443b971 vboot: use out_flags to indicate dev mode
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4218 -gerrit commit 443b971cf6cb523a37f2e360ff2bf7727d7eaa92 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 4 08:57:54 2013 -0500 vboot: use out_flags to indicate dev mode In order to make the proper decision on loading the option rom or not the developer mode setting needs to be known. Under early firmware selection it is possible to know the state of developer mode by a flag in out flags. Use this flag when early firmware selection is being employed to determine if developer mode is enabled or not. Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57380 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 6f1fe72..c2cc0e1 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -26,9 +26,28 @@ #include <cbmem.h> #include <console/console.h> +#if CONFIG_VBOOT_VERIFY_FIRMWARE +static int vboot_enable_developer(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) { + printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", + __func__); + return 0; + } + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); +} +#else +static inline int vboot_enable_developer(void) { return 0; } +#endif + int developer_mode_enabled(void) { - return get_developer_mode_switch(); + return get_developer_mode_switch() || vboot_enable_developer(); } int recovery_mode_enabled(void)

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Patch merged into coreboot/master: 5679e5a google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI`
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit 5679e5a4b6ddf32a3a5291913a353037938473ae Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Oct 21 20:23:35 2013 +0200 google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI` Make the declaration and use of it conditional on the ELOG_GSMI Kconfig variable. Change-Id: I2ef291d2f3e7d35545014e03ba8e0045da6050e5 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3987 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3987 for details. -gerrit

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Patch set updated for coreboot: 62ee959 Add DDR refresh config to pei data structure.
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4213 -gerrit commit 62ee9597c5c34e2e3f51e22b6a094d574dd2f3cb Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Wed May 8 11:41:04 2013 -0700 Add DDR refresh config to pei data structure. Allow platform customized DDR config, including forcing refresh rate to 2x. Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2 Reviewed-on: https://gerrit.chromium.org/gerrit/50476 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/northbridge/intel/sandybridge/pei_data.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index d317515..5e0ff0f 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -121,6 +121,14 @@ struct pei_data * 2 2N */ int nmode; + /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + int ddr_refresh_rate_config; } __attribute__((packed)); #endif

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Patch set updated for coreboot: 4948ea8 peppy: Re-enable EC software sync
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4212 -gerrit commit 4948ea8d0afcf3b2da17755eb3389fc6f6315474 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri May 31 18:57:20 2013 -0700 peppy: Re-enable EC software sync The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. (Taken from I63ca00d6c94854f2b395eb736ce20792da5f8de2). Change-Id: I9c7d1d1f1aaf7de33d0cec5f6daf648576ba8900 Reviewed-on: https://gerrit.chromium.org/gerrit/57289 Reviewed-by: Dave Parker <dparker(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/peppy/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index b7745e1..5eb8b95 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_SOFTWARE_SYNC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME

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Patch set updated for coreboot: 0271ff2 peppy: Update GPIO table + USB port map.
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4211 -gerrit commit 0271ff238d560daebcee679921d710b15ffde19d Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue May 28 17:46:49 2013 -0700 peppy: Update GPIO table + USB port map. - Update GPIO table to match board. - Update USB port map. - Remove iSSD power sequencing code. Change-Id: Iaa8e5921ed9db6bcfd18b5a888c7f80b2c93a710 Reviewed-on: https://gerrit.chromium.org/gerrit/56869 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/peppy/gpio.h | 16 ++++++------ src/mainboard/google/peppy/romstage.c | 46 ++++------------------------------- 2 files changed, 13 insertions(+), 49 deletions(-) diff --git a/src/mainboard/google/peppy/gpio.h b/src/mainboard/google/peppy/gpio.h index 6dfb98f..7c023b5 100644 --- a/src/mainboard/google/peppy/gpio.h +++ b/src/mainboard/google/peppy/gpio.h @@ -39,8 +39,8 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ - LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ LP_GPIO_UNUSED, /* 19: UNUSED */ LP_GPIO_UNUSED, /* 20: UNUSED */ @@ -56,7 +56,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_UNUSED, /* 33: UNUSED */ LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ @@ -67,12 +67,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 41: UNUSED */ LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ LP_GPIO_UNUSED, /* 43: UNUSED */ - LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ + LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ LP_GPIO_INPUT, /* 47: RAM_ID2 */ LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ + LP_GPIO_UNUSED, /* 49: UNUSED */ LP_GPIO_UNUSED, /* 50: UNUSED */ LP_GPIO_IRQ_EDGE, /* 51: ALS_INT_L */ LP_GPIO_IRQ_EDGE, /* 52: SIM_DET */ @@ -84,12 +84,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ - LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ LP_GPIO_UNUSED, /* 64: UNUSED */ LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ LP_GPIO_UNUSED, /* 67: UNUSED */ LP_GPIO_UNUSED, /* 68: UNUSED */ LP_GPIO_UNUSED, /* 69: UNUSED */ diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 8679adb..834479d 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -98,39 +98,6 @@ static void copy_spd(struct pei_data *peid) sizeof(peid->spd_data[0])); } -/* - * Power Sequencing for SanDisk i100/i110 SSD - * - * Must be sequenced in this order with specified timing. - * - * 1. VCC_IO : 30us - 100ms - * 2. VCC_FLASH : 70us - 10ms - * 3. VCCQ : 70us - 10ms - * 4. VDDC : 30us - 100ms - * - * There is no feedback to know if the voltage has stabilized - * so this implementation will use the max ramp times. That - * means it adds significantly to the boot time. - */ -static void issd_power_sequence(void) -{ - struct gpio_seq { - int gpio; - int wait_ms; - } issd_gpio_seq[] = { - { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ - { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ - { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ - { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ - }; - int step; - - for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) { - set_gpio(issd_gpio_seq[step].gpio, 1); - udelay(issd_gpio_seq[step].wait_ms * 1000); - } -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { @@ -161,18 +128,18 @@ void mainboard_romstage_entry(unsigned long bist) usb2_ports: { /* Length, Enable, OCn# */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, 0 }, /* P1: Port A */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ + { 0x0040, 1, 2 }, /* P4: USB 2.0 Port */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ }, usb3_ports: { /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN6 */ + { 1, 0 }, /* P1; Port A, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P2; */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, @@ -190,7 +157,4 @@ void mainboard_romstage_entry(unsigned long bist) /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); - - /* Power sequence the iSSD module */ - issd_power_sequence(); }

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Patch set updated for coreboot: 4b34db9 lynxpoint: Do not clear ACPI NVS region on resume
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4210 -gerrit commit 4b34db99e81a8c2ee9826b854fde848d2ba7442b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 07:49:55 2013 -0700 lynxpoint: Do not clear ACPI NVS region on resume There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff50476..cc95454 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -701,7 +701,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs) + if (acpi_slp_type != 3 && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); }

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coreboot-gerrit November 2013