coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cb69646 lynxpoint: Add an inverted input GPIO type
by Stefan Reinauer 26 Nov '13

26 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4209 -gerrit commit cb69646c9e19c41f8a47400c1b38f9168f0c0685 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 07:48:47 2013 -0700 lynxpoint: Add an inverted input GPIO type The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. suspend/resume on slippy with trackpad wake: 8 | 2013-05-29 07:43:14 | ACPI Enter | S3 9 | 2013-05-29 07:43:18 | ACPI Wake | S3 10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12 and with power button wake: 11 | 2013-05-29 07:43:35 | ACPI Enter | S3 12 | 2013-05-29 07:43:40 | EC Event | Power Button 13 | 2013-05-29 07:43:40 | ACPI Wake | S3 14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0 Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56940 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/gpio.h | 4 ++-- src/mainboard/google/slippy/gpio.h | 4 ++-- src/southbridge/intel/lynxpoint/lp_gpio.h | 4 ++++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/falco/gpio.h b/src/mainboard/google/falco/gpio.h index 037ddcb..3af0d59 100644 --- a/src/mainboard/google/falco/gpio.h +++ b/src/mainboard/google/falco/gpio.h @@ -35,7 +35,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 9: RAM_ID1 */ LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_INPUT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ @@ -48,7 +48,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 22: UNUSED */ LP_GPIO_UNUSED, /* 23: UNUSED */ LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_INPUT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ LP_GPIO_UNUSED, /* 26: UNUSED */ LP_GPIO_UNUSED, /* 27: UNUSED */ LP_GPIO_UNUSED, /* 28: UNUSED */ diff --git a/src/mainboard/google/slippy/gpio.h b/src/mainboard/google/slippy/gpio.h index 4b557ce..2d47ea7 100644 --- a/src/mainboard/google/slippy/gpio.h +++ b/src/mainboard/google/slippy/gpio.h @@ -35,7 +35,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 9: RAM_ID1 */ LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_INPUT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ @@ -48,7 +48,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 22: UNUSED */ LP_GPIO_UNUSED, /* 23: UNUSED */ LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_INPUT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ LP_GPIO_UNUSED, /* 26: UNUSED */ LP_GPIO_UNUSED, /* 27: UNUSED */ LP_GPIO_UNUSED, /* 28: UNUSED */ diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index f1b2717..38da9e2 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -123,6 +123,10 @@ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ .owner = GPIO_OWNER_GPIO } +#define LP_GPIO_INPUT_INVERT \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ + .owner = GPIO_OWNER_GPIO } + #define LP_GPIO_IRQ_EDGE \ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ .owner = GPIO_OWNER_GPIO, \

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Patch merged into coreboot/master: 4aab71a slippy/falco: Re-enable EC software sync
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit 4aab71aae4e9a30fa61aab10947869f3430be4ee Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 11:35:43 2013 -0700 slippy/falco: Re-enable EC software sync The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. Google Chrome EC MKBP driver ready, id 'slippy_no_version' Clearing the recovery request. EC hash:7fea29992ef72e3e64d8ffe522aa1dfa68dcb44a2da96a4c19530ea1a0bd22c4 EC-RW hash address, size are 0xffa1cfe8, 32. Hash = 727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde Expected hash:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde EC-RW firmware address, size are 0xffad000c, 57180. VbEcSoftwareSync() - expected len = 57180 Computed hash of expected image:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde VbEcSoftwareSync() updating EC-RW... VbEcSoftwareSync() jumping to EC-RW VbEcSoftwareSync() in RW; done Change-Id: I63ca00d6c94854f2b395eb736ce20792da5f8de2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56821 Reviewed-on: http://review.coreboot.org/4208 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4208 for details. -gerrit

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Patch merged into coreboot/master: cb73a84 Clean up POST codes for Boot State machine
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit cb73a8410cb80c8ff86e3d860ac3c8ae458b19ac Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 10 10:41:04 2013 -0700 Clean up POST codes for Boot State machine Now that there is a clearly defined boot state machine we can add some useful post codes to indicate the current point in the state machine by having it log a post code before the execution of each state. This removes the currently defined POST codes that were used by hardwaremain in favor of a new contiguous range that are defined for each boot state. The reason for this is that the existing codes are mostly used to indicate when something is done, which is confusing for actual debug because POST code debugging relies on knowing what is about to happen (to know what may be at fault) rather than what has just finished. One additonal change is added during device init step as this step often does the bulk of the work, and frequently logs POST codes itself. Therefore in order to keep better track of what device is being initialized POST_BS_DEV_INIT is logged before each device is initialized. interrupted boot with reset button and gathered the eventlog. Mosys has been extended to decode the well-known POST codes: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: Ida1e1129d274d28cbe8e49e4a01483e335a03d96 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58106 Reviewed-on: http://review.coreboot.org/4231 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4231 for details. -gerrit

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Patch merged into coreboot/master: 8adf7a2 Log device path into CMOS during probe stages
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit 8adf7a2c50dcb3a7f09b66c1f3918ab195d8c5ec Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 10 10:34:20 2013 -0700 Log device path into CMOS during probe stages One of the most common hangs during coreboot execution is during ramstage device init steps. Currently there are a set of (somewhat misleading) post codes during this phase which give some indication as to where execution stopped, but it provides no information on what device was actually being initialized at that point. This uses the new CMOS "extra" log banks to store the encoded device path of the device that is about to be touched by coreboot. This way if the system hangs when talking to the device there will be some indication where to investigate next. interrupted boot with reset button and gathered the eventlog after several test runs: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58105 Reviewed-on: http://review.coreboot.org/4230 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4230 for details. -gerrit

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Patch merged into coreboot/master: d5686fe Extend CMOS POST code logging to store extra data
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit d5686fe23b1341ca2c72b2941cf80577e6198f23 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 10 10:21:41 2013 -0700 Extend CMOS POST code logging to store extra data This can be used to indicate sub-state within a POST code range which can assist in debugging BIOS hangs. For example this can be used to indicate which device is about to be initialized so if the system hangs while talking to that device it can be identified. Change-Id: I2f8155155f09fe9e242ebb7204f0b5cba3a1fa1e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58104 Reviewed-on: http://review.coreboot.org/4229 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4229 for details. -gerrit

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Patch merged into coreboot/master: e807c34 cmos post: Guard with spinlock
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit e807c34a5e34e8dd7cb959458de593ea1070fde4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 10 09:53:33 2013 -0700 cmos post: Guard with spinlock The CMOS post code storage mechanism does back-to-back CMOS reads and writes that may be interleaved during CPU bringup, leading to corruption of the log or of other parts of CMOS. Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58102 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/4227 for details. -gerrit

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Patch merged into coreboot/master: 35bd3fe Extend the ELOG errors for EC fan.
by gerrit＠coreboot.org 26 Nov '13

26 Nov '13

the following patch was just integrated into master: commit 35bd3fedfeafe96b5fb938c1b47e2b0380fdbfb7 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Sep 24 22:14:24 2012 -0600 Extend the ELOG errors for EC fan. Change-Id: Ida98f81b1ac1f6b3ba16c0b98e5c64756606fd58 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48318 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4126 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4126 for details. -gerrit

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Patch set updated for coreboot: 00aa9a1 amd/car/post_cache_as_ram: Switch stack in assembly rather than in C
by Vladimir Serbinenko 26 Nov '13

26 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4286 -gerrit commit 00aa9a192d02ae73f9c1d391b23666e19f40876e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 17:49:29 2013 +0100 amd/car/post_cache_as_ram: Switch stack in assembly rather than in C Compiler may do loads of optimisations around stack switch and so it's allowed to break stack switch as it sees fit. Do it in assembly instead. Not tested. Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 7 +++++++ src/cpu/amd/car/post_cache_as_ram.c | 21 +++++++++------------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..199083b 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -414,10 +414,17 @@ CAR_FAM10_ap_out: pushl %ebx /* Init detected. */ pushl %eax /* BIST */ call cache_as_ram_main + /* We will not go back. */ post_code(0xaf) /* Should never see this POST code. */ + .globl cache_as_ram_switch_stack + +cache_as_ram_switch_stack: + subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp + call cache_as_ram_new_stack + all_mtrr_msrs: /* fixed MTRR MSRs */ .long MTRRfix64K_00000_MSR diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index eca7673..afb13e4 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -75,6 +75,8 @@ static void vErrata343(void) #endif } +void cache_as_ram_switch_stack(void); + static void post_cache_as_ram(void) { #if CONFIG_HAVE_ACPI_RESUME @@ -92,9 +94,6 @@ static void post_cache_as_ram(void) } #endif - unsigned testx = 0x5a5a5a5a; - print_debug_pcar("testx = ", testx); - /* copy data from cache as ram to ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. */ @@ -112,21 +111,19 @@ static void post_cache_as_ram(void) vErrata343(); memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline + cache_as_ram_switch_stack(); +} - __asm__ volatile ( - /* set new esp */ /* before CONFIG_RAMBASE */ - "subl %0, %%esp\n\t" - ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) - /* discard all registers (eax is used for %0), so gcc redoes everything - after the stack is moved */ - : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" - ); +void +cache_as_ram_new_stack (void); +void +cache_as_ram_new_stack (void) +{ /* We can put data to stack again */ /* only global variable sysinfo in cache need to be offset */ print_debug("Done\n"); - print_debug_pcar("testx = ", testx); print_debug("Disabling cache as ram now \n");

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New patch to review for coreboot: aec67ba amd/car/post_cache_as_ram: Switch stack in assembly rather than in C
by Vladimir Serbinenko 26 Nov '13

26 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4286 -gerrit commit aec67ba8f659dfb818af9c5999cf8bfa1f9db206 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 17:49:29 2013 +0100 amd/car/post_cache_as_ram: Switch stack in assembly rather than in C Compiler may do loads of optimisations around stack switch and so it's allowed to break stack switch as it sees fit. Do it in assembly instead. Not tested. Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 7 +++++++ src/cpu/amd/car/post_cache_as_ram.c | 20 ++++++++------------ 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..199083b 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -414,10 +414,17 @@ CAR_FAM10_ap_out: pushl %ebx /* Init detected. */ pushl %eax /* BIST */ call cache_as_ram_main + /* We will not go back. */ post_code(0xaf) /* Should never see this POST code. */ + .globl cache_as_ram_switch_stack + +cache_as_ram_switch_stack: + subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp + call cache_as_ram_new_stack + all_mtrr_msrs: /* fixed MTRR MSRs */ .long MTRRfix64K_00000_MSR diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index eca7673..1d0ba7c 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -75,6 +75,8 @@ static void vErrata343(void) #endif } +void cache_as_ram_switch_stack(void); + static void post_cache_as_ram(void) { #if CONFIG_HAVE_ACPI_RESUME @@ -92,9 +94,6 @@ static void post_cache_as_ram(void) } #endif - unsigned testx = 0x5a5a5a5a; - print_debug_pcar("testx = ", testx); - /* copy data from cache as ram to ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. */ @@ -112,21 +111,18 @@ static void post_cache_as_ram(void) vErrata343(); memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline +} - __asm__ volatile ( - /* set new esp */ /* before CONFIG_RAMBASE */ - "subl %0, %%esp\n\t" - ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) - /* discard all registers (eax is used for %0), so gcc redoes everything - after the stack is moved */ - : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" - ); +void +cache_as_ram_new_stack (void); +void +cache_as_ram_new_stack (void) +{ /* We can put data to stack again */ /* only global variable sysinfo in cache need to be offset */ print_debug("Done\n"); - print_debug_pcar("testx = ", testx); print_debug("Disabling cache as ram now \n");

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Patch set updated for coreboot: da82222 Remove sprintf
by Vladimir Serbinenko 26 Nov '13

26 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4280 -gerrit commit da822227a7985f6efcccdacc32831038bf63bef5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 26 02:42:52 2013 +0100 Remove sprintf Remove sprintf as if you can't easily use snprintf then you probably have buffer overflow. Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 3 ++- src/console/vsprintf.c | 14 -------------- src/include/string.h | 1 - 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 121cb22..6496d75 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -274,7 +274,8 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(0x83); len = acpigen_write_len_f(); - sprintf(pscope, "\\_PR.CPU%x", (unsigned int) cpuindex); + snprintf(pscope, sizeof (pscope), + "\\_PR.CPU%x", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 3d085e9..99e3dc8 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -57,20 +57,6 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) return i; } -int sprintf(char *buf, const char *fmt, ...) -{ - va_list args; - int i; - - va_start(args, fmt); - /* A trick: we have at most (size_t)-1 adressable space anyway, so - if we output so much we'll crash anyway. */ - i = vsnprintf(buf, -1, fmt, args); - va_end(args); - - return i; -} - int snprintf(char *buf, size_t size, const char *fmt, ...) { va_list args; diff --git a/src/include/string.h b/src/include/string.h index dc125e1..b4d0268 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -16,7 +16,6 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) -int sprintf(char * buf, const char *fmt, ...); int snprintf(char * buf, size_t size, const char *fmt, ...); #endif

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coreboot-gerrit November 2013