coreboot-gerrit November 2013

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Patch set updated for coreboot: d13f5e9 lynxpoint: Enable SerialIO clock in PCI mode
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4180 -gerrit commit d13f5e9ff43d7a198545d5e098af9b1446e2f77a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 16:37:40 2013 -0700 lynxpoint: Enable SerialIO clock in PCI mode The clock gating register at offset 0x800 is managed by the clock driver in the kernel when the devices are in ACPI mode. When in PCI mode we should force enable the clock here. When in ACPI mode or the device is disabled it should be put in D3Hot state. > i2cdetect -y -r 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56122 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 26 ++++++++++++++++++++----- src/southbridge/intel/lynxpoint/pch.h | 6 ++++++ src/southbridge/intel/lynxpoint/serialio.c | 31 ++++++++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cc3718d..58c68cd 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -83,10 +83,18 @@ u16 get_gpiobase(void) #ifndef __SMM__ +/* Put device in D3Hot Power State */ +static void pch_enable_d3hot(device_t dev) +{ + u32 reg32 = pci_read_config32(dev, PCH_PCS); + reg32 |= PCH_PCS_PS_D3HOT; + pci_write_config32(dev, PCH_PCS, reg32); +} + /* Set bit in Function Disble register to hide this device */ -static void pch_hide_devfn(unsigned devfn) +static void pch_hide_devfn(device_t dev) { - switch (devfn) { + switch (dev->path.pci.devfn) { case PCI_DEVFN(19, 0): /* Audio DSP */ RCBA32_OR(FD, PCH_DISABLE_ADSPD); break; @@ -94,24 +102,31 @@ static void pch_hide_devfn(unsigned devfn) RCBA32_OR(FD, PCH_DISABLE_XHCI); break; case PCI_DEVFN(21, 0): /* DMA */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 1): /* I2C0 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 2): /* I2C1 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 3): /* SPI0 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 4): /* SPI1 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 5): /* UART0 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 6): /* UART1 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(22, 0): /* MEI #1 */ @@ -127,6 +142,7 @@ static void pch_hide_devfn(unsigned devfn) RCBA32_OR(FD2, PCH_DISABLE_KT); break; case PCI_DEVFN(23, 0): /* SDIO */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ @@ -146,7 +162,7 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ - RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); + RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); break; case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); @@ -404,7 +420,7 @@ static void pch_pcie_enable(device_t dev) new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); /* Hide this device if possible */ - pch_hide_devfn(dev->path.pci.devfn); + pch_hide_devfn(dev); } else { int fn; @@ -463,7 +479,7 @@ void pch_enable(device_t dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* Hide this device if possible */ - pch_hide_devfn(dev->path.pci.devfn); + pch_hide_devfn(dev); } else { /* Enable SERR */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ca1d8b1..b01fdc0 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -218,6 +218,10 @@ void set_gpio(int gpio_num, int value); #define SEE (1 << 1) #define PERE (1 << 0) +/* Power Management Control and Status */ +#define PCH_PCS 0x84 +#define PCH_PCS_PS_D3HOT 3 + #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) @@ -377,6 +381,8 @@ void set_gpio(int gpio_num, int value); #define SIO_ID_UART1 6 /* D21:F6 */ #define SIO_ID_SDIO 7 /* D23:F0 */ +#define SIO_REG_PPR_CLOCK 0x800 +#define SIO_REG_PPR_CLOCK_EN (1 << 0) #define SIO_REG_PPR_RST 0x804 #define SIO_REG_PPR_RST_ASSERT 0x3 #define SIO_REG_PPR_GEN 0x808 diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 11d6a36..8257cc2 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -29,6 +29,22 @@ #include "pch.h" #include "nvs.h" +/* Set D3Hot Power State in ACPI mode */ +static void serialio_enable_d3hot(struct device *dev) +{ + u32 reg32 = pci_read_config32(dev, PCH_PCS); + reg32 |= PCH_PCS_PS_D3HOT; + pci_write_config32(dev, PCH_PCS, reg32); +} + +/* Enable clock in PCI mode */ +static void serialio_enable_clock(struct resource *bar0) +{ + u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK); + reg32 |= SIO_REG_PPR_CLOCK_EN; + write32(bar0->base + SIO_REG_PPR_CLOCK, reg32); +} + /* Put Serial IO D21:F0-F6 device into desired mode. */ static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) { @@ -143,9 +159,15 @@ static void serialio_init(struct device *dev) struct southbridge_intel_lynxpoint_config *config = dev->chip_info; struct resource *bar0, *bar1; int sio_index = -1; + u32 reg32; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); + /* Ensure memory and bus master are enabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); if (!bar0) @@ -154,6 +176,11 @@ static void serialio_init(struct device *dev) if (!bar1) return; + if (!config->sio_acpi_mode) + serialio_enable_clock(bar0); + else if (dev->path.pci.devfn != PCI_DEVFN(21, 0)) + serialio_enable_d3hot(dev); /* all but SDMA */ + switch (dev->path.pci.devfn) { case PCI_DEVFN(21, 0): /* SDMA */ sio_index = SIO_ID_SDMA; @@ -241,9 +268,9 @@ static struct pci_operations pci_ops = { }; static struct device_operations device_ops = { - .read_resources = pci_bus_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, + .enable_resources = pci_dev_enable_resources, .init = serialio_init, .ops_pci = &pci_ops, };

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Patch set updated for coreboot: 7b1b96c slippy: Put SerialIO devices in PCI mode
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4171 -gerrit commit 7b1b96cb44d0c62361454c40e716862ca8c11def Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 15 15:05:38 2013 -0700 slippy: Put SerialIO devices in PCI mode The device at function 0 also needs to be enabled or the kernel will ignore all other functions. 00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03) 00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03) 00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03) Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51370 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 665e6dc..143147f 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -56,13 +56,13 @@ chip northbridge/intel/haswell register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" + register "sio_acpi_mode" = "0" register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA + device pci 15.0 on end # Serial I/O DMA device pci 15.1 on end # I2C0 device pci 15.2 on end # I2C1 device pci 15.3 off end # GSPI0

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Patch set updated for coreboot: 9f4cbad Fix int15 return value for mainboard oprom handlers
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4168 -gerrit commit 9f4cbad60c2936872b0e95b7e625eadc3bc371d4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 10 13:50:09 2013 -0700 Fix int15 return value for mainboard oprom handlers These boards were returning 0 to indicate success when the realmode handler expects it to return 1 to indicate that it handled the interrupt. Change-Id: I2baeaf8c2774fa7668a8b2f2d9ad698302eefb21 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50881 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/google/butterfly/mainboard.c | 16 ++++++++-------- src/mainboard/google/link/mainboard.c | 18 +++++++++--------- src/mainboard/google/parrot/mainboard.c | 16 ++++++++-------- src/mainboard/google/slippy/mainboard.c | 16 ++++++++-------- src/mainboard/google/stout/mainboard.c | 16 ++++++++-------- src/mainboard/intel/baskingridge/mainboard.c | 16 ++++++++-------- src/mainboard/intel/wtm2/mainboard.c | 16 ++++++++-------- 7 files changed, 57 insertions(+), 57 deletions(-) diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index c33b9cf..32a8308 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -194,7 +194,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res = -1; + int res = 0; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", __func__, X86_AX); @@ -210,7 +210,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f35: /* @@ -226,7 +226,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f51: /* @@ -238,7 +238,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0001; /* Int-LVDS */ - res = 0; + res = 1; break; case 0x5f70: switch (X86_CH) { @@ -246,25 +246,25 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", X86_CH); - return 0; + break; } break; diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 01d4484..2731df0 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -64,7 +64,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res=-1; + int res = 0; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", __func__, X86_AX); @@ -80,7 +80,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f35: /* @@ -96,7 +96,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f51: /* @@ -108,7 +108,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0003; /* eDP */ - res = 0; + res = 1; break; case 0x5f70: switch (X86_CH) { @@ -116,29 +116,29 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", X86_CH); - return 0; + break; } break; case 0x5fac: - res = 0; + res = 1; break; default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index c07d9e2..bc505be 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -52,7 +52,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res=-1; + int res = 0; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", __func__, X86_AX); @@ -68,7 +68,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f35: /* @@ -84,7 +84,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f51: /* @@ -96,7 +96,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0003; /* eDP */ - res = 0; + res = 1; break; case 0x5f70: switch (X86_CH) { @@ -104,25 +104,25 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", X86_CH); - return 0; + break; } break; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 8efe77b..c91be19 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -45,7 +45,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res=-1; + int res = 0; printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, X86_AX, X86_BX, X86_CX, X86_DX); @@ -61,7 +61,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0001; - res = 0; + res = 1; break; case 0x5f35: /* @@ -77,7 +77,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 0x5f51: /* @@ -89,7 +89,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0003; - res = 0; + res = 1; break; case 0x5f70: switch ((X86_CX >> 8) & 0xff) { @@ -97,26 +97,26 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); - return 0; + break; } break; diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 62ac7ea..7f6b7dd 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -52,7 +52,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res=-1; + int res = 0; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", __func__, X86_AX); @@ -68,7 +68,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f35: /* @@ -84,7 +84,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; /* Use video bios default */ - res = 0; + res = 1; break; case 0x5f51: /* @@ -96,7 +96,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0001; - res = 0; + res = 1; break; case 0x5f70: switch (X86_CH) { @@ -104,25 +104,25 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", X86_CH); - return 0; + break; } break; diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index d49ba45..69943cb 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -45,7 +45,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res=-1; + int res = 0; printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, X86_AX, X86_BX, X86_CX, X86_DX); @@ -61,7 +61,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0001; - res = 0; + res = 1; break; case 0x5f35: /* @@ -77,7 +77,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 0x5f51: /* @@ -89,7 +89,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0003; - res = 0; + res = 1; break; case 0x5f70: switch ((X86_CX >> 8) & 0xff) { @@ -97,26 +97,26 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); - return 0; + break; } break; diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index d49ba45..e7650fa 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -45,7 +45,7 @@ void mainboard_suspend_resume(void) #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { - int res=-1; + int res = 1; printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, X86_AX, X86_BX, X86_CX, X86_DX); @@ -61,7 +61,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0001; - res = 0; + res = 1; break; case 0x5f35: /* @@ -77,7 +77,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 0x5f51: /* @@ -89,7 +89,7 @@ static int int15_handler(void) */ X86_AX = 0x005f; X86_CX = 0x0003; - res = 0; + res = 1; break; case 0x5f70: switch ((X86_CX >> 8) & 0xff) { @@ -97,26 +97,26 @@ static int int15_handler(void) /* Get Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 1: /* Set Mux */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; case 2: /* Get SG/Non-SG mode */ X86_AX = 0x005f; X86_CX = 0x0000; - res = 0; + res = 1; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); - return 0; + break; } break;

1 0

Patch set updated for coreboot: 404af8c slippy: Minor vboot related fixes
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4169 -gerrit commit 404af8cfb4fc08d10c2978a2603fa2efc9879c37 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 14 11:16:34 2013 -0700 slippy: Minor vboot related fixes - Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/google/slippy/acpi_tables.c | 6 ++++-- src/mainboard/google/slippy/chromeos.c | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 22 +++++++++++++++++++--- src/southbridge/intel/lynxpoint/lpc.c | 20 +------------------- src/vendorcode/google/chromeos/gnvs.c | 8 +++++++- 6 files changed, 32 insertions(+), 27 deletions(-) diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index a53ac00..a2ef673 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index e08a7ce..9c179e8 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -31,6 +31,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h> extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -99,8 +100,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) #if CONFIG_CHROMEOS // TODO(reinauer) this could move elsewhere? chromeos_init_vboot(&(gnvs->chromeos)); - /* Emerald Lake has no EC (?) */ - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif /* Update the mem console pointer. */ diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 51d625b..1b70fde 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* The dev-switch is virtual */ int get_developer_mode_switch(void) { - return 0; + return 1; } /* There are actually two recovery switches. One is the magic keyboard chord, diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 7a24e1f..38506c9 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,10 +20,12 @@ #include <console/console.h> #include <arch/io.h> +#include <device/device.h> #include <device/pci_def.h> #include <timestamp.h> #include <elog.h> #include "pch.h" +#include "chip.h" #if CONFIG_INTEL_LYNXPOINT_LP #include "lp_gpio.h" @@ -96,15 +98,29 @@ static int sleep_type_s3(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct southbridge_intel_lynxpoint_config *config = NULL; /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } int early_pch_init(const void *gpio_map, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c3b5322..33d74f1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -520,18 +520,6 @@ static void pch_fixups(struct device *dev) RCBA32_OR(0x21a8, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -712,12 +700,6 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void pch_lpc_enable_resources(device_t dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(device_t dev) { /* Enable PCH Display Port */ @@ -745,7 +727,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .init = lpc_init, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 5ee3665..ba1588d 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -49,9 +49,15 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - if (vboot_handoff != NULL) + if (vboot_handoff != NULL) { + vboot_handoff->init_params.flags |= VB_INIT_FLAG_OPROM_MATTERS; + if (oprom_is_loaded) + vboot_handoff->init_params.flags |= + VB_INIT_FLAG_OPROM_LOADED; + memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], ARRAY_SIZE(chromeos->vdat)); + } #endif #if CONFIG_ELOG

1 0

Patch set updated for coreboot: d2571d6 libpayload (EHCI): correctly align PORTSC
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4174 -gerrit commit d2571d649963cbadecd7984438c2e56b4fae8bec Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 17 11:56:09 2013 -0700 libpayload (EHCI): correctly align PORTSC Two structures in the USB EHCI stack were pointing to hardware but not marked attribute((packed)) hence leaving it to GCC to correctly align the data structures. Next, the number of reserved bytes in hc_op_t was wrong (but implicitly aligned to the correct values on x86) It seems this worked fine on x86, but on ARM it was doing the wrong thing. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d Reviewed-on: https://gerrit.chromium.org/gerrit/55555 Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/drivers/usb/ehci_private.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index 3b9faf6..3365be1 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -78,10 +78,10 @@ typedef volatile struct { u32 ctrldssegment; u32 periodiclistbase; u32 asynclistaddr; - u8 res1[0x3f-0x1c]; + u8 res1[0x40-0x1c]; u32 configflag; portsc_t portsc[0]; -} hc_op_t; +} __attribute__ ((packed)) hc_op_t; typedef volatile struct { #define QTD_TERMINATE 1 @@ -130,7 +130,7 @@ typedef volatile struct { #define QH_PIPE_MULTIPLIER_SHIFT 30 volatile u32 current_td_ptr; volatile qtd_t td; -} ehci_qh_t; +} __attribute__ ((packed)) ehci_qh_t; typedef struct ehci { hc_cap_t *capabilities;

1 0

Patch set updated for coreboot: 7f8aaf2 libpayload: Add USB support for non-PCI controllers
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4175 -gerrit commit 7f8aaf2f994c8f2d79de77bcb0c2f960e7c3af18 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 2 16:16:41 2013 -0700 libpayload: Add USB support for non-PCI controllers Restructure USB stack to not depend on PCI, and make PCI stub available on x86, but provide fixed BARs for ARM (Exynos 5) Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49970 --- payloads/libpayload/Config.in | 28 ++++++++++++++++-- payloads/libpayload/drivers/usb/ehci.c | 41 ++++++++++++++++---------- payloads/libpayload/drivers/usb/ehci.h | 3 +- payloads/libpayload/drivers/usb/ehci_private.h | 1 - payloads/libpayload/drivers/usb/ehci_rh.c | 2 ++ payloads/libpayload/drivers/usb/ohci.c | 24 +++++++++++---- payloads/libpayload/drivers/usb/ohci.h | 5 ++-- payloads/libpayload/drivers/usb/ohci_private.h | 1 - payloads/libpayload/drivers/usb/uhci.c | 11 +++---- payloads/libpayload/drivers/usb/uhci.h | 4 +-- payloads/libpayload/drivers/usb/usbhub.c | 2 ++ payloads/libpayload/drivers/usb/usbinit.c | 33 +++++++++++++++++---- payloads/libpayload/drivers/usb/usbmsc.c | 1 + payloads/libpayload/drivers/usb/xhci.c | 36 ++++++++++++++-------- payloads/libpayload/drivers/usb/xhci.h | 5 ++-- payloads/libpayload/include/usb/usb.h | 3 +- 16 files changed, 142 insertions(+), 58 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 6610f8f..bb5176f 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -326,7 +326,7 @@ config USB config USB_UHCI bool "Support for USB UHCI controllers" - depends on USB + depends on USB && ARCH_X86 help Select this option if you are going to use USB 1.1 on an Intel based system. @@ -335,7 +335,7 @@ config USB_OHCI bool "Support for USB OHCI controllers" depends on USB help - Select this option if you are going to use USB 1.1 on an AMD based + Select this option if you are going to use USB 1.1 on a non-Intel based system. config USB_EHCI @@ -382,6 +382,30 @@ config USB_GEN_HUB bool default n if (!USB_HUB && !USB_XHCI) default y if (USB_HUB || USB_XHCI) +config USB_PCI + bool + default y if ARCH_X86 + default n + +config USB_MEMORY + bool + default y if ARCH_ARMV7 + default n + +config USB_OHCI_BASE_ADDRESS + hex + depends on USB_MEMORY && USB_OHCI + default 0x12120000 + +config USB_EHCI_BASE_ADDRESS + hex + depends on USB_MEMORY && USB_EHCI + default 0x12110000 + +config USB_XHCI_BASE_ADDRESS + hex + depends on USB_MEMORY && USB_XHCI + default 0x12000000 endmenu diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index f5c14d5..e61e806 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -69,7 +69,7 @@ static void dump_td(u32 addr) usb_debug("+---------------------------------------------------+\n"); } -#ifdef USB_DEBUG +#if 0 && defined(USB_DEBUG) static void dump_qh(ehci_qh_t *cur) { qtd_t *tmp_qtd = NULL; @@ -724,7 +724,7 @@ static u8 *ehci_poll_intr_queue(void *const queue) } hci_t * -ehci_init (pcidev_t addr) +ehci_init (void *bar) { int i; hci_t *controller = new_controller (); @@ -736,15 +736,6 @@ ehci_init (pcidev_t addr) if(!controller->instance) fatal("Not enough memory creating USB controller instance.\n"); -#define PCI_COMMAND 4 -#define PCI_COMMAND_IO 1 -#define PCI_COMMAND_MEMORY 2 -#define PCI_COMMAND_MASTER 4 - - u32 pci_command = pci_read_config32(addr, PCI_COMMAND); - pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; - pci_write_config32(addr, PCI_COMMAND, pci_command); - controller->type = EHCI; controller->start = ehci_start; @@ -760,8 +751,7 @@ ehci_init (pcidev_t addr) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; - controller->bus_address = addr; - controller->reg_base = pci_read_config32 (controller->bus_address, USBBASE); + controller->reg_base = (u32)(unsigned long)bar; for (i = 0; i < 128; i++) { controller->devices[i] = 0; } @@ -770,9 +760,6 @@ ehci_init (pcidev_t addr) EHCI_INST(controller)->capabilities = phys_to_virt(controller->reg_base); EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(controller->reg_base) + EHCI_INST(controller)->capabilities->caplength); - /* default value for frame length adjust */ - pci_write_config8(addr, FLADJ, FLADJ_framelength(60000)); - /* Set the high address word (aka segment) if controller is 64-bit */ if (EHCI_INST(controller)->capabilities->hccparams & 1) EHCI_INST(controller)->operation->ctrldssegment = 0; @@ -818,3 +805,25 @@ ehci_init (pcidev_t addr) return controller; } + +#ifdef CONFIG_USB_PCI +hci_t * +ehci_pci_init (pcidev_t addr) +{ + hci_t *controller; + u32 reg_base; + + u32 pci_command = pci_read_config32(addr, PCI_COMMAND); + pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; + pci_write_config32(addr, PCI_COMMAND, pci_command); + + reg_base = pci_read_config32 (addr, USBBASE); + + /* default value for frame length adjust */ + pci_write_config8(addr, FLADJ, FLADJ_framelength(60000)); + + controller = ehci_init((void *)(unsigned long)reg_base); + + return controller; +} +#endif diff --git a/payloads/libpayload/drivers/usb/ehci.h b/payloads/libpayload/drivers/usb/ehci.h index c66643c..c1b1fa9 100644 --- a/payloads/libpayload/drivers/usb/ehci.h +++ b/payloads/libpayload/drivers/usb/ehci.h @@ -33,7 +33,8 @@ #include <pci.h> #include <usb/usb.h> -hci_t *ehci_init (pcidev_t addr); +hci_t *ehci_pci_init (pcidev_t addr); +hci_t *ehci_init (void *bar); void ehci_rh_init (usbdev_t *dev); diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index 3365be1..986ee79 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -30,7 +30,6 @@ #ifndef __EHCI_PRIVATE_H #define __EHCI_PRIVATE_H -#include <pci.h> #include <usb/usb.h> #define USBBASE 0x10 diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 8982804..5c4daed 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -27,6 +27,8 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG + #include <libpayload.h> #include "ehci.h" #include "ehci_private.h" diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 95db5f4..edd275b 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -136,7 +136,7 @@ ohci_reinit (hci_t *controller) { } -#ifdef USB_DEBUG +#if 0 && defined(USB_DEBUG) /* Section 4.3.3 */ static const char *completion_codes[] = { "No error", @@ -167,7 +167,7 @@ static const char *direction[] = { #endif hci_t * -ohci_init (pcidev_t addr) +ohci_init (void *bar) { int i; @@ -201,10 +201,7 @@ ohci_init (pcidev_t addr) init_device_entry (controller, 0); OHCI_INST (controller)->roothub = controller->devices[0]; - controller->bus_address = addr; - /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4 - * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ - controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear + controller->reg_base = (u32)(unsigned long)bar; OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); usb_debug("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); @@ -255,6 +252,21 @@ ohci_init (pcidev_t addr) return controller; } +#ifdef CONFIG_USB_PCI +hci_t * +ohci_pci_init (pcidev_t addr) +{ + u32 reg_base; + + /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4 + * BASE ADDRESS only [31-12] bits. All other usually 0, but not all. + * OHCI mandates MMIO, so bit 0 is clear */ + reg_base = pci_read_config32 (addr, 0x10) & 0xfffff000; + + return ohci_init((void *)(unsigned long)reg_base); +} +#endif + static void ohci_shutdown (hci_t *controller) { diff --git a/payloads/libpayload/drivers/usb/ohci.h b/payloads/libpayload/drivers/usb/ohci.h index f501167..9c31d9c 100644 --- a/payloads/libpayload/drivers/usb/ohci.h +++ b/payloads/libpayload/drivers/usb/ohci.h @@ -33,8 +33,9 @@ #include <pci.h> #include <usb/usb.h> - hci_t *ohci_init (pcidev_t addr); +hci_t *ohci_pci_init (pcidev_t addr); +hci_t *ohci_init (void *bar); - void ohci_rh_init (usbdev_t *dev); +void ohci_rh_init (usbdev_t *dev); #endif diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h index a32203c..b6eaf6b 100644 --- a/payloads/libpayload/drivers/usb/ohci_private.h +++ b/payloads/libpayload/drivers/usb/ohci_private.h @@ -30,7 +30,6 @@ #ifndef __OHCI_PRIVATE_H #define __OHCI_PRIVATE_H -#include <pci.h> #include <usb/usb.h> #define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit)) diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index f9c361d..b81b911 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -147,7 +147,7 @@ uhci_reinit (hci_t *controller) } hci_t * -uhci_init (pcidev_t addr) +uhci_pci_init (pcidev_t addr) { int i; u16 reg16; @@ -182,16 +182,17 @@ uhci_init (pcidev_t addr) init_device_entry (controller, 0); UHCI_INST (controller)->roothub = controller->devices[0]; - controller->bus_address = addr; - controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1; /* ~1 clears the register type indicator that is set to 1 for IO space */ + /* ~1 clears the register type indicator that is set to 1 + * for IO space */ + controller->reg_base = pci_read_config32 (addr, 0x20) & ~1; /* kill legacy support handler */ uhci_stop (controller); mdelay (1); uhci_reg_write16 (controller, USBSTS, 0x3f); - reg16 = pci_read_config16(controller->bus_address, 0xc0); + reg16 = pci_read_config16(addr, 0xc0); reg16 &= 0xdf80; - pci_write_config16 (controller->bus_address, 0xc0, reg16); + pci_write_config16 (addr, 0xc0, reg16); UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t)); /* 4kb aligned to 4kb */ if (! UHCI_INST (controller)->framelistptr) diff --git a/payloads/libpayload/drivers/usb/uhci.h b/payloads/libpayload/drivers/usb/uhci.h index 2ef3f0b..6bb5c17 100644 --- a/payloads/libpayload/drivers/usb/uhci.h +++ b/payloads/libpayload/drivers/usb/uhci.h @@ -33,8 +33,8 @@ #include <pci.h> #include <usb/usb.h> - hci_t *uhci_init (pcidev_t addr); +hci_t *uhci_pci_init (pcidev_t addr); - void uhci_rh_init (usbdev_t *dev); +void uhci_rh_init (usbdev_t *dev); #endif diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 20e064e..4e077f6 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -27,6 +27,8 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG + #include <usb/usb.h> #include "generic_hub.h" diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 76653ff..f74a833 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG #include <libpayload-config.h> #include <usb/usb.h> #include "uhci.h" @@ -35,6 +36,7 @@ #include "xhci.h" #include <usb/usbdisk.h> +#ifdef CONFIG_USB_PCI /** * Initializes USB controller attached to PCI * @@ -58,8 +60,6 @@ static int usb_controller_initialize(int bus, int dev, int func) prog_if = (class >> 8) & 0xff; /* enable busmaster */ -#define PCI_COMMAND 4 -#define PCI_COMMAND_MASTER 4 if (devclass == 0xc03) { u32 pci_command; @@ -73,7 +73,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x00: #ifdef CONFIG_USB_UHCI usb_debug("UHCI controller\n"); - uhci_init (pci_device); + uhci_pci_init (pci_device); #else usb_debug("UHCI controller (not supported)\n"); #endif @@ -82,7 +82,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x10: #ifdef CONFIG_USB_OHCI usb_debug("OHCI controller\n"); - ohci_init(pci_device); + ohci_pci_init(pci_device); #else usb_debug("OHCI controller (not supported)\n"); #endif @@ -91,7 +91,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x20: #ifdef CONFIG_USB_EHCI usb_debug("EHCI controller\n"); - ehci_init(pci_device); + ehci_pci_init(pci_device); #else usb_debug("EHCI controller (not supported)\n"); #endif @@ -100,7 +100,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x30: #ifdef CONFIG_USB_XHCI usb_debug("xHCI controller\n"); - xhci_init(pci_device); + xhci_pci_init(pci_device); #else usb_debug("xHCI controller (not supported)\n"); #endif @@ -154,12 +154,33 @@ static void usb_scan_pci_bus(int bus) } } } +#endif + +#ifdef CONFIG_USB_MEMORY +static void usb_scan_memory(void) +{ +#ifdef CONFIG_USB_XHCI + xhci_init((void *)(unsigned long)CONFIG_USB_XHCI_BASE_ADDRESS); +#endif +#ifdef CONFIG_USB_EHCI + ehci_init((void *)(unsigned long)CONFIG_USB_EHCI_BASE_ADDRESS); +#endif +#ifdef CONFIG_USB_OHCI + ohci_init((void *)(unsigned long)CONFIG_USB_OHCI_BASE_ADDRESS); +#endif +} +#endif /** * Initialize all USB controllers attached to PCI. */ int usb_initialize(void) { +#ifdef CONFIG_USB_PCI usb_scan_pci_bus(0); +#endif +#ifdef CONFIG_USB_MEMORY + usb_scan_memory(); +#endif return 0; } diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 16af448..ad7e82f 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG #include <endian.h> #include <usb/usb.h> #include <usb/usbmsc.h> diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 51f9422..aa2fe57 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -143,7 +143,7 @@ xhci_wait_ready(xhci_t *const xhci) } hci_t * -xhci_init (const pcidev_t addr) +xhci_init (const void *bar) { int i; @@ -192,14 +192,7 @@ xhci_init (const pcidev_t addr) goto _free_xhci; } - /* Now, gather information and check for compatibility */ - - controller->bus_address = addr; - controller->reg_base = pci_read_config32(addr, REG_BAR0) & ~0xf; - if (pci_read_config32(addr, REG_BAR1) > 0) { - xhci_debug("We don't do 64bit addressing\n"); - goto _free_xhci; - } + controller->reg_base = (u32)(unsigned long)bar; xhci->capreg = phys_to_virt(controller->reg_base); xhci->opreg = ((void *)xhci->capreg) + xhci->capreg->caplength; @@ -270,7 +263,6 @@ xhci_init (const pcidev_t addr) } /* Now start working on the hardware */ - if (xhci_wait_ready(xhci)) goto _free_xhci; @@ -279,8 +271,6 @@ xhci_init (const pcidev_t addr) xhci_reset(controller); xhci_reinit(controller); - xhci_switch_ppt_ports(addr); - xhci->roothub->controller = controller; xhci->roothub->init = xhci_rh_init; xhci->roothub->init(xhci->roothub); @@ -308,6 +298,28 @@ _free_controller: return NULL; } +#ifdef CONFIG_USB_PCI +hci_t * +xhci_pci_init (pcidev_t addr) +{ + u32 reg_addr; + hci_t controller; + + reg_addr = (u32)phys_to_virt(pci_read_config32 (addr, 0x10) & ~0xf); + //controller->reg_base = pci_read_config32 (addr, 0x14) & ~0xf; + if (pci_read_config32 (addr, 0x14) > 0) { + fatal("We don't do 64bit addressing.\n"); + } + + controller = xhci_init((void *)(unsigned long)reg_addr); + controller->bus_address = addr; + + xhci_switch_ppt_ports(addr); + + return controller; +} +#endif + static void xhci_reset(hci_t *const controller) { diff --git a/payloads/libpayload/drivers/usb/xhci.h b/payloads/libpayload/drivers/usb/xhci.h index b900b12..b76c982 100644 --- a/payloads/libpayload/drivers/usb/xhci.h +++ b/payloads/libpayload/drivers/usb/xhci.h @@ -33,8 +33,9 @@ #include <pci.h> #include <usb/usb.h> - hci_t *xhci_init (pcidev_t addr); +hci_t *xhci_pci_init (pcidev_t addr); +hci_t *xhci_init (void *bar); - void xhci_rh_init (usbdev_t *dev); +void xhci_rh_init (usbdev_t *dev); #endif diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index ab45708..a351690 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -30,7 +30,7 @@ #ifndef __USB_H #define __USB_H #include <libpayload.h> -#include <pci.h> +#include <pci/pci.h> typedef enum { host_to_device = 0, device_to_host = 1 } dev_req_dir; typedef enum { standard_type = 0, class_type = 1, vendor_type = @@ -118,7 +118,6 @@ typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3} hc_type; struct usbdev_hc { hci_t *next; - pcidev_t bus_address; u32 reg_base; hc_type type; usbdev_t *devices[128]; // dev 0 is root hub, 127 is last addressable

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Patch set updated for coreboot: 38875c3 slippy: set PWM values
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4172 -gerrit commit 38875c350e642a7b26281736d4c487cae5d5c77e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 15 17:02:23 2013 -0700 slippy: set PWM values The dev screen was not displaying properly. With the PWM values programmed the screen displays correctly. Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51472 --- src/mainboard/google/slippy/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 143147f..29c4763 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -9,6 +9,10 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end

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Patch set updated for coreboot: 992d2d9 lynxpoint: update azalia device ids
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4173 -gerrit commit 992d2d93142fdaaa1bf362dc039af981e26003ba Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 20 15:57:16 2013 -0500 lynxpoint: update azalia device ids The vendor ids were never updated to reflect LynxPoint's device ids. Therefore, none of the initialization was being ran. Fix this. Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55821 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/azalia.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 0e62676..ee12042 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -365,7 +365,7 @@ static struct device_operations azalia_ops = { .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; +static const unsigned short pci_device_ids[] = { 0x8c20, 0x9c20, 0 }; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops,

1 0

Patch set updated for coreboot: d2be2ae haswell: Update ChromeOS ACPI GPIO package
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4162 -gerrit commit d2be2aec9a41c44ae94f513a14584d829b0bebe9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 7 11:31:33 2013 -0700 haswell: Update ChromeOS ACPI GPIO package The chromeos_acpi driver sysfs naming is not what crossystem expects if there is just one entry in the package because it does not add a ".#" suffix in that case. Specify all the expected GPIOs on wtm2 as undefined, which should be 0xFF and not 0x00 becuase 0 is a valid GPIO. Change-Id: I9b17e9bab94219695e65b17914c84acf02a0983b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50337 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/acpi/chromeos.asl | 6 +++--- src/mainboard/intel/wtm2/acpi/chromeos.asl | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl index 307e2e2..da4fb40 100644 --- a/src/mainboard/intel/baskingridge/acpi/chromeos.asl +++ b/src/mainboard/intel/baskingridge/acpi/chromeos.asl @@ -18,7 +18,7 @@ */ Name(OIPG, Package() { - Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch - Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect + Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery + Package () { 0x0002, 0, 48, "LynxPoint" }, // developer + Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect }) diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl index c6b258b..40ffcf0 100644 --- a/src/mainboard/intel/wtm2/acpi/chromeos.asl +++ b/src/mainboard/intel/wtm2/acpi/chromeos.asl @@ -18,6 +18,7 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery + Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer + Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect })

1 0

Patch set updated for coreboot: cc9fce9 haswell: Remove limit on package C-state
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4163 -gerrit commit cc9fce9e263b9d5ed7d18c2b95b3dad99294b9cc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 7 13:19:56 2013 -0700 haswell: Remove limit on package C-state With the XHCI controller enabled we no longer hang the system when dropping into a package C-state so remove the code that was disabling it. Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50355 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 071135c..b2e6eaf 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -426,10 +426,7 @@ static void configure_c_states(void) msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - msr.lo &= ~(0xf); // Clear deepest package c-state - /* FIXME: The deepest package c-state is set to C0/C1 to work around - * platform instability when package C3 or deeper c-states are used. */ - msr.lo |= 0; // Deepeset package c-state is C0/C1. + /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);

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coreboot-gerrit November 2013