coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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856 discussions

New patch to review for coreboot: a16a9b5 haswell: check for clean reset
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4216 -gerrit commit a16a9b510e4338b9d58bc75c37ad36d2032833d5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 30 10:40:54 2013 -0500 haswell: check for clean reset When an INIT# is delivered to the CPU the CPU starts executing from the reset vector. However, the internal state is maintained. Therefore, check for such a condition and reset the system. Issues 'apreset warm' on the EC console. INIT# is sent and CPU notices it's not a clean reset and forces one. No hangs. Change-Id: I71229e0e5015ba8c60f5989c533268604ecc1ecc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57111 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/haswell/bootblock.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index bb065c8..e502cfa 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -112,10 +112,28 @@ static void set_flex_ratio_to_tdp_nominal(void) } } +static void check_for_clean_reset(void) +{ + msr_t msr; + msr = rdmsr(MTRRdefType_MSR); + + /* Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. */ + if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { + outb(0x0, 0xcf9); + outb(0x6, 0xcf9); + while (1) { + asm("hlt"); + } + } +} + static void bootblock_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); + check_for_clean_reset(); enable_rom_caching(); intel_update_microcode_from_cbfs(); }

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New patch to review for coreboot: 5629511 libpayload: place dummy_media.c in correct object list
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4215 -gerrit commit 56295112157550c0f16d510e7644624f459ec205 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 29 08:06:17 2013 -0500 libpayload: place dummy_media.c in correct object list The commit introducing dummy_media.c was placed in the libc object list. This wasn't correct. It should be in the libcbfs object list as well as guarded by CONFIG_CBFS. Change-Id: Iace43fff8f85f60ecac5e6eb8350cd1f3ee9d35e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56925 --- payloads/libpayload/arch/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index e8ca109..c37328e 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -34,4 +34,4 @@ libc-y += virtual.c libc-y += memcpy.S memset.S libc-y += exception_asm.S exception.c libc-y += cache.c -libc-y += dummy_media.c +libcbfs-$(CONFIG_CBFS) += dummy_media.c

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New patch to review for coreboot: 0ba4803 Butterfly: Force DDR refresh rate to 2x.
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4214 -gerrit commit 0ba48038676e8b1edaf21ac1d2bdbe82c05d1561 Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Wed May 8 11:45:23 2013 -0700 Butterfly: Force DDR refresh rate to 2x. Due to OEM request, always set DDR refresh rate at 2x. Change-Id: I81a4f57aca6388551dca6effbd9a4ac1a97e4f5a Reviewed-on: https://gerrit.chromium.org/gerrit/50477 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/butterfly/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index f56884d..67e509e 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -162,6 +162,7 @@ void main(unsigned long bist) { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, + ddr_refresh_rate_config: 2, /* Force double refresh rate */ }; timestamp_init(get_initial_timestamp());

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New patch to review for coreboot: c515ad3 Add DDR refresh config to pei data structure.
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4213 -gerrit commit c515ad3983e0bea7526f93333dc603563e6edd31 Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Wed May 8 11:41:04 2013 -0700 Add DDR refresh config to pei data structure. Allow platform customized DDR config, including forcing refresh rate to 2x. Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2 Reviewed-on: https://gerrit.chromium.org/gerrit/50476 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/northbridge/intel/sandybridge/pei_data.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index d317515..5e0ff0f 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -121,6 +121,14 @@ struct pei_data * 2 2N */ int nmode; + /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + int ddr_refresh_rate_config; } __attribute__((packed)); #endif

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New patch to review for coreboot: 2ab3688 peppy: Re-enable EC software sync
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4212 -gerrit commit 2ab368828c5c64d3b85482fc9cb09dbfd183c43b Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri May 31 18:57:20 2013 -0700 peppy: Re-enable EC software sync The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. (Taken from I63ca00d6c94854f2b395eb736ce20792da5f8de2). Change-Id: I9c7d1d1f1aaf7de33d0cec5f6daf648576ba8900 Reviewed-on: https://gerrit.chromium.org/gerrit/57289 Reviewed-by: Dave Parker <dparker(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/peppy/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index b7745e1..5eb8b95 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_SOFTWARE_SYNC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME

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New patch to review for coreboot: 18b92fd peppy: Update GPIO table + USB port map.
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4211 -gerrit commit 18b92fd657547bf4c1d5fbac9dbc1820251fce77 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue May 28 17:46:49 2013 -0700 peppy: Update GPIO table + USB port map. - Update GPIO table to match board. - Update USB port map. - Remove iSSD power sequencing code. Change-Id: Iaa8e5921ed9db6bcfd18b5a888c7f80b2c93a710 Reviewed-on: https://gerrit.chromium.org/gerrit/56869 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/peppy/gpio.h | 16 ++++++------ src/mainboard/google/peppy/romstage.c | 46 ++++------------------------------- 2 files changed, 13 insertions(+), 49 deletions(-) diff --git a/src/mainboard/google/peppy/gpio.h b/src/mainboard/google/peppy/gpio.h index 6dfb98f..7c023b5 100644 --- a/src/mainboard/google/peppy/gpio.h +++ b/src/mainboard/google/peppy/gpio.h @@ -39,8 +39,8 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ - LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ LP_GPIO_UNUSED, /* 19: UNUSED */ LP_GPIO_UNUSED, /* 20: UNUSED */ @@ -56,7 +56,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_UNUSED, /* 33: UNUSED */ LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ @@ -67,12 +67,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 41: UNUSED */ LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ LP_GPIO_UNUSED, /* 43: UNUSED */ - LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ + LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ LP_GPIO_INPUT, /* 47: RAM_ID2 */ LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ + LP_GPIO_UNUSED, /* 49: UNUSED */ LP_GPIO_UNUSED, /* 50: UNUSED */ LP_GPIO_IRQ_EDGE, /* 51: ALS_INT_L */ LP_GPIO_IRQ_EDGE, /* 52: SIM_DET */ @@ -84,12 +84,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ - LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ LP_GPIO_UNUSED, /* 64: UNUSED */ LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ LP_GPIO_UNUSED, /* 67: UNUSED */ LP_GPIO_UNUSED, /* 68: UNUSED */ LP_GPIO_UNUSED, /* 69: UNUSED */ diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 8679adb..834479d 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -98,39 +98,6 @@ static void copy_spd(struct pei_data *peid) sizeof(peid->spd_data[0])); } -/* - * Power Sequencing for SanDisk i100/i110 SSD - * - * Must be sequenced in this order with specified timing. - * - * 1. VCC_IO : 30us - 100ms - * 2. VCC_FLASH : 70us - 10ms - * 3. VCCQ : 70us - 10ms - * 4. VDDC : 30us - 100ms - * - * There is no feedback to know if the voltage has stabilized - * so this implementation will use the max ramp times. That - * means it adds significantly to the boot time. - */ -static void issd_power_sequence(void) -{ - struct gpio_seq { - int gpio; - int wait_ms; - } issd_gpio_seq[] = { - { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ - { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ - { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ - { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ - }; - int step; - - for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) { - set_gpio(issd_gpio_seq[step].gpio, 1); - udelay(issd_gpio_seq[step].wait_ms * 1000); - } -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { @@ -161,18 +128,18 @@ void mainboard_romstage_entry(unsigned long bist) usb2_ports: { /* Length, Enable, OCn# */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, 0 }, /* P1: Port A */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ + { 0x0040, 1, 2 }, /* P4: USB 2.0 Port */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ }, usb3_ports: { /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN6 */ + { 1, 0 }, /* P1; Port A, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P2; */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, @@ -190,7 +157,4 @@ void mainboard_romstage_entry(unsigned long bist) /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); - - /* Power sequence the iSSD module */ - issd_power_sequence(); }

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New patch to review for coreboot: a14b459 lynxpoint: Do not clear ACPI NVS region on resume
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4210 -gerrit commit a14b4597f1c502a462afb379c2ecc53bb5157c3a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 07:49:55 2013 -0700 lynxpoint: Do not clear ACPI NVS region on resume There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff50476..cc95454 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -701,7 +701,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs) + if (acpi_slp_type != 3 && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); }

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New patch to review for coreboot: 76876c3 lynxpoint: Add an inverted input GPIO type
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4209 -gerrit commit 76876c3b718312c95133598c15d1b9b8aa1bd70c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 07:48:47 2013 -0700 lynxpoint: Add an inverted input GPIO type The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. suspend/resume on slippy with trackpad wake: 8 | 2013-05-29 07:43:14 | ACPI Enter | S3 9 | 2013-05-29 07:43:18 | ACPI Wake | S3 10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12 and with power button wake: 11 | 2013-05-29 07:43:35 | ACPI Enter | S3 12 | 2013-05-29 07:43:40 | EC Event | Power Button 13 | 2013-05-29 07:43:40 | ACPI Wake | S3 14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0 Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56940 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/gpio.h | 4 ++-- src/mainboard/google/slippy/gpio.h | 4 ++-- src/southbridge/intel/lynxpoint/lp_gpio.h | 4 ++++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/falco/gpio.h b/src/mainboard/google/falco/gpio.h index 037ddcb..3af0d59 100644 --- a/src/mainboard/google/falco/gpio.h +++ b/src/mainboard/google/falco/gpio.h @@ -35,7 +35,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 9: RAM_ID1 */ LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_INPUT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ @@ -48,7 +48,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 22: UNUSED */ LP_GPIO_UNUSED, /* 23: UNUSED */ LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_INPUT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ LP_GPIO_UNUSED, /* 26: UNUSED */ LP_GPIO_UNUSED, /* 27: UNUSED */ LP_GPIO_UNUSED, /* 28: UNUSED */ diff --git a/src/mainboard/google/slippy/gpio.h b/src/mainboard/google/slippy/gpio.h index 4b557ce..2d47ea7 100644 --- a/src/mainboard/google/slippy/gpio.h +++ b/src/mainboard/google/slippy/gpio.h @@ -35,7 +35,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 9: RAM_ID1 */ LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_INPUT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ @@ -48,7 +48,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 22: UNUSED */ LP_GPIO_UNUSED, /* 23: UNUSED */ LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_INPUT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ LP_GPIO_UNUSED, /* 26: UNUSED */ LP_GPIO_UNUSED, /* 27: UNUSED */ LP_GPIO_UNUSED, /* 28: UNUSED */ diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index f1b2717..38da9e2 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -123,6 +123,10 @@ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ .owner = GPIO_OWNER_GPIO } +#define LP_GPIO_INPUT_INVERT \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ + .owner = GPIO_OWNER_GPIO } + #define LP_GPIO_IRQ_EDGE \ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ .owner = GPIO_OWNER_GPIO, \

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New patch to review for coreboot: b57caf1 slippy/falco: Re-enable EC software sync
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4208 -gerrit commit b57caf1ab1fa1ee0f8d0abb88adc350e37a20a8b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 11:35:43 2013 -0700 slippy/falco: Re-enable EC software sync The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. Google Chrome EC MKBP driver ready, id 'slippy_no_version' Clearing the recovery request. EC hash:7fea29992ef72e3e64d8ffe522aa1dfa68dcb44a2da96a4c19530ea1a0bd22c4 EC-RW hash address, size are 0xffa1cfe8, 32. Hash = 727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde Expected hash:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde EC-RW firmware address, size are 0xffad000c, 57180. VbEcSoftwareSync() - expected len = 57180 Computed hash of expected image:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde VbEcSoftwareSync() updating EC-RW... VbEcSoftwareSync() jumping to EC-RW VbEcSoftwareSync() in RW; done Change-Id: I63ca00d6c94854f2b395eb736ce20792da5f8de2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56821 --- src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 068e7f1..3a08086 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_SOFTWARE_SYNC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index a2ef673..a53ac00 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_SOFTWARE_SYNC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME

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New patch to review for coreboot: 50a18da x86: fix compile error for !CONFIG_MULTIBOOT
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4207 -gerrit commit 50a18dac8bca4325f9af7069fdc55331c145b2ae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 16:15:01 2013 -0500 x86: fix compile error for !CONFIG_MULTIBOOT Some code was previously removed regarding elf notes. However, that code left a dangling comma under !CONFIG_MULTIBOOT configs for inline assembly constraints. Instead, place the comma within the #ifdef stanza. Change-Id: I805453ef57d34fbfb904b4d145d8874921d8d660 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56844 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: David James <davidjames(a)chromium.org> --- src/arch/x86/boot/boot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 7fc433d..1b28a4c 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -20,9 +20,9 @@ void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) " cld \n\t" :: - "r" (entry), + "r" (entry) #if CONFIG_MULTIBOOT - "b"(mbi), "a" (MB_MAGIC2) + , "b"(mbi), "a" (MB_MAGIC2) #endif ); }

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coreboot-gerrit November 2013