coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: fa93c5d libpayload: usb mass storage card hot plug
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4226 -gerrit commit fa93c5da6a21674c02d8bac52c9fd3d6f4ac5923 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 7 12:31:21 2013 -0500 libpayload: usb mass storage card hot plug Mass storage devices such as card readers show up as as USB devices. However the media not be inserted. In those situations the previous code would just fake a disk and call usbcreate_disk. This is inappropriate because it forms a 1:1 mapping of USB device to disk leading to the inability to remove the disk and/or handle "hot plug" card insertion and removals. To alleviate this issue introduce the notion of ready to the usbmsc structure. It tracks detached, not ready, and ready states. The polling routine is then used to track not ready to ready transitions thereby creating and removing disks appropriately. This handles the case of inserting and removing a card that shows up as a new disk. Booted recovery mode. Able to observe inerstion and removal of sdcard. Also able to insert valid USB flash drive to boot as well. Change-Id: I3eefbe537ec1b9c975744b8984b06c17ae236f40 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57948 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/drivers/usb/usbmsc.c | 202 +++++++++++++++++++++++-------- payloads/libpayload/include/usb/usbmsc.h | 8 ++ 2 files changed, 157 insertions(+), 53 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index ffb1c93..f1de483 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -67,21 +67,60 @@ static const char *msc_protocol_strings[0x51] = { "Bulk-Only Transport" }; +static inline void +usb_msc_mark_ready (usbdev_t *dev) +{ + MSC_INST (dev)->ready = USB_MSC_READY; +} + +static inline void +usb_msc_mark_not_ready (usbdev_t *dev) +{ + MSC_INST (dev)->ready = USB_MSC_NOT_READY; +} + +static inline void +usb_msc_mark_detached (usbdev_t *dev) +{ + MSC_INST (dev)->ready = USB_MSC_DETACHED; +} + +static inline int +usb_msc_is_detached (usbdev_t *dev) +{ + return MSC_INST (dev)->ready == USB_MSC_DETACHED; +} + +static inline int +usb_msc_is_ready (usbdev_t *dev) +{ + return MSC_INST (dev)->ready == USB_MSC_READY; +} static void -usb_msc_destroy (usbdev_t *dev) +usb_msc_create_disk (usbdev_t *dev) { - if (dev->data) { - if (MSC_INST (dev)->usbdisk_created && usbdisk_remove) - usbdisk_remove (dev); - free (dev->data); + if (usbdisk_create) { + usbdisk_create (dev); + MSC_INST (dev)->usbdisk_created = 1; } - dev->data = 0; } static void -usb_msc_poll (usbdev_t *dev) +usb_msc_remove_disk (usbdev_t *dev) { + if (MSC_INST (dev)->usbdisk_created && usbdisk_remove) + usbdisk_remove (dev); +} + +static void +usb_msc_destroy (usbdev_t *dev) +{ + if (dev->data) { + usb_msc_remove_disk (dev); + free (dev->data); + } + dev->data = 0; } const int DEV_RESET = 0xff; @@ -125,6 +164,8 @@ static int request_sense (usbdev_t *dev); static int request_sense_no_media (usbdev_t *dev); +static void +usb_msc_poll (usbdev_t *dev); static int reset_transport (usbdev_t *dev) @@ -357,7 +398,7 @@ request_sense (usbdev_t *dev) sizeof (cb), buf, 19, 1); } -static int request_sense_no_media(usbdev_t *dev) +static int request_sense_no_media (usbdev_t *dev) { u8 buf[19]; int ret; @@ -379,10 +420,11 @@ static int request_sense_no_media(usbdev_t *dev) if (buf[12] != 0x3a) return MSC_COMMAND_FAIL; - /* No media is present. Return MSC_COMMAND_DETACHED so as not to use - * this device any longer. */ - usb_debug("Empty media found.\n"); - return MSC_COMMAND_DETACHED; + /* No media is present. Return MSC_COMMAND_OK while marking the disk + * not ready. */ + usb_debug ("Empty media found.\n"); + usb_msc_mark_not_ready (dev); + return MSC_COMMAND_OK; } static int @@ -446,10 +488,74 @@ read_capacity (usbdev_t *dev) return MSC_COMMAND_OK; } +static void +usb_msc_test_unit_ready (usbdev_t *dev) +{ + int i; + /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ + const int timeout = 30 * 10; + + usb_debug (" Waiting for device to become ready..."); + + /* Initially mark the device ready. */ + usb_msc_mark_ready (dev); + + for (i = 0; i < timeout; i++) { + switch (test_unit_ready (dev)) { + case MSC_COMMAND_OK: + break; + case MSC_COMMAND_FAIL: + mdelay (100); + if (!(timeout % 10)) + usb_debug ("."); + continue; + default: + usb_debug ("detached. Device not ready.\n"); + usb_msc_mark_detached (dev); + return; + } + break; + } + if (i >= timeout) { + usb_debug ("timeout. Device not ready.\n"); + usb_msc_mark_not_ready (dev); + } + + /* Don't bother spinning up the stroage device if the device is not + * ready. This can happen when empty card readers are present. + * Polling will pick it back up if readiness changes. */ + if (!usb_msc_is_ready (dev)) + return; + + usb_debug ("ok.\n"); + + usb_debug (" spin up"); + for (i = 0; i < 30; i++) { + usb_debug ("."); + switch (spin_up (dev)) { + case MSC_COMMAND_OK: + usb_debug (" OK."); + break; + case MSC_COMMAND_FAIL: + mdelay (100); + continue; + default: + /* Device is no longer ready. */ + usb_msc_mark_detached (dev); + return; + } + break; + } + usb_debug ("\n"); + + if (read_capacity (dev) != MSC_COMMAND_OK) + usb_msc_mark_not_ready (dev); +} + void usb_msc_init (usbdev_t *dev) { - int i, timeout; + int i; /* init .data before setting .destroy */ dev->data = NULL; @@ -489,6 +595,7 @@ usb_msc_init (usbdev_t *dev) MSC_INST (dev)->bulk_in = 0; MSC_INST (dev)->bulk_out = 0; MSC_INST (dev)->usbdisk_created = 0; + usb_msc_mark_ready (dev); for (i = 1; i <= dev->num_endp; i++) { if (dev->endpoints[i].endpoint == 0) @@ -517,47 +624,36 @@ usb_msc_init (usbdev_t *dev) usb_debug (" has %d luns\n", get_max_luns (dev) + 1); - usb_debug (" Waiting for device to become ready..."); - timeout = 30 * 10; /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ - while (timeout--) { - switch (test_unit_ready (dev)) { - case MSC_COMMAND_OK: - break; - case MSC_COMMAND_FAIL: - mdelay (100); - if (!(timeout % 10)) - usb_debug ("."); - continue; - default: /* if it's worse return */ - return; - } - break; - } - if (timeout < 0) { - usb_debug ("timeout. Device not ready. Still trying...\n"); - } else { - usb_debug ("ok.\n"); - } + /* Test if unit is ready. */ + usb_msc_test_unit_ready (dev); - usb_debug (" spin up"); - for (i = 0; i < 30; i++) { - usb_debug ("."); - switch (spin_up (dev)) { - case MSC_COMMAND_OK: - usb_debug (" OK."); - break; - case MSC_COMMAND_FAIL: - mdelay (100); - continue; - default: /* if it's worse return */ - return; - } - break; - } - usb_debug ("\n"); + /* Nothing to do if device is not ready. */ + if (!usb_msc_is_ready (dev)) + return; - if ((read_capacity (dev) == MSC_COMMAND_OK) && usbdisk_create) { - usbdisk_create (dev); - MSC_INST (dev)->usbdisk_created = 1; + /* Create the disk. */ + usb_msc_create_disk (dev); +} + +static void +usb_msc_poll (usbdev_t *dev) +{ + int prev_ready; + + /* Nothing to do if device is detached. */ + if (usb_msc_is_detached (dev)) + return; + + /* Handle ready transitions by keeping track of previous state . */ + prev_ready = usb_msc_is_ready (dev); + + usb_msc_test_unit_ready (dev); + + if (!prev_ready && usb_msc_is_ready (dev)) { + usb_debug ("usb msc: not ready -> ready\n"); + usb_msc_create_disk (dev); + } else if (prev_ready && !usb_msc_is_ready (dev)) { + usb_debug ("usb msc: ready -> not ready\n"); + usb_msc_remove_disk (dev); } } diff --git a/payloads/libpayload/include/usb/usbmsc.h b/payloads/libpayload/include/usb/usbmsc.h index 5c3dadc..8930156 100644 --- a/payloads/libpayload/include/usb/usbmsc.h +++ b/payloads/libpayload/include/usb/usbmsc.h @@ -36,9 +36,17 @@ typedef struct { endpoint_t *bulk_in; endpoint_t *bulk_out; int usbdisk_created; + int ready; void *data; /* For use by consumers of libpayload. */ } usbmsc_inst_t; +/* Possible values for ready field. */ +enum { + USB_MSC_DETACHED = -1, /* Disk detached or out to lunch. */ + USB_MSC_NOT_READY = 0, /* Disk not ready yet -- empty card reader */ + USB_MSC_READY = 1, /* Disk ready to communicate. */ +}; + #define MSC_INST(dev) ((usbmsc_inst_t*)(dev)->data) typedef enum { cbw_direction_data_in = 0x80, cbw_direction_data_out = 0

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New patch to review for coreboot: ab22ac4 libpayload: usb mass storage detect empty media
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4225 -gerrit commit ab22ac4852a408e81654d6f90df354899f78f53a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jun 6 16:14:21 2013 -0500 libpayload: usb mass storage detect empty media There is currently a hard-coded 30 sec delay in the mass storage driver while waiting for each device to become ready. However, mass storage card readers that are empty return an error code on the TEST UNIT READY command. A REQUEST SENSE command then needs to be issued and interrogate the data to determine if no media is present. If no media determination is found to be true the USB device is no longer considered a candidate to be a disk. This code does lead to the fact that the media card reader needs to be populated at enumeration time. I suspect this is not an issue as it appears the storage stack in libpayload can't handle removable media coming online later. Booted recovery and dev modes. Noted that removable mass storage devices with no media were ignored without any boot delay. Change-Id: Ida7a45614d97c6e6fbfc9bb099765aad4df550fd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57828 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/drivers/usb/usbmsc.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index ad7e82f..ffb1c93 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -123,6 +123,8 @@ enum { static int request_sense (usbdev_t *dev); +static int +request_sense_no_media (usbdev_t *dev); static int reset_transport (usbdev_t *dev) @@ -256,6 +258,11 @@ execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen, if (cb[0] == 0x03) /* requesting sense failed, that's bad */ return MSC_COMMAND_FAIL; + else if (cb[0] == 0) + /* If command was TEST UNIT READY determine if the + * device is of removable type indicating no media + * found. */ + return request_sense_no_media (dev); /* error "check condition" or reserved error */ ret = request_sense (dev); /* return fail or the status of request_sense if it's worse */ @@ -350,6 +357,34 @@ request_sense (usbdev_t *dev) sizeof (cb), buf, 19, 1); } +static int request_sense_no_media(usbdev_t *dev) +{ + u8 buf[19]; + int ret; + cmdblock6_t cb; + memset (&cb, 0, sizeof (cb)); + cb.command = 0x3; + + ret = execute_command (dev, cbw_direction_data_in, (u8 *) &cb, + sizeof (cb), buf, 19, 1); + + if (ret) + return ret; + + /* Check if sense key is set to NOT READY. */ + if ((buf[2] & 0xf) != 2) + return MSC_COMMAND_FAIL; + + /* Check if additional sense code is 0x3a. */ + if (buf[12] != 0x3a) + return MSC_COMMAND_FAIL; + + /* No media is present. Return MSC_COMMAND_DETACHED so as not to use + * this device any longer. */ + usb_debug("Empty media found.\n"); + return MSC_COMMAND_DETACHED; +} + static int test_unit_ready (usbdev_t *dev) {

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New patch to review for coreboot: b6b81b9 slippy: update verbs for ALC283
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4224 -gerrit commit b6b81b9393f2da57eee1c996fa8d29bdab0b05fc Author: Dylan Reid <dgreid(a)chromium.org> Date: Tue Jun 4 20:01:32 2013 -0700 slippy: update verbs for ALC283 Set verbs to reflect the layout used for the ALC283 in slippy. install on slippy and check that headphone switch works as does external mic. Change-Id: I2d6bcda9cf8bbf49cbb6d2dbbe7f1a5adf315d8a Signed-off-by: Dylan Reid <dgreid(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57560 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/slippy/hda_verb.h | 120 ++++++++++++++++----------------- 1 file changed, 58 insertions(+), 62 deletions(-) diff --git a/src/mainboard/google/slippy/hda_verb.h b/src/mainboard/google/slippy/hda_verb.h index 56275a2..3866a51 100644 --- a/src/mainboard/google/slippy/hda_verb.h +++ b/src/mainboard/google/slippy/hda_verb.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,81 +19,77 @@ static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 - 0x10134210, // Subsystem ID - 0x00000007, // Number of jacks + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000b, // Number of jacks (NID entries) - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */ - 0x00172010, - 0x00172142, - 0x00172213, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, 0x00172310, /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */ - 0x00571cf0, - 0x00571d20, - 0x00571e21, - 0x00571f02, + /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ + 0x00571c10, + 0x00571d10, + 0x00571ea6, + 0x00571fb7, - /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */ - 0x00671c10, - 0x00671d00, - 0x00671e17, - 0x00671f90, + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471c10, // group 1, front left/right + 0x01471d01, // no connector, no jack detect + 0x01471e17, // speaker out, analog + 0x01471f90, // fixed function, internal - /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */ - 0x00771cf0, - 0x00771d20, - 0x00771ea1, - 0x00771f02, + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, - /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */ - 0x00871c37, - 0x00871d00, - 0x00871ea7, - 0x00871f77, + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01971c11, // group 1, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f03, // connector, left panel - /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */ - 0x00971c3e, - 0x00971d00, - 0x00971ea6, - 0x00971f77, + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, - /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */ - 0x00a71cf0, - 0x00a71d10, - 0x00a71e45, - 0x00a71f43, + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, - /* coreboot specific header */ - 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ - 0x00172001, - 0x00172101, - 0x00172286, - 0x00172380, + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ - 0x30571c10, - 0x30571d00, - 0x30571e56, - 0x30571f18, + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ - 0x30671c20, - 0x30671d00, - 0x30671e56, - 0x30671f18, + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f03, // connector, left panel - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - 0x30771c30, - 0x30771d00, - 0x30771e56, - 0x30771f18 };

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New patch to review for coreboot: 5f0f65e vboot: use out_flags to indicate recovery mode
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4223 -gerrit commit 5f0f65e1ba5dd90377abb131a938abe39a7cabfe Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:14:42 2013 -0700 vboot: use out_flags to indicate recovery mode In order to make the proper decision on loading the option rom or not the recovery mode setting needs to be known. Normally this is detected by asking the EC, but if recovery is requested with crossystem then the EC does not know about it. Instead we need to check the output flags from VbInit(). Change-Id: I09358e6fd979b4af6b37a13115ac34db3d98b09d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57474 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index c2cc0e1..828cfd2 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -41,8 +41,21 @@ static int vboot_enable_developer(void) return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); } + +static int vboot_enable_recovery(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) + return 0; + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); +} #else static inline int vboot_enable_developer(void) { return 0; } +static inline int vboot_enable_recovery(void) { return 0; } #endif int developer_mode_enabled(void) @@ -52,11 +65,20 @@ int developer_mode_enabled(void) int recovery_mode_enabled(void) { - /* TODO(reinauer): get information from VbInit. - * the recovery mode switch is not the only reason to go - * to recovery mode. + /* + * This is called in multiple places and has to detect + * recovery mode triggered from the EC and via shared + * recovery reason set with crossystem. + * + * If shared recovery reason is set: + * - before VbInit then get_recovery_mode_from_vbnv() is true + * - after VbInit then vboot_enable_recovery() is true + * + * Otherwise the mainboard handler for get_recovery_mode_switch() + * will detect recovery mode initiated by the EC. */ - return get_recovery_mode_switch() || get_recovery_mode_from_vbnv(); + return get_recovery_mode_switch() || get_recovery_mode_from_vbnv() || + vboot_enable_recovery(); } #if CONFIG_VBOOT_VERIFY_FIRMWARE

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New patch to review for coreboot: 2c0600f vboot: Do not pass OPROM_MATTERS flag to VbInit
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4222 -gerrit commit 2c0600f18eca4db689da9540924f05af796582f1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:08:54 2013 -0700 vboot: Do not pass OPROM_MATTERS flag to VbInit Since we are using VBNV to determine if developer mode is active we do not need the messy OPROM hook magic any longer. Change-Id: I1b9effef3ef2aa84e916060d8e61ee42515a2b7c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57473 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/gnvs.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index ba1588d..5ee3665 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -49,15 +49,9 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - if (vboot_handoff != NULL) { - vboot_handoff->init_params.flags |= VB_INIT_FLAG_OPROM_MATTERS; - if (oprom_is_loaded) - vboot_handoff->init_params.flags |= - VB_INIT_FLAG_OPROM_LOADED; - + if (vboot_handoff != NULL) memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], ARRAY_SIZE(chromeos->vdat)); - } #endif #if CONFIG_ELOG

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New patch to review for coreboot: 3ec1675 slippy/falco/peppy: Fix Chrome OS GPIO export in ACPI
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4221 -gerrit commit 3ec1675208c1edd23d0adefc889155f61990bf36 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:06:25 2013 -0700 slippy/falco/peppy: Fix Chrome OS GPIO export in ACPI The OIPG package needs to have >1 member to make the chromeos_acpi kernel driver do the right automagic sysfs topology creation. Additionally an "unimplemented" GPIO should be reported as 0xFF because 0 is a valid GPIO number. verify crossystem on slippy $ sudo crossystem | grep -e recoverysw_cur -e wpsw_cur recoverysw_cur = (error) wpsw_cur = 1 Change-Id: I06dff09152bde30a3ffe58b1defe9d299155472c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57471 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/acpi/chromeos.asl | 3 +-- src/mainboard/google/peppy/acpi/chromeos.asl | 3 +-- src/mainboard/google/slippy/acpi/chromeos.asl | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/falco/acpi/chromeos.asl b/src/mainboard/google/falco/acpi/chromeos.asl index e427821..4e9035b 100644 --- a/src/mainboard/google/falco/acpi/chromeos.asl +++ b/src/mainboard/google/falco/acpi/chromeos.asl @@ -18,7 +18,6 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect }) diff --git a/src/mainboard/google/peppy/acpi/chromeos.asl b/src/mainboard/google/peppy/acpi/chromeos.asl index e427821..4e9035b 100644 --- a/src/mainboard/google/peppy/acpi/chromeos.asl +++ b/src/mainboard/google/peppy/acpi/chromeos.asl @@ -18,7 +18,6 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect }) diff --git a/src/mainboard/google/slippy/acpi/chromeos.asl b/src/mainboard/google/slippy/acpi/chromeos.asl index e427821..4e9035b 100644 --- a/src/mainboard/google/slippy/acpi/chromeos.asl +++ b/src/mainboard/google/slippy/acpi/chromeos.asl @@ -18,7 +18,6 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect })

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New patch to review for coreboot: 109d6e5 haswell boards: Enable VIRTUAL_DEV_SWITCH
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4220 -gerrit commit 109d6e52d063336ada7a64f8756d9c63ff617bb7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 3 10:45:08 2013 -0700 haswell boards: Enable VIRTUAL_DEV_SWITCH This config option was not enabled which was preventing the user from enabling developer mode from recovery mode. With this enabled we can disable the "dev mode by default" behavior and let people enable it by entering recovery mode. This will make the firmware behave like a typical chromeos device. Peppy is left in "default dev mode" until after bringup. 1) boot slippy in normal mode by default 2) enter recovery mode with servo button 3) Ctrl+D on USB keyboard to enter developer mode 4) boot slippy in developer mode Change-Id: I414c0d10dd0489e3c89798f75a2872a43297c8d8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57350 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/falco/chromeos.c | 2 +- src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/google/slippy/chromeos.c | 2 +- 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 3a08086..3c0c576 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 1b70fde..51d625b 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* The dev-switch is virtual */ int get_developer_mode_switch(void) { - return 1; + return 0; } /* There are actually two recovery switches. One is the magic keyboard chord, diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 5eb8b95..74a04fb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index a53ac00..aaea947 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 1b70fde..51d625b 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* The dev-switch is virtual */ int get_developer_mode_switch(void) { - return 1; + return 0; } /* There are actually two recovery switches. One is the magic keyboard chord,

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New patch to review for coreboot: f4626ee haswell: Update pei_data to match ref code
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4219 -gerrit commit f4626ee382c4b3804bcbdbea5486bafe4beae7d7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 3 10:41:12 2013 -0700 haswell: Update pei_data to match ref code - Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/romstage.c | 28 ++++++++++++------ src/mainboard/google/peppy/romstage.c | 26 +++++++++++------ src/mainboard/google/slippy/romstage.c | 26 +++++++++++------ src/mainboard/intel/baskingridge/romstage.c | 44 +++++++++++++++++++---------- src/mainboard/intel/wtm2/romstage.c | 24 ++++++++++------ src/northbridge/intel/haswell/pei_data.h | 19 ++++++++++++- 6 files changed, 116 insertions(+), 51 deletions(-) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index ef6a849..888394a 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -129,17 +129,27 @@ void mainboard_romstage_entry(unsigned long bist) // 3 = disable dimm 0+1 on channel dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, + // Enable 2x refresh mode + ddr_refresh_2x: 1, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Port A, CN8 */ - { 0x0040, 1, 0 }, /* P1: Port B, CN9 */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 1, 3 }, /* P7: USB2 Port */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN8 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Port B, CN9 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P7: USB2 Port */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 834479d..0c4adc4 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -126,15 +126,23 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: USB 2.0 Port */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ + /* Length, Enable, OCn#, Location */ + { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, /* P4: Port B, CN6 */ + USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 8679adb..b7ae209 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -159,15 +159,23 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ + /* Length, Enable, OCn#, Location */ + { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, /* P4: Port B, CN6 */ + USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 8b18e6d..2be4b91 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -94,21 +94,35 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 0, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */ - { 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */ - { 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */ - { 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */ - { 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */ - { 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */ - { 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */ - { 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */ - { 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */ - { 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */ - { 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */ - { 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ + USB_PORT_DOCK }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index f38389c..cd5fad7 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -100,14 +100,22 @@ void mainboard_romstage_entry(unsigned long bist) max_ddr3_freq: 1600, usb2_ports: { /* Length, Enable, OCn# */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */ - { 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */ + { 0x40, 1, USB_OC_PIN_SKIP, /* P0: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P1: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P2: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P3: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P4: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P5: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P6: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P7: */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 7311829..b7dc8cf 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,16 +31,31 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 12 +#define PEI_VERSION 13 #define MAX_USB2_PORTS 16 #define MAX_USB3_PORTS 16 #define USB_OC_PIN_SKIP 8 +enum usb2_port_location { + USB_PORT_BACK_PANEL = 0, + USB_PORT_FRONT_PANEL, + USB_PORT_DOCK, + USB_PORT_MINI_PCIE, + USB_PORT_FLEX, + USB_PORT_INTERNAL, + USB_PORT_SKIP +}; + +/* Usb Port Length: + * [16:4] = length in inches in octal format + * [3:0] = decimal point + */ struct usb2_port_setting { uint16_t length; uint8_t enable; uint8_t over_current_pin; + uint8_t location; } __attribute__((packed)); struct usb3_port_setting { @@ -75,6 +90,8 @@ struct pei_data // 3 = disable dimm 0+1 on channel int dimm_channel0_disabled; int dimm_channel1_disabled; + /* Enable 2x Refresh Mode */ + int ddr_refresh_2x; /* Data read from flash and passed into MRC */ unsigned char *mrc_input; unsigned int mrc_input_len;

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New patch to review for coreboot: 760fe4a vboot: use out_flags to indicate dev mode
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4218 -gerrit commit 760fe4ac5291a9fd0d08ea202c12796971a37cf9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 4 08:57:54 2013 -0500 vboot: use out_flags to indicate dev mode In order to make the proper decision on loading the option rom or not the developer mode setting needs to be known. Under early firmware selection it is possible to know the state of developer mode by a flag in out flags. Use this flag when early firmware selection is being employed to determine if developer mode is enabled or not. Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57380 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 6f1fe72..c2cc0e1 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -26,9 +26,28 @@ #include <cbmem.h> #include <console/console.h> +#if CONFIG_VBOOT_VERIFY_FIRMWARE +static int vboot_enable_developer(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) { + printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", + __func__); + return 0; + } + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); +} +#else +static inline int vboot_enable_developer(void) { return 0; } +#endif + int developer_mode_enabled(void) { - return get_developer_mode_switch(); + return get_developer_mode_switch() || vboot_enable_developer(); } int recovery_mode_enabled(void)

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New patch to review for coreboot: 1105bbd lynxpoint: Enable USB clock gating, late setup, and sleep prep
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4217 -gerrit commit 1105bbdd7f4fec811ed2315e69a64842f1c2059c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 15:27:55 2013 -0700 lynxpoint: Enable USB clock gating, late setup, and sleep prep Both EHCI and XHCI controllers have additional setup steps that are not part of the PEI reference code so they need to be done later. Both controllers also have specific clock gating setup requirements that are now implemented. Additionally they both have specific requirements when entering sleep states. XHCI needs something in S3/S4/S5 and EHCI only has steps for S4/S5 entry. Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57033 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 1 + src/southbridge/intel/lynxpoint/pch.h | 7 ++ src/southbridge/intel/lynxpoint/smihandler.c | 98 +++++++++++++++ src/southbridge/intel/lynxpoint/usb_ehci.c | 31 +++-- src/southbridge/intel/lynxpoint/usb_xhci.c | 175 +++++++++++++++++++++++++++ 5 files changed, 303 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 370e017..4d96edf 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sata.c ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c ramstage-y += me_9.x.c ramstage-y += smbus.c ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index b01fdc0..6ee81d1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -224,6 +224,7 @@ void set_gpio(int gpio_num, int value); #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) +#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 @@ -335,6 +336,12 @@ void set_gpio(int gpio_num, int value); #define SATA_IOBP_SP0G3IR 0xea000151 #define SATA_IOBP_SP1G3IR 0xea000051 +/* USB Registers */ +#define EHCI_PWR_CNTL_STS 0x54 +#define EHCI_PWR_STS_MASK 0x3 +#define EHCI_PWR_STS_SET_D0 0x0 +#define EHCI_PWR_STS_SET_D3 0x3 + /* Serial IO IOBP Registers */ #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ #define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 203a1bb..add53ed 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -20,6 +20,7 @@ * MA 02110-1301 USA */ +#include <delay.h> #include <types.h> #include <arch/hlt.h> #include <arch/io.h> @@ -105,6 +106,98 @@ static void busmaster_disable_on_bus(int bus) } } +/* Handler for EHCI controller on entry to S3/S4/S5 */ +static void ehci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u32 reg32; + u32 bar0_base; + u16 pwr_state; + u16 pci_cmd; + + /* Check if the controller is disabled or not present */ + bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (bar0_base == 0 || bar0_base == 0xffffffff) + return; + pci_cmd = pci_read_config32(dev, PCI_COMMAND); + + switch (slp_typ) { + case SLP_TYP_S4: + case SLP_TYP_S5: + /* Check if controller is in D3 power state */ + pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); + if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { + /* Put in D0 */ + pwr_state &= ~EHCI_PWR_STS_MASK; + pwr_state |= EHCI_PWR_STS_SET_D0; + pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); + + /* Make sure memory bar is set */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); + + /* Make sure memory space is enabled */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } + + /* + * If Run/Stop (bit0) is clear in USB2.0_CMD: + * - Clear Async Schedule Enable (bit5) and + * - Clear Periodic Schedule Enable (bit4) and + * - Set Run/Stop (bit0) + */ + reg32 = read32(bar0_base + 0x20); + if (reg32 & (1 << 0)) { + reg32 &= ~((1 << 5) | (1 << 4)); + reg32 |= (1 << 0); + write32(bar0_base + 0x20, reg32); + } + + /* Check for Port Enabled in PORTSC */ + reg32 = read32(bar0_base + 0x64); + if (reg32 & (1 << 2)) { + /* Set suspend bit in PORTSC if not already set */ + if (!(reg32 & (1 << 7))) { + reg32 |= (1 << 7); + write32(bar0_base + 0x64, reg32); + } + + /* Delay 25ms !! */ + udelay(25 * 1000); + + /* Clear Run/Stop bit */ + reg32 = read32(bar0_base + 0x20); + reg32 &= (1 << 0); + write32(bar0_base + 0x20, reg32); + } + + pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS); + if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) { + /* Restore pci command reg */ + pci_write_config16(dev, PCI_COMMAND, pci_cmd); + + /* Enable D3 */ + pwr_state |= EHCI_PWR_STS_SET_D3; + pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state); + } + } +} + +/* Handler for XHCI controller on entry to S3/S4/S5 */ +static void xhci_sleep_prepare(device_t dev, u8 slp_typ) +{ + u16 reg16; + + switch (slp_typ) { + case SLP_TYP_S3: + case SLP_TYP_S4: + case SLP_TYP_S5: + /* Set D3Hot state and PME enable bit */ + reg16 = pci_read_config16(dev, 0x74); + reg16 |= (1 << 8) | (1 << 1) | (1 << 0); + pci_write_config16(dev, 0x74, reg16); + } +} + static void southbridge_smi_sleep(void) { u8 reg8; @@ -132,6 +225,11 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ-2); + /* USB sleep preparations */ + ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); + ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); + xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); + #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ if (slp_typ >= 5) diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index fd7c659..f06151b 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -26,20 +26,33 @@ #include <usbdebug.h> #include <arch/io.h> -static void usb_ehci_init(struct device *dev) +static void usb_ehci_clock_gating(struct device *dev) { u32 reg32; - /* Disable Wake on Disconnect in RMH */ - reg32 = RCBA32(0x35b0); - reg32 |= 0x22; - RCBA32(0x35b0) = reg32; + /* IOBP 0xE5004001[7:6] = 11b */ + pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); + + /* Dx:F0:DCh[5,2,1] = 111b + * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ + reg32 = pci_read_config32(dev, 0xdc); + reg32 |= (1 << 5) | (1 << 2) | (1 << 1); + pci_write_config32(dev, 0xdc, reg32); + + /* Dx:F0:78h[1:0] = 11b */ + reg32 = pci_read_config32(dev, 0x78); + reg32 |= (1 << 1) | (1 << 0); + pci_write_config32(dev, 0x78, reg32); +} +static void usb_ehci_init(struct device *dev) +{ printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + + usb_ehci_clock_gating(dev); + + /* Disable Wake on Disconnect in RMH */ + RCBA32_OR(0x35b0, 0x00000022); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c new file mode 100644 index 0000000..33f33f4 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "pch.h" + +static void usb_xhci_clock_gating(device_t dev) +{ + u32 reg32; + + /* IOBP 0xE5004001[7:6] = 11b */ + pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); + + reg32 = pci_read_config32(dev, 0x40); + reg32 &= ~(1 << 23); /* unsupported request */ + + if (pch_is_lp()) { + /* D20:F0:40h[18,17,8] = 111b */ + reg32 |= (1 << 18) | (1 << 17) | (1 << 8); + /* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */ + reg32 &= ~(1 << 19); + reg32 |= (1 << 21) | (1 << 20); + } else { + /* D20:F0:40h[21,20,18,17,8] = 11111b */ + reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); + } + + /* Avoid writing upper byte as it is write-once */ + pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff)); + pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); + + /* D20:F0:44h[9,7,3] = 111b */ + reg32 = pci_read_config32(dev, 0x44); + reg32 |= (1 << 9) | (1 << 7) | (1 << 3); + pci_write_config32(dev, 0x44, reg32); + + reg32 = pci_read_config32(dev, 0xa0); + if (pch_is_lp()) { + /* D20:F0:A0h[18] = 1 */ + reg32 |= (1 << 18); + } else { + /* D20:F0:A0h[6] = 1 */ + reg32 |= (1 << 6); + } + pci_write_config32(dev, 0xa0, reg32); + + /* D20:F0:A4h[13] = 0 */ + reg32 = pci_read_config32(dev, 0xa4); + reg32 &= ~(1 << 13); + pci_write_config32(dev, 0xa4, reg32); +} + +static void usb_xhci_init(device_t dev) +{ + struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + u32 reg32; + + if (!bar0 || bar0->base == 0 || bar0->base == 0xffffffff) + return; + + /* Enable clock gating first */ + usb_xhci_clock_gating(dev); + + /* D20:F0:74h[1:0] = 11b (set D3Hot state) */ + reg32 = pci_read_config16(dev, 0x74); + reg32 |= (1 << 1) | (1 << 0); + pci_write_config16(dev, 0x74, reg32); + + reg32 = read32(bar0->base + 0x8144); + if (pch_is_lp()) { + /* XHCIBAR + 8144h[8,7,6] = 111b */ + reg32 |= (1 << 8) | (1 << 7) | (1 << 6); + } else { + /* XHCIBAR + 8144h[8,7,6] = 100b */ + reg32 &= ~((1 << 7) | (1 << 6)); + reg32 |= (1 << 8); + } + write32(bar0->base + 0x8144, reg32); + + if (pch_is_lp()) { + /* XHCIBAR + 816Ch[19:0] = 000f0038h */ + reg32 = read32(bar0->base + 0x816c); + reg32 &= ~0x000fffff; + reg32 |= 0x000f0038; + write32(bar0->base + 0x816c, reg32); + + /* D20:F0:B0h[17,14,13] = 100b */ + reg32 = pci_read_config32(dev, 0xb0); + reg32 &= ~((1 << 14) | (1 << 13)); + reg32 |= (1 << 17); + pci_write_config32(dev, 0xb0, reg32); + + /* XHCIBAR + 818Ch[7:0] = FFh */ + reg32 = read32(bar0->base + 0x818c); + reg32 |= 0xff; + write32(bar0->base + 0x818c, reg32); + } + + reg32 = pci_read_config32(dev, 0x50); + if (pch_is_lp()) { + /* D20:F0:50h[28:0] = 0FCE2E5Fh */ + reg32 &= ~0x1fffffff; + reg32 |= 0x0fce2e5f; + } else { + /* D20:F0:50h[26:0] = 07886E9Fh */ + reg32 &= ~0x07ffffff; + reg32 |= 0x07886e9f; + } + pci_write_config32(dev, 0x50, reg32); + + /* D20:F0:44h[31] = 1 (Access Control Bit) */ + reg32 = pci_read_config32(dev, 0x40); + reg32 |= (1 << 31); + pci_write_config32(dev, 0x40, reg32); + + /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ + reg32 = pci_read_config32(dev, 0x40); + reg32 &= ~(1 << 23); /* unsupported request */ + reg32 |= (1 << 31); + pci_write_config32(dev, 0x40, reg32); +} + +static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_xhci_set_subsystem, +}; + +static struct device_operations usb_xhci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_xhci_init, + .ops_pci = &lops_pci, +}; + +static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ + 0x9c31, /* LynxPoint-LP */ + 0 }; + +static const struct pci_driver pch_usb_xhci __pci_driver = { + .ops = &usb_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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coreboot-gerrit November 2013