coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d464044 libpayload: provide missing cbfs symbol
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4199 -gerrit commit d46404497e38dfcd815571ef83add04d37e8586c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 09:25:32 2013 -0500 libpayload: provide missing cbfs symbol The generic cbfs code relies on the libpayload_init_default_cbfs_media symbol. However, none was provided for ARM. Provide an empty implementation that returns an error as there is no generic way to locate the default cbfs media. Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56805 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/arch/armv7/Makefile.inc | 1 + payloads/libpayload/arch/armv7/dummy_media.c | 42 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index 9c7fe83..e8ca109 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -34,3 +34,4 @@ libc-y += virtual.c libc-y += memcpy.S memset.S libc-y += exception_asm.S exception.c libc-y += cache.c +libc-y += dummy_media.c diff --git a/payloads/libpayload/arch/armv7/dummy_media.c b/payloads/libpayload/arch/armv7/dummy_media.c new file mode 100644 index 0000000..7926976 --- /dev/null +++ b/payloads/libpayload/arch/armv7/dummy_media.c @@ -0,0 +1,42 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define LIBPAYLOAD + +#include <cbfs.h> +#include <string.h> + +/* The generic cbfs code relies on the libpayload_init_default_cbfs_media + * symbol. Therefore, provide an implementation that just throws an error. */ + +int libpayload_init_default_cbfs_media(struct cbfs_media *media); + +int libpayload_init_default_cbfs_media(struct cbfs_media *media) +{ + return -1; +}

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Patch set updated for coreboot: 335736a cmos post: Guard with spinlock
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4227 -gerrit commit 335736a4b6fe354e52fdd40a6f2e18d572165ad8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 10 09:53:33 2013 -0700 cmos post: Guard with spinlock The CMOS post code storage mechanism does back-to-back CMOS reads and writes that may be interleaved during CPU bringup, leading to corruption of the log or of other parts of CMOS. Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58102 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/smp/spinlock.h | 14 ++++++++++++++ src/console/post.c | 15 ++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 5c1dd94..32be2f2 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,6 +1,8 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H +#ifndef __PRE_RAM__ + /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ @@ -61,4 +63,16 @@ static inline __attribute__((always_inline)) void cpu_relax(void) __asm__ __volatile__("rep;nop": : :"memory"); } +#else /* !__PRE_RAM__ */ + +#define DECLARE_SPIN_LOCK(x) +#define barrier() do {} while(0) +#define spin_is_locked(lock) 0 +#define spin_unlock_wait(lock) do {} while(0) +#define spin_lock(lock) do {} while(0) +#define spin_unlock(lock) do {} while(0) +#define cpu_relax() do {} while(0) + +#endif /* !__PRE_RAM__ */ + #endif /* ARCH_SMP_SPINLOCK_H */ diff --git a/src/console/post.c b/src/console/post.c index f55683e..11c631d 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -23,6 +23,7 @@ #include <console/console.h> #if CONFIG_CMOS_POST #include <pc80/mc146818rtc.h> +#include <smp/spinlock.h> #endif #include <elog.h> @@ -44,10 +45,14 @@ void __attribute__((weak)) mainboard_post(uint8_t value) #if CONFIG_CMOS_POST +DECLARE_SPIN_LOCK(cmos_post_lock) + #if !defined(__PRE_RAM__) void cmos_post_log(void) { - u8 code; + u8 code = 0; + + spin_lock(&cmos_post_lock); /* Get post code from other bank */ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { @@ -57,10 +62,10 @@ void cmos_post_log(void) case CMOS_POST_BANK_1_MAGIC: code = cmos_read(CMOS_POST_BANK_0_OFFSET); break; - default: - return; } + spin_unlock(&cmos_post_lock); + /* Check last post code in previous boot against normal list */ switch (code) { case POST_OS_BOOT: @@ -80,6 +85,8 @@ void cmos_post_log(void) static void cmos_post_code(u8 value) { + spin_lock(&cmos_post_lock); + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: cmos_write(value, CMOS_POST_BANK_0_OFFSET); @@ -88,6 +95,8 @@ static void cmos_post_code(u8 value) cmos_write(value, CMOS_POST_BANK_1_OFFSET); break; } + + spin_unlock(&cmos_post_lock); } #endif /* CONFIG_CMOS_POST */

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Patch set updated for coreboot: df133c9 libpayload: usb mass storage card hot plug
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4226 -gerrit commit df133c94aedc448c376ecff256efaf1befd6c78f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 7 12:31:21 2013 -0500 libpayload: usb mass storage card hot plug Mass storage devices such as card readers show up as as USB devices. However the media not be inserted. In those situations the previous code would just fake a disk and call usbcreate_disk. This is inappropriate because it forms a 1:1 mapping of USB device to disk leading to the inability to remove the disk and/or handle "hot plug" card insertion and removals. To alleviate this issue introduce the notion of ready to the usbmsc structure. It tracks detached, not ready, and ready states. The polling routine is then used to track not ready to ready transitions thereby creating and removing disks appropriately. This handles the case of inserting and removing a card that shows up as a new disk. Booted recovery mode. Able to observe inerstion and removal of sdcard. Also able to insert valid USB flash drive to boot as well. Change-Id: I3eefbe537ec1b9c975744b8984b06c17ae236f40 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57948 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/drivers/usb/usbmsc.c | 202 +++++++++++++++++++++++-------- payloads/libpayload/include/usb/usbmsc.h | 8 ++ 2 files changed, 157 insertions(+), 53 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index ffb1c93..f1de483 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -67,21 +67,60 @@ static const char *msc_protocol_strings[0x51] = { "Bulk-Only Transport" }; +static inline void +usb_msc_mark_ready (usbdev_t *dev) +{ + MSC_INST (dev)->ready = USB_MSC_READY; +} + +static inline void +usb_msc_mark_not_ready (usbdev_t *dev) +{ + MSC_INST (dev)->ready = USB_MSC_NOT_READY; +} + +static inline void +usb_msc_mark_detached (usbdev_t *dev) +{ + MSC_INST (dev)->ready = USB_MSC_DETACHED; +} + +static inline int +usb_msc_is_detached (usbdev_t *dev) +{ + return MSC_INST (dev)->ready == USB_MSC_DETACHED; +} + +static inline int +usb_msc_is_ready (usbdev_t *dev) +{ + return MSC_INST (dev)->ready == USB_MSC_READY; +} static void -usb_msc_destroy (usbdev_t *dev) +usb_msc_create_disk (usbdev_t *dev) { - if (dev->data) { - if (MSC_INST (dev)->usbdisk_created && usbdisk_remove) - usbdisk_remove (dev); - free (dev->data); + if (usbdisk_create) { + usbdisk_create (dev); + MSC_INST (dev)->usbdisk_created = 1; } - dev->data = 0; } static void -usb_msc_poll (usbdev_t *dev) +usb_msc_remove_disk (usbdev_t *dev) { + if (MSC_INST (dev)->usbdisk_created && usbdisk_remove) + usbdisk_remove (dev); +} + +static void +usb_msc_destroy (usbdev_t *dev) +{ + if (dev->data) { + usb_msc_remove_disk (dev); + free (dev->data); + } + dev->data = 0; } const int DEV_RESET = 0xff; @@ -125,6 +164,8 @@ static int request_sense (usbdev_t *dev); static int request_sense_no_media (usbdev_t *dev); +static void +usb_msc_poll (usbdev_t *dev); static int reset_transport (usbdev_t *dev) @@ -357,7 +398,7 @@ request_sense (usbdev_t *dev) sizeof (cb), buf, 19, 1); } -static int request_sense_no_media(usbdev_t *dev) +static int request_sense_no_media (usbdev_t *dev) { u8 buf[19]; int ret; @@ -379,10 +420,11 @@ static int request_sense_no_media(usbdev_t *dev) if (buf[12] != 0x3a) return MSC_COMMAND_FAIL; - /* No media is present. Return MSC_COMMAND_DETACHED so as not to use - * this device any longer. */ - usb_debug("Empty media found.\n"); - return MSC_COMMAND_DETACHED; + /* No media is present. Return MSC_COMMAND_OK while marking the disk + * not ready. */ + usb_debug ("Empty media found.\n"); + usb_msc_mark_not_ready (dev); + return MSC_COMMAND_OK; } static int @@ -446,10 +488,74 @@ read_capacity (usbdev_t *dev) return MSC_COMMAND_OK; } +static void +usb_msc_test_unit_ready (usbdev_t *dev) +{ + int i; + /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ + const int timeout = 30 * 10; + + usb_debug (" Waiting for device to become ready..."); + + /* Initially mark the device ready. */ + usb_msc_mark_ready (dev); + + for (i = 0; i < timeout; i++) { + switch (test_unit_ready (dev)) { + case MSC_COMMAND_OK: + break; + case MSC_COMMAND_FAIL: + mdelay (100); + if (!(timeout % 10)) + usb_debug ("."); + continue; + default: + usb_debug ("detached. Device not ready.\n"); + usb_msc_mark_detached (dev); + return; + } + break; + } + if (i >= timeout) { + usb_debug ("timeout. Device not ready.\n"); + usb_msc_mark_not_ready (dev); + } + + /* Don't bother spinning up the stroage device if the device is not + * ready. This can happen when empty card readers are present. + * Polling will pick it back up if readiness changes. */ + if (!usb_msc_is_ready (dev)) + return; + + usb_debug ("ok.\n"); + + usb_debug (" spin up"); + for (i = 0; i < 30; i++) { + usb_debug ("."); + switch (spin_up (dev)) { + case MSC_COMMAND_OK: + usb_debug (" OK."); + break; + case MSC_COMMAND_FAIL: + mdelay (100); + continue; + default: + /* Device is no longer ready. */ + usb_msc_mark_detached (dev); + return; + } + break; + } + usb_debug ("\n"); + + if (read_capacity (dev) != MSC_COMMAND_OK) + usb_msc_mark_not_ready (dev); +} + void usb_msc_init (usbdev_t *dev) { - int i, timeout; + int i; /* init .data before setting .destroy */ dev->data = NULL; @@ -489,6 +595,7 @@ usb_msc_init (usbdev_t *dev) MSC_INST (dev)->bulk_in = 0; MSC_INST (dev)->bulk_out = 0; MSC_INST (dev)->usbdisk_created = 0; + usb_msc_mark_ready (dev); for (i = 1; i <= dev->num_endp; i++) { if (dev->endpoints[i].endpoint == 0) @@ -517,47 +624,36 @@ usb_msc_init (usbdev_t *dev) usb_debug (" has %d luns\n", get_max_luns (dev) + 1); - usb_debug (" Waiting for device to become ready..."); - timeout = 30 * 10; /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ - while (timeout--) { - switch (test_unit_ready (dev)) { - case MSC_COMMAND_OK: - break; - case MSC_COMMAND_FAIL: - mdelay (100); - if (!(timeout % 10)) - usb_debug ("."); - continue; - default: /* if it's worse return */ - return; - } - break; - } - if (timeout < 0) { - usb_debug ("timeout. Device not ready. Still trying...\n"); - } else { - usb_debug ("ok.\n"); - } + /* Test if unit is ready. */ + usb_msc_test_unit_ready (dev); - usb_debug (" spin up"); - for (i = 0; i < 30; i++) { - usb_debug ("."); - switch (spin_up (dev)) { - case MSC_COMMAND_OK: - usb_debug (" OK."); - break; - case MSC_COMMAND_FAIL: - mdelay (100); - continue; - default: /* if it's worse return */ - return; - } - break; - } - usb_debug ("\n"); + /* Nothing to do if device is not ready. */ + if (!usb_msc_is_ready (dev)) + return; - if ((read_capacity (dev) == MSC_COMMAND_OK) && usbdisk_create) { - usbdisk_create (dev); - MSC_INST (dev)->usbdisk_created = 1; + /* Create the disk. */ + usb_msc_create_disk (dev); +} + +static void +usb_msc_poll (usbdev_t *dev) +{ + int prev_ready; + + /* Nothing to do if device is detached. */ + if (usb_msc_is_detached (dev)) + return; + + /* Handle ready transitions by keeping track of previous state . */ + prev_ready = usb_msc_is_ready (dev); + + usb_msc_test_unit_ready (dev); + + if (!prev_ready && usb_msc_is_ready (dev)) { + usb_debug ("usb msc: not ready -> ready\n"); + usb_msc_create_disk (dev); + } else if (prev_ready && !usb_msc_is_ready (dev)) { + usb_debug ("usb msc: ready -> not ready\n"); + usb_msc_remove_disk (dev); } } diff --git a/payloads/libpayload/include/usb/usbmsc.h b/payloads/libpayload/include/usb/usbmsc.h index 5c3dadc..8930156 100644 --- a/payloads/libpayload/include/usb/usbmsc.h +++ b/payloads/libpayload/include/usb/usbmsc.h @@ -36,9 +36,17 @@ typedef struct { endpoint_t *bulk_in; endpoint_t *bulk_out; int usbdisk_created; + int ready; void *data; /* For use by consumers of libpayload. */ } usbmsc_inst_t; +/* Possible values for ready field. */ +enum { + USB_MSC_DETACHED = -1, /* Disk detached or out to lunch. */ + USB_MSC_NOT_READY = 0, /* Disk not ready yet -- empty card reader */ + USB_MSC_READY = 1, /* Disk ready to communicate. */ +}; + #define MSC_INST(dev) ((usbmsc_inst_t*)(dev)->data) typedef enum { cbw_direction_data_in = 0x80, cbw_direction_data_out = 0

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Patch set updated for coreboot: 7168092 libpayload: usb mass storage detect empty media
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4225 -gerrit commit 716809248bdeeabb90ca4d8981617cf8b5dba94b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jun 6 16:14:21 2013 -0500 libpayload: usb mass storage detect empty media There is currently a hard-coded 30 sec delay in the mass storage driver while waiting for each device to become ready. However, mass storage card readers that are empty return an error code on the TEST UNIT READY command. A REQUEST SENSE command then needs to be issued and interrogate the data to determine if no media is present. If no media determination is found to be true the USB device is no longer considered a candidate to be a disk. This code does lead to the fact that the media card reader needs to be populated at enumeration time. I suspect this is not an issue as it appears the storage stack in libpayload can't handle removable media coming online later. Booted recovery and dev modes. Noted that removable mass storage devices with no media were ignored without any boot delay. Change-Id: Ida7a45614d97c6e6fbfc9bb099765aad4df550fd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57828 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/drivers/usb/usbmsc.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index ad7e82f..ffb1c93 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -123,6 +123,8 @@ enum { static int request_sense (usbdev_t *dev); +static int +request_sense_no_media (usbdev_t *dev); static int reset_transport (usbdev_t *dev) @@ -256,6 +258,11 @@ execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen, if (cb[0] == 0x03) /* requesting sense failed, that's bad */ return MSC_COMMAND_FAIL; + else if (cb[0] == 0) + /* If command was TEST UNIT READY determine if the + * device is of removable type indicating no media + * found. */ + return request_sense_no_media (dev); /* error "check condition" or reserved error */ ret = request_sense (dev); /* return fail or the status of request_sense if it's worse */ @@ -350,6 +357,34 @@ request_sense (usbdev_t *dev) sizeof (cb), buf, 19, 1); } +static int request_sense_no_media(usbdev_t *dev) +{ + u8 buf[19]; + int ret; + cmdblock6_t cb; + memset (&cb, 0, sizeof (cb)); + cb.command = 0x3; + + ret = execute_command (dev, cbw_direction_data_in, (u8 *) &cb, + sizeof (cb), buf, 19, 1); + + if (ret) + return ret; + + /* Check if sense key is set to NOT READY. */ + if ((buf[2] & 0xf) != 2) + return MSC_COMMAND_FAIL; + + /* Check if additional sense code is 0x3a. */ + if (buf[12] != 0x3a) + return MSC_COMMAND_FAIL; + + /* No media is present. Return MSC_COMMAND_DETACHED so as not to use + * this device any longer. */ + usb_debug("Empty media found.\n"); + return MSC_COMMAND_DETACHED; +} + static int test_unit_ready (usbdev_t *dev) {

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Patch set updated for coreboot: 7fddf74 slippy: update verbs for ALC283
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4224 -gerrit commit 7fddf74e55a6caff2ff56e7949f022ead5e6e5fd Author: Dylan Reid <dgreid(a)chromium.org> Date: Tue Jun 4 20:01:32 2013 -0700 slippy: update verbs for ALC283 Set verbs to reflect the layout used for the ALC283 in slippy. install on slippy and check that headphone switch works as does external mic. Change-Id: I2d6bcda9cf8bbf49cbb6d2dbbe7f1a5adf315d8a Signed-off-by: Dylan Reid <dgreid(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57560 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/slippy/hda_verb.h | 120 ++++++++++++++++----------------- 1 file changed, 58 insertions(+), 62 deletions(-) diff --git a/src/mainboard/google/slippy/hda_verb.h b/src/mainboard/google/slippy/hda_verb.h index 56275a2..3866a51 100644 --- a/src/mainboard/google/slippy/hda_verb.h +++ b/src/mainboard/google/slippy/hda_verb.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,81 +19,77 @@ static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 - 0x10134210, // Subsystem ID - 0x00000007, // Number of jacks + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000b, // Number of jacks (NID entries) - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */ - 0x00172010, - 0x00172142, - 0x00172213, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, 0x00172310, /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */ - 0x00571cf0, - 0x00571d20, - 0x00571e21, - 0x00571f02, + /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ + 0x00571c10, + 0x00571d10, + 0x00571ea6, + 0x00571fb7, - /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */ - 0x00671c10, - 0x00671d00, - 0x00671e17, - 0x00671f90, + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471c10, // group 1, front left/right + 0x01471d01, // no connector, no jack detect + 0x01471e17, // speaker out, analog + 0x01471f90, // fixed function, internal - /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */ - 0x00771cf0, - 0x00771d20, - 0x00771ea1, - 0x00771f02, + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, - /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */ - 0x00871c37, - 0x00871d00, - 0x00871ea7, - 0x00871f77, + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01971c11, // group 1, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f03, // connector, left panel - /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */ - 0x00971c3e, - 0x00971d00, - 0x00971ea6, - 0x00971f77, + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, - /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */ - 0x00a71cf0, - 0x00a71d10, - 0x00a71e45, - 0x00a71f43, + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, - /* coreboot specific header */ - 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ - 0x00172001, - 0x00172101, - 0x00172286, - 0x00172380, + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ - 0x30571c10, - 0x30571d00, - 0x30571e56, - 0x30571f18, + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ - 0x30671c20, - 0x30671d00, - 0x30671e56, - 0x30671f18, + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f03, // connector, left panel - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - 0x30771c30, - 0x30771d00, - 0x30771e56, - 0x30771f18 };

1 0

Patch set updated for coreboot: a82ba66 slippy: Update SPD
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4157 -gerrit commit a82ba66df36cfd49baff6981fb601eea48830062 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 3 15:59:59 2013 -0700 slippy: Update SPD Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50082 --- src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex | 17 +++++++++++++++++ src/mainboard/google/slippy/Makefile.inc | 3 ++- src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex | 17 +++++++++++++++++ .../google/slippy/Micron_MT41K256M16HA.spd.hex | 17 ----------------- 4 files changed, 36 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 1b80e6b..67b82e5 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -28,7 +28,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_MT41K256M16HA +SPD_SOURCES = Micron_4KTF25664HZ +SPD_SOURCES += Hynix_HMT425S6AFR6A SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex deleted file mode 100644 index a310e17..0000000 --- a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Micron MT41K256M16HA-125 DDR3L-1600 -92 11 0B 03 04 19 00 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2C 00 00 00 00 00 00 00 06 F2 -34 4A 54 46 32 35 36 36 20 34 48 5A 2D 31 47 36 -45 31 45 31 80 2C 00 00 00 00 00 00 00 00 01 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

1 0

Patch set updated for coreboot: efeb1be Make ssize_t an actual ssize_t
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4156 -gerrit commit efeb1be591dfdb1156bd60bf02c22808c5d822c2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 2 14:02:28 2013 -0700 Make ssize_t an actual ssize_t In the process of getting rid of compiler includes during in coreboot and libpayload, we defined size_t and ssize_t ourselves, using a GCC macro for size_t: __SIZE_TYPE__. Unfortunately, there is no __SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make __SIZE_TYPE__ __SSIZE_TYPE__. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b Reviewed-on: https://gerrit.chromium.org/gerrit/49947 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/stddef.h | 8 +++++++- src/include/stddef.h | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index 91ae782..f9deaeb 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -5,7 +5,13 @@ #define __SIZE_TYPE__ unsigned long #endif typedef __SIZE_TYPE__ size_t; -typedef long ssize_t; +/* There is a GCC macro for a size_t type, but not + * for a ssize_t type. Below construct tricks GCC + * into making __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *) 0)->MEMBER) diff --git a/src/include/stddef.h b/src/include/stddef.h index 5b51c00..d0dad62 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -6,7 +6,13 @@ typedef long ptrdiff_t; #define __SIZE_TYPE__ unsigned long #endif typedef __SIZE_TYPE__ size_t; -typedef long ssize_t; +/* There is a GCC macro for a size_t type, but not + * for a ssize_t type. Below construct tricks GCC + * into making __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned typedef int wchar_t; typedef unsigned int wint_t;

1 0

Patch set updated for coreboot: caab2a2 x86: call cbfstool update-fit when fit selected
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4159 -gerrit commit caab2a2c71aef108da23a96574a574d3500f95b4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 10:56:16 2013 -0500 x86: call cbfstool update-fit when fit selected In order for the FIT entries to be populated in the table the update-fit command needs to be done on the coreboot image. That way the microcode entries are added to the table properly. Change-Id: I44595aee1ca710f4f04d482d8900cf95fbc1797f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50317 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index dee56c5..3939122 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -130,6 +130,12 @@ endif ifeq ($(CONFIG_PXE_ROM),y) $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw endif +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) + @printf " UPDATE-FIT \n" + $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) +endif +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

1 0

Patch set updated for coreboot: 68bc45c lynxpoint: Expose ACPI Device for LP GPIO controller
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4158 -gerrit commit 68bc45c65baa0b8b76654d56049ad6f97a00e21c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 6 14:02:27 2013 -0700 lynxpoint: Expose ACPI Device for LP GPIO controller In order to probe the gpio-lynxpoint kernel driver the LP GPIO controller needs to be exposed as a specific ACPI device. This also allows the resources to be exposed to the OS via this device instead of the catch-all LPC device. Ensure the driver loads at boot: gpiochip_find_base: found new base at 162 gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00 Also ensure the driver is visible in sysfs: $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label INT33C7:00 Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50215 --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 58 ++++------------------- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 50 +++++++++++++++++++ 2 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index f9bf578..7e26926 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -199,60 +199,22 @@ Device (LPCB) 0x1, 0xff) // GPIO region may be 128 bytes or 4096 bytes - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, - 0x1, 0x00, GPR1) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR2) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR3) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR4) + IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) }) Method (_CRS, 0, NotSerialized) { - CreateByteField (^RBUF, ^GPR1._LEN, R1LN) - CreateByteField (^RBUF, ^GPR2._LEN, R2LN) - CreateByteField (^RBUF, ^GPR3._LEN, R3LN) - CreateByteField (^RBUF, ^GPR4._LEN, R4LN) + // LynxPoint-LP GPIO resources are defined in the + // SerialIO GPIO device and LynxPoint-H GPIO resources + // are defined here. + If (LNot (\ISLP ())) { + CreateByteField (^RBUF, ^GPR1._LEN, R1LN) + CreateWordField (^RBUF, ^GPR1._MIN, R1MN) + CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - CreateWordField (^RBUF, ^GPR1._MIN, R1MN) - CreateWordField (^RBUF, ^GPR2._MIN, R2MN) - CreateWordField (^RBUF, ^GPR3._MIN, R3MN) - CreateWordField (^RBUF, ^GPR4._MIN, R4MN) - - CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - CreateWordField (^RBUF, ^GPR2._MAX, R2MX) - CreateWordField (^RBUF, ^GPR3._MAX, R3MX) - CreateWordField (^RBUF, ^GPR4._MAX, R4MX) - - // Update GPIO region for LynxPoint-LP - If (\ISLP ()) { - // LynxPoint-LP - Store (R1MN, Local0) - - // Update GPIO bank 1 - Store (Local0, R1MN) - Store (Local0, R1MX) - Store (0xff, R1LN) - - // Update GPIO bank 2 - Add (Local0, 0x100, Local0) - Store (Local0, R2MN) - Store (Local0, R2MX) - Store (0xff, R2LN) - - // Update GPIO bank 3 - Add (Local0, 0x100, Local0) - Store (Local0, R3MN) - Store (Local0, R3MN) - Store (0xff, R3LN) - - // Update GPIO bank 4 - Add (Local0, 0x100, Local0) - Store (Local0, R4MN) - Store (Local0, R4MN) - Store (0xff, R4LN) - } Else { - // LynxPoint-H // Update GPIO region length + Store (DEFAULT_GPIOBASE, R1MN) + Store (DEFAULT_GPIOBASE, R1MX) Store (DEFAULT_GPIOSIZE, R1LN) } Return (RBUF) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 6ea23c6..03f6974 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -468,3 +468,53 @@ Device (SDIO) } } } + +Device (GPIO) +{ + // GPIO Controller + Name (_HID, "INT33C7") + Name (_CID, "INT33C7") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + DWordIo (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + EntireRange, // ISARanges + 0x00000000, // AddressGranularity + 0x00000000, // AddressMinimum + 0x00000000, // AddressMaximum + 0x00000000, // AddressTranslation + 0x00000000, // RangeLength + , // ResourceSourceIndex + , // ResourceSource + BAR0) + }) + + Method (_CRS, 0, NotSerialized) + { + If (\ISLP ()) { + CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) + CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) + CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) + + Store (DEFAULT_GPIOSIZE, BLEN) + Store (DEFAULT_GPIOBASE, BMIN) + Store (Subtract (Add (DEFAULT_GPIOBASE, + DEFAULT_GPIOSIZE), 1), BMAX) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (\ISLP ()) { + Return (0xF) + } Else { + Return (0x0) + } + } +}

1 0

Patch set updated for coreboot: cdf369b lynxpoint: Move ME lock down to ramstage
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4153 -gerrit commit cdf369b0d73873a41c334cefff4e844c310b3910 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 1 11:30:24 2013 -0700 lynxpoint: Move ME lock down to ramstage Now that we have RW ramstage we don't need to have the management engine lock down step done in a final SMM. ME: mkhi_end_of_post ME: END OF POST message successful (0) PCI: 00:16.0: Disabling device Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49757 --- src/mainboard/google/slippy/smihandler.c | 1 - src/mainboard/intel/baskingridge/mainboard_smi.c | 1 - src/mainboard/intel/wtm2/mainboard_smi.c | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/me_9.x.c | 59 ++++-------------------- 5 files changed, 11 insertions(+), 53 deletions(-) diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index bbdb7f9..01e763e 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -133,7 +133,6 @@ int mainboard_smi_apmc(u8 apmc) return 0; } - intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index e543494..f24af67 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -84,7 +84,6 @@ int mainboard_smi_apmc(u8 apmc) return 0; } - intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c index 3ffc684..bcc94d6 100644 --- a/src/mainboard/intel/wtm2/mainboard_smi.c +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -60,7 +60,6 @@ int mainboard_smi_apmc(u8 apmc) return 0; } - intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f1a82fb..370e017 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -46,7 +46,7 @@ ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c finalize.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 01eb844..bde4e9d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -47,7 +47,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ static const char *me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -58,7 +57,6 @@ static const char *me_bios_path_values[] = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); -#endif /* MMIO base address for MEI interface */ static u32 mei_base_address; @@ -116,14 +114,12 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "PCI READ"); } -#endif static inline void read_host_csr(struct mei_csr *csr) { @@ -351,7 +347,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -456,8 +452,6 @@ static int mkhi_global_reset(void) } #endif -#ifdef __SMM__ - /* Send END OF POST message to the ME */ static int mkhi_end_of_post(void) { @@ -485,43 +479,6 @@ static int mkhi_end_of_post(void) return 0; } -void intel_me_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - - mei_base_address = - pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; - - /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -#else /* !__SMM__ */ - /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(device_t dev) { @@ -679,6 +636,12 @@ static int intel_me_extend_valid(device_t dev) /* Hide the ME virtual PCI devices */ static void intel_me_hide(device_t dev) { + /* Make sure IO is disabled */ + u32 reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + dev->enabled = 0; pch_enable(dev); } @@ -729,9 +692,9 @@ static void intel_me_init(device_t dev) } #endif - /* - * Leave the ME unlocked. It will be locked via SMI command later. - */ + /* Lock down and hide Management Engine */ + mkhi_end_of_post(); + intel_me_hide(dev); } static void set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -953,5 +916,3 @@ mbp_failure: intel_me_mbp_give_up(dev); return -1; } - -#endif /* !__SMM__ */

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coreboot-gerrit November 2013