coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a93d141 AMD CAR: Fix issue with gcc 4.8.x
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4205 -gerrit commit a93d141b604075974c34944bf50567737fb07113 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Nov 19 14:26:50 2013 -0800 AMD CAR: Fix issue with gcc 4.8.x Starting with gcc 4.8.x we can't add ebp to the clobber list anymore. Since we're not actually using the register here, just removing it does not cause issues. Change-Id: I226c14b7e651919ec2d61cbcb18be50cf7f2f7a8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/amd/car/post_cache_as_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index eca7673..bad7535 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -119,7 +119,7 @@ static void post_cache_as_ram(void) ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) /* discard all registers (eax is used for %0), so gcc redoes everything after the stack is moved */ - : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" + : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi" ); /* We can put data to stack again */

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Patch set updated for coreboot: f4776e9 RTC: Skip rtc_init() in S3 resume path
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4206 -gerrit commit f4776e9cd9335d1287f7ee63356ea94d1948dcf1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 28 12:37:08 2013 -0700 RTC: Skip rtc_init() in S3 resume path In addition to not clearing the pending interrupts, we also don't want to reset the RTC control register when booting with an S3 resume. On most new systems, when the RTC well is losing power, we will also lose state that is required to perform a resume, so we end up in a normal boot anyways. Hence don't do any RTC initialization in the S3 resume path. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I73b486082faa741e9dccd15f2b8e3a8399c98f80 Reviewed-on: https://gerrit.chromium.org/gerrit/56826 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/pc80/mc146818rtc.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index be52454..79aba27 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -71,6 +71,17 @@ void rtc_init(int invalid) unsigned char x; #endif +#if CONFIG_HAVE_ACPI_RESUME + /* + * Avoid clearing pending interrupts and resetting the RTC control + * register in the resume path because the Linux kernel relies on + * this to know if it should restart the RTC timer queue if the wake + * was due to the RTC alarm. + */ + if (acpi_slp_type == 3) + return; +#endif + printk(BIOS_DEBUG, "RTC Init\n"); #if CONFIG_USE_OPTION_TABLE @@ -128,16 +139,6 @@ void rtc_init(int invalid) PC_CKS_RANGE_END,PC_CKS_LOC); #endif -#if CONFIG_HAVE_ACPI_RESUME - /* - * Avoid clearing pending interrupts in the resume path because - * the Linux kernel relies on this to know if it should restart - * the RTC timer queue if the wake was due to the RTC alarm. - */ - if (acpi_slp_type == 3) - return; -#endif - /* Clear any pending interrupts */ (void) cmos_read(RTC_INTR_FLAGS); }

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Patch set updated for coreboot: da581be x86: fix compile error for !CONFIG_MULTIBOOT
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4207 -gerrit commit da581be286afa538acbf5e62d001fae651b6f2fb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 16:15:01 2013 -0500 x86: fix compile error for !CONFIG_MULTIBOOT Some code was previously removed regarding elf notes. However, that code left a dangling comma under !CONFIG_MULTIBOOT configs for inline assembly constraints. Instead, place the comma within the #ifdef stanza. Change-Id: I805453ef57d34fbfb904b4d145d8874921d8d660 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56844 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: David James <davidjames(a)chromium.org> --- src/arch/x86/boot/boot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 7fc433d..1b28a4c 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -20,9 +20,9 @@ void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) " cld \n\t" :: - "r" (entry), + "r" (entry) #if CONFIG_MULTIBOOT - "b"(mbi), "a" (MB_MAGIC2) + , "b"(mbi), "a" (MB_MAGIC2) #endif ); }

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Patch set updated for coreboot: 4fbdc0d falco: Add Elpida DIMM SPD
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4192 -gerrit commit 4fbdc0d5487cd67bd186e96f88df5f25e55ca919 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 24 12:43:24 2013 -0700 falco: Add Elpida DIMM SPD This was provided by the vendor but I added the part number at byte 128-143 so it can be identified when extracted by mosys. Change-Id: Ib1e430cd390b4dbc013fc0802f1a59c1a0412577 Reviewed-on: https://gerrit.chromium.org/gerrit/56634 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex | 17 +++++++++++++++++ src/mainboard/google/falco/Makefile.inc | 1 + 2 files changed, 18 insertions(+) diff --git a/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex new file mode 100644 index 0000000..eb41f0b --- /dev/null +++ b/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex @@ -0,0 +1,17 @@ +# Elpida EDJ4216EFBG-GN-F +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index 7e6a9ac..e19db11 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -30,6 +30,7 @@ SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! SPD_SOURCES = Hynix_HMT425S6AFR6A SPD_SOURCES += Micron_4KTF25664HZ +SPD_SOURCES += Elpida_EDJ4216EFBG SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)

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Patch set updated for coreboot: 480e934 libpayload: allow for pointers in cbfs ram media
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4193 -gerrit commit 480e934c270e286f3fe1a84982bc6e59712de0d2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 24 13:34:38 2013 -0500 libpayload: allow for pointers in cbfs ram media The ram_map() handled offsets from 0->size as well as negative offsets from the top of the region. However, the cbfs core tries to map a offset that is actually a pointer within the region itself. Allow for such instances. This fixes an issue when using ram_media with tthe ebmedded SeaBIOS cbfs. Change-Id: I15b0b3b643390d3784ae5887c0f17d420d59c5b6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56641 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/libcbfs/ram_media.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 859555c..9f11a31 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -43,6 +43,12 @@ static int ram_open(struct cbfs_media *media) { static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { struct ram_media *m = (struct ram_media*)media->context; + + /* Special case an absolute pointer within the region. */ + if (offset >= (uintptr_t)m->start && + offset < ((uintptr_t)m->start + m->size)) + return (void *)offset; + /* assume addressing from top of image in this case */ if (offset > 0xf0000000) { offset = m->size + offset;

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Patch set updated for coreboot: 02138eb libpayload: expose cbfs ram functions
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4194 -gerrit commit 02138eb815f5d52e492778bc889a3f96ae29d65d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 24 13:40:51 2013 -0500 libpayload: expose cbfs ram functions The ram_media.c file is being compiled, however the global functions were not exposed through a header. Change-Id: I4588fbe320c29051566cef277bf4d20a83abf853 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56642 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/cbfs_ram.h | 61 +++++++++++++++++++++++++++++++++ payloads/libpayload/libcbfs/ram_media.c | 4 +-- 2 files changed, 62 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/include/cbfs_ram.h b/payloads/libpayload/include/cbfs_ram.h new file mode 100644 index 0000000..defe823 --- /dev/null +++ b/payloads/libpayload/include/cbfs_ram.h @@ -0,0 +1,61 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * This file is dual-licensed. You can choose between: + * - The GNU GPL, version 2, as published by the Free Software Foundation + * - The revised BSD license (without advertising clause) + * + * --------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * --------------------------------------------------------------------------- + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * --------------------------------------------------------------------------- + */ + +#ifndef _CBFS_RAM_H_ +#define _CBFS_RAM_H_ + +#include <stdint.h> + +struct cbfs_media; + +/* The following functions return 0 for success. None-zero on error. */ +int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size); +int setup_cbfs_from_ram(void *start, uint32_t size); +int setup_cbfs_from_flash(void); + +#endif /* _CBFS_RAM_H_ */ diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 9f11a31..a260b05 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ #include <cbfs.h> +#include <cbfs_ram.h> #include <string.h> #include <stdio.h> #include <stdlib.h> @@ -77,7 +78,6 @@ static int ram_close(struct cbfs_media *media) { return 0; } -int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size); int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size) { // TODO Find a way to release unused media. Maybe adding media->destroy. struct ram_media *m = (struct ram_media*)malloc(sizeof(*m)); @@ -96,7 +96,6 @@ int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size) { static int is_default_cbfs_media_initialized; static struct cbfs_media default_cbfs_media; -int setup_cbfs_from_ram(void *start, uint32_t size); int setup_cbfs_from_ram(void *start, uint32_t size) { int result = init_cbfs_ram_media(&default_cbfs_media, start, size); if (result == 0) @@ -105,7 +104,6 @@ int setup_cbfs_from_ram(void *start, uint32_t size) { } extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int setup_cbfs_from_flash(void); int setup_cbfs_from_flash(void) { int result = libpayload_init_default_cbfs_media(&default_cbfs_media); if (result == 0)

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Patch set updated for coreboot: deac4af haswell: Add magic to turn on grahpics in normal mode
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4195 -gerrit commit deac4af6b13c7de723b2f7b2d51161016c28e9d9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:49:09 2013 -0700 haswell: Add magic to turn on grahpics in normal mode The haswell i915 kernel driver apparently expects the VBIOS to set a few specific registers. This sequence is enough to make the driver happy without executing the VBIOS. This also makes graphics work after suspend/resume. Change-Id: I34937d55ffff8a9445442e6e6ca1bfc49869da63 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56806 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f3ddbd3..467ed93 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -131,17 +131,13 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write(0x0a094, 0x00040000); } -static void gma_pm_init_post_vbios(struct device *dev) +static void gma_setup_panel(struct device *dev) { struct northbridge_intel_haswell_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - /* Disable Force Wake */ - gtt_write(0x0a188, 0x00010000); - gtt_poll(0x130044, 1 << 0, 0 << 0); - /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { @@ -187,6 +183,22 @@ static void gma_pm_init_post_vbios(struct device *dev) } } +static void gma_pm_init_post_vbios(struct device *dev) +{ + extern int oprom_is_loaded; + + if (!oprom_is_loaded) { + /* Magic to force graphics into happy state for kernel */ + gtt_write(0xc7204, 0xabcd000f); /* panel power up */ + gtt_write(0x45400, 0x80000000); /* power well enable */ + gtt_write(0x64000, 0x00000091); /* DDI-A enable */ + } + + /* Disable Force Wake */ + gtt_write(0x0a188, 0x00010000); + gtt_poll(0x130044, 1 << 0, 0 << 0); +} + static void gma_func0_init(struct device *dev) { int lightup_ok = 0; @@ -203,9 +215,13 @@ static void gma_func0_init(struct device *dev) * So it's almost like having two hardcodes. */ graphics_base = dev->resource_list[1].base; + /* Init graphics power management */ gma_pm_init_pre_vbios(dev); + /* Post VBIOS init */ + gma_setup_panel(dev); + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); u32 iobase, mmiobase, physbase;

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Patch set updated for coreboot: 26aee8e slippy: Add panel power sequence timings
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4196 -gerrit commit 26aee8ee3064f48a5a8308dc41b76f40b7941d02 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:54:15 2013 -0700 slippy: Add panel power sequence timings These are placeholder values until we can configure for the exact panel. Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56807 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index fc6462c..b9bc47f 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -13,6 +13,14 @@ chip northbridge/intel/haswell register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000" + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end

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Patch set updated for coreboot: a6b6a60 falco: Add panel power sequence timings
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4197 -gerrit commit a6b6a6071e4bb9eee3ccc95d906887b0bd87d8d7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:55:02 2013 -0700 falco: Add panel power sequence timings These are placeholder values until we can configure for the exact panel. Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56808 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index fc6462c..b9bc47f 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -13,6 +13,14 @@ chip northbridge/intel/haswell register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000" + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end

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Patch set updated for coreboot: 7cf948f falco: Update DIMM SPD table
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4198 -gerrit commit 7cf948f0c79c21043bffa1a34ce1e6007bdc091a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 08:32:21 2013 -0700 falco: Update DIMM SPD table RAM_ID indices have been changed and settled on a 2GB config that will be the same DRAM chips but only used in one channel. Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56810 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/Makefile.inc | 9 ++++++--- src/mainboard/google/falco/romstage.c | 6 ++++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index e19db11..edb8cf6 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -28,9 +28,12 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Hynix_HMT425S6AFR6A -SPD_SOURCES += Micron_4KTF25664HZ -SPD_SOURCES += Elpida_EDJ4216EFBG +SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 +SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 +SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only +SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only +SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 3bf1dbd..ef6a849 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -91,6 +91,12 @@ static void copy_spd(struct pei_data *peid) if (spd_file->len < sizeof(peid->spd_data[0])) die("Missing SPD data."); + /* Index 0-2 are 4GB config with both CH0 and CH1 + * Index 3-5 are 2GB config with CH0 only + */ + if (spd_index > 2) + peid->dimm_channel1_disabled = 3; + memcpy(peid->spd_data[0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index * sizeof(peid->spd_data[0]),

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coreboot-gerrit November 2013