Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4172
-gerrit
commit 5b0fe8363ed15d892b8e02309896ddbb1e72b1e3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed May 15 17:02:23 2013 -0700
slippy: set PWM values
The dev screen was not displaying properly. With the
PWM values programmed the screen displays correctly.
Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51472
---
src/mainboard/google/slippy/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 143147f..29c4763 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -9,6 +9,10 @@ chip northbridge/intel/haswell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4163
-gerrit
commit 72380e40ed9edbcd4cf67a8188c663afe567cb06
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 7 13:19:56 2013 -0700
haswell: Remove limit on package C-state
With the XHCI controller enabled we no longer hang the
system when dropping into a package C-state so remove
the code that was disabling it.
Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50355
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/cpu/intel/haswell/haswell_init.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 071135c..b2e6eaf 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -426,10 +426,7 @@ static void configure_c_states(void)
msr.lo |= (1 << 26); // C1 Auto Demotion Enable
msr.lo |= (1 << 25); // C3 Auto Demotion Enable
msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
- msr.lo &= ~(0xf); // Clear deepest package c-state
- /* FIXME: The deepest package c-state is set to C0/C1 to work around
- * platform instability when package C3 or deeper c-states are used. */
- msr.lo |= 0; // Deepeset package c-state is C0/C1.
+ /* The deepest package c-state defaults to factory-configured value. */
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4160
-gerrit
commit e7929dcf530ef8047ed95d5a6bf738579842efff
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 7 11:05:06 2013 -0500
haswell: split microcode between ULT and non-ULT
The current microcode blobs contain both ULT and non-ULT
revisions. Only include one or the other based off of the
CONFIG_INTEL_LYNXPOINT_LP Kconfig option.
Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50318
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/cpu/intel/haswell/microcode_blob.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h
index fabadee..5b4f74a 100644
--- a/src/cpu/intel/haswell/microcode_blob.h
+++ b/src/cpu/intel/haswell/microcode_blob.h
@@ -17,11 +17,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if CONFIG_INTEL_LYNXPOINT_LP
+#include "microcode-M7240650_ffff000a.h"
+#include "microcode-M7240651_0000000a.h"
+#else
#include "microcode-M32306c1_ffff000d.h"
#include "microcode-M32306c2_ffff0003.h"
#include "microcode-M3240660_ffff000b.h"
-#include "microcode-M7240650_ffff000a.h"
-#include "microcode-M7240651_0000000a.h"
+#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4161
-gerrit
commit 121e4b633024411a06dbfd6f819b46a9b74e5118
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 7 11:14:01 2013 -0500
cbfstool: check potential microcode update earlier
The update-fit command takes in a parameter for number of slots
in the FIT table. It then processes the microcobe blob in cbfs
adding those entries to the FIT table. However, the tracking of
the number of mircocode updates was incremented before validating
the update. Therefore, move the sanity checking before an increment
of the number of updates.
Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50319
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
util/cbfstool/fit.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index 12a7e3b..02cfaee 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -206,6 +206,10 @@ static int parse_microcode_blob(struct cbfs_image *image,
mcu_header = rom_buffer_pointer(image, current_offset);
+ /* Quickly sanity check a prospective microcode update. */
+ if (mcu_header->total_size < sizeof(*mcu_header))
+ break;
+
/* FIXME: Should the checksum be validated? */
mcus[num_mcus].offset = current_offset;
mcus[num_mcus].size = mcu_header->total_size;
@@ -215,10 +219,6 @@ static int parse_microcode_blob(struct cbfs_image *image,
num_mcus++;
file_length -= mcus[num_mcus].size;
- /* Can't determine any more entries. */
- if (!mcu_header->total_size)
- break;
-
/* Reached limit of FIT entries. */
if (num_mcus == *total_mcus)
break;
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4167
-gerrit
commit 68dd7269a55bb5de70e69a2a5813770ec6b2e20d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 10 11:00:56 2013 -0700
slippy: Add EC to the device tree
This lets the keyboard init get called properly.
Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50853
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/slippy/devicetree.cb | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 5fb3cb4..665e6dc 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -84,7 +84,15 @@ chip northbridge/intel/haswell
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on end # LPC bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal