Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4182
-gerrit
commit 10cfa8036aeacefcff8cba0af6d84012672a4dce
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed May 22 15:28:20 2013 -0500
lynxpoint: fix mem corruption during ssdt2 gen
The ssdt2 generation code was calling acpigen_patch_len().
However, none of the entries had AML object lengths that
needed patching. That resulted in the following message:
ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c', Â line 52
Additionally, this caused an errant write to a memory address
whose value was in the variable ltop. This was the 0 address.
Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56299
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
---
src/southbridge/intel/lynxpoint/acpi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c
index ccf4323..b619e6e 100644
--- a/src/southbridge/intel/lynxpoint/acpi.c
+++ b/src/southbridge/intel/lynxpoint/acpi.c
@@ -88,7 +88,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
/* Fill the SSDT with an entry for each SerialIO device */
for (id = 0; id < 8; id++)
len += acpi_create_serialio_ssdt_entry(id, gnvs);
- acpigen_patch_len(len-1);
/* (Re)calculate length and checksum. */
current = (unsigned long)acpigen_get_current();
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4181
-gerrit
commit 4fcad8ebb1f0bd8d562dc98ccc48edc5444b1cb3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 22 09:51:11 2013 -0700
lynxpoint: Fix XHCI controller device in ACPI
The ACPI code was defining two EHCI controllers and ignoring
the XHCI controller. This changes the second EHCI controller
to be XHCI instead and changes the wake resource to indicate
S3 and not S4.
cat /proc/acpi/wakeup
Device S-state Status Sysfs node
HDEF S4 *disabled pci:0000:00:1b.0
EHCI S3 *enabled pci:0000:00:1d.0
XHCI S3 *enabled pci:0000:00:14.0
Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56263
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/acpi/usb.asl | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl
index cf3e6a0..5c1f6a5 100644
--- a/src/southbridge/intel/lynxpoint/acpi/usb.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl
@@ -23,11 +23,11 @@
// EHCI Controller 0:1d.0
-Device (EHC1)
+Device (EHCI)
{
Name(_ADR, 0x001d0000)
- Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+ Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
// Leave USB ports on for to allow Wake from USB
@@ -55,13 +55,13 @@ Device (EHC1)
}
}
-// EHCI #2 Controller 0:1a.0
+// XHCI Controller 0:14.0
-Device (EHC2)
+Device (XHCI)
{
- Name(_ADR, 0x001a0000)
+ Name(_ADR, 0x00140000)
- Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+ Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
// Leave USB ports on for to allow Wake from USB
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4171
-gerrit
commit df9fbe0d48248556a85d67511ec8182d82a05f1d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 15 15:05:38 2013 -0700
slippy: Put SerialIO devices in PCI mode
The device at function 0 also needs to be enabled
or the kernel will ignore all other functions.
00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03)
00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03)
00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03)
Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51370
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/slippy/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 665e6dc..143147f 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -56,13 +56,13 @@ chip northbridge/intel/haswell
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
- register "sio_acpi_mode" = "1"
+ register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
- device pci 15.0 off end # Serial I/O DMA
+ device pci 15.0 on end # Serial I/O DMA
device pci 15.1 on end # I2C0
device pci 15.2 on end # I2C1
device pci 15.3 off end # GSPI0
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4174
-gerrit
commit 3f510b8e27b08b2d584d7f6dd85671f64cb75b66
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri May 17 11:56:09 2013 -0700
libpayload (EHCI): correctly align PORTSC
Two structures in the USB EHCI stack were pointing
to hardware but not marked attribute((packed)) hence
leaving it to GCC to correctly align the data structures.
Next, the number of reserved bytes in hc_op_t was wrong
(but implicitly aligned to the correct values on x86)
It seems this worked fine on x86, but on ARM it was doing
the wrong thing.
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d
Reviewed-on: https://gerrit.chromium.org/gerrit/55555
Commit-Queue: Stefan Reinauer <reinauer(a)google.com>
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Tested-by: Stefan Reinauer <reinauer(a)google.com>
---
payloads/libpayload/drivers/usb/ehci_private.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h
index 3b9faf6..3365be1 100644
--- a/payloads/libpayload/drivers/usb/ehci_private.h
+++ b/payloads/libpayload/drivers/usb/ehci_private.h
@@ -78,10 +78,10 @@ typedef volatile struct {
u32 ctrldssegment;
u32 periodiclistbase;
u32 asynclistaddr;
- u8 res1[0x3f-0x1c];
+ u8 res1[0x40-0x1c];
u32 configflag;
portsc_t portsc[0];
-} hc_op_t;
+} __attribute__ ((packed)) hc_op_t;
typedef volatile struct {
#define QTD_TERMINATE 1
@@ -130,7 +130,7 @@ typedef volatile struct {
#define QH_PIPE_MULTIPLIER_SHIFT 30
volatile u32 current_td_ptr;
volatile qtd_t td;
-} ehci_qh_t;
+} __attribute__ ((packed)) ehci_qh_t;
typedef struct ehci {
hc_cap_t *capabilities;