coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: b44f079 lynxpoint: Move ME lock down to ramstage
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4153 -gerrit commit b44f079e86df77fc9ff516245c131ee27fcbc754 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 1 11:30:24 2013 -0700 lynxpoint: Move ME lock down to ramstage Now that we have RW ramstage we don't need to have the management engine lock down step done in a final SMM. ME: mkhi_end_of_post ME: END OF POST message successful (0) PCI: 00:16.0: Disabling device Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49757 --- src/mainboard/google/slippy/smihandler.c | 1 - src/mainboard/intel/baskingridge/mainboard_smi.c | 1 - src/mainboard/intel/wtm2/mainboard_smi.c | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/me_9.x.c | 59 ++++-------------------- 5 files changed, 11 insertions(+), 53 deletions(-) diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index bbdb7f9..01e763e 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -133,7 +133,6 @@ int mainboard_smi_apmc(u8 apmc) return 0; } - intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index e543494..f24af67 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -84,7 +84,6 @@ int mainboard_smi_apmc(u8 apmc) return 0; } - intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c index 3ffc684..bcc94d6 100644 --- a/src/mainboard/intel/wtm2/mainboard_smi.c +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -60,7 +60,6 @@ int mainboard_smi_apmc(u8 apmc) return 0; } - intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f1a82fb..370e017 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -46,7 +46,7 @@ ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c finalize.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 01eb844..bde4e9d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -47,7 +47,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ static const char *me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -58,7 +57,6 @@ static const char *me_bios_path_values[] = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); -#endif /* MMIO base address for MEI interface */ static u32 mei_base_address; @@ -116,14 +114,12 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "PCI READ"); } -#endif static inline void read_host_csr(struct mei_csr *csr) { @@ -351,7 +347,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -456,8 +452,6 @@ static int mkhi_global_reset(void) } #endif -#ifdef __SMM__ - /* Send END OF POST message to the ME */ static int mkhi_end_of_post(void) { @@ -485,43 +479,6 @@ static int mkhi_end_of_post(void) return 0; } -void intel_me_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - - mei_base_address = - pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; - - /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -#else /* !__SMM__ */ - /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(device_t dev) { @@ -679,6 +636,12 @@ static int intel_me_extend_valid(device_t dev) /* Hide the ME virtual PCI devices */ static void intel_me_hide(device_t dev) { + /* Make sure IO is disabled */ + u32 reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + dev->enabled = 0; pch_enable(dev); } @@ -729,9 +692,9 @@ static void intel_me_init(device_t dev) } #endif - /* - * Leave the ME unlocked. It will be locked via SMI command later. - */ + /* Lock down and hide Management Engine */ + mkhi_end_of_post(); + intel_me_hide(dev); } static void set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -953,5 +916,3 @@ mbp_failure: intel_me_mbp_give_up(dev); return -1; } - -#endif /* !__SMM__ */

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Patch set updated for coreboot: f72926e lynxpoint: Add missing ME MBP entries
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4152 -gerrit commit f72926eb19dffbf674de6920b37d05918c523ac8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 1 11:27:58 2013 -0700 lynxpoint: Add missing ME MBP entries There were two undefined MBP types that are now defined. These include NFC status and some interesting timing data. ME: Wake Event to ME Reset: 6 ms ME: ME Reset to Platform Reset: 7 ms ME: Platform Reset to CPU Reset: 51 ms Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49756 --- src/southbridge/intel/lynxpoint/me.h | 17 +++++++++++++++++ src/southbridge/intel/lynxpoint/me_9.x.c | 17 ++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index a305822..d919107 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -334,6 +334,7 @@ void intel_me8_finalize_smm(void); #define MBP_APPID_INTEL_AT 3 #define MBP_APPID_HWA 4 #define MBP_APPID_ICC 5 +#define MBP_APPID_NFC 6 /* Kernel items: */ #define MBP_KERNEL_FW_VER_ITEM 1 #define MBP_KERNEL_FW_CAP_ITEM 2 @@ -341,12 +342,15 @@ void intel_me8_finalize_smm(void); #define MBP_KERNEL_PLAT_KEY_ITEM 4 #define MBP_KERNEL_FW_TYPE_ITEM 5 #define MBP_KERNEL_MFS_FAILURE_ITEM 6 +#define MBP_KERNEL_PLAT_TIME_ITEM 7 /* Intel AT items: */ #define MBP_INTEL_AT_STATE_ITEM 1 /* ICC Items: */ #define MBP_ICC_PROFILE_ITEM 1 /* HWA Items: */ #define MBP_HWA_REQUEST_ITEM 1 +/* NFC Items: */ +#define MBP_NFC_SUPPORT_DATA_ITEM 1 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) #define MBP_IDENT(appid, item) \ @@ -453,6 +457,17 @@ typedef struct { } __attribute__ ((packed)) mbp_at_state; typedef struct { + u32 wake_event_mrst_time_ms; + u32 mrst_pltrst_time_ms; + u32 pltrst_cpurst_time_ms; +} __attribute__ ((packed)) mbp_plat_time; + +typedef struct { + u32 device_type : 2; + u32 reserved : 30; +} __attribute__ ((packed)) mbp_nfc_data; + +typedef struct { mbp_fw_version_name *fw_version_name; mbp_mefwcaps *fw_capabilities; mbp_rom_bist_data *rom_bist_data; @@ -461,6 +476,8 @@ typedef struct { mbp_icc_profile *icc_profile; mbp_at_state *at_state; u32 *mfsintegrity; + mbp_plat_time *plat_time; + mbp_nfc_data *nfc_data; } me_bios_payload; struct me_fwcaps { diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index a16879b..01eb844 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -712,12 +712,21 @@ static void intel_me_init(device_t dev) if (intel_mei_setup(dev) < 0) return; - if(intel_me_read_mbp(&mbp_data, dev)) + if (intel_me_read_mbp(&mbp_data, dev)) return; #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); me_print_fwcaps(mbp_data.fw_capabilities); + + if (mbp_data.plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data.plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data.plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data.plat_time->pltrst_cpurst_time_ms); + } #endif /* @@ -923,6 +932,12 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) case MBP_IDENT(KERNEL, MFS_FAILURE): ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); + case MBP_IDENT(KERNEL, PLAT_TIME): + ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); + + case MBP_IDENT(NFC, SUPPORT_DATA): + ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); + default: printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ dw offset 0x%x\n", mbp->data[i], i);

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Patch set updated for coreboot: 35319b9 call fill_lb_framebuffer() earlier
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4155 -gerrit commit 35319b9c6a419e84ed4502e2696ddc1a38b6ba0f Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 18:23:24 2013 -0700 call fill_lb_framebuffer() earlier fill_lb_framebuffer() now sets the framebuffer pointer according to the EDID information, so it must be called before setting the tag and size. (credit to rminnich for this, I'm just uploading it) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I5ac783fa3a776eee504d39889284041d1dc2c92a Reviewed-on: https://gerrit.chromium.org/gerrit/50012 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/lib/coreboot_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e5729ba..a0a806d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -177,9 +177,9 @@ static void lb_framebuffer(struct lb_header *header) return; struct lb_framebuffer *framebuffer; framebuffer = (struct lb_framebuffer *)lb_new_record(header); + fill_lb_framebuffer(framebuffer); framebuffer->tag = LB_TAG_FRAMEBUFFER; framebuffer->size = sizeof(*framebuffer); - fill_lb_framebuffer(framebuffer); #endif }

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Patch set updated for coreboot: 0a2e3c7 slippy: Add SPD data for on-board memory
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4154 -gerrit commit 0a2e3c79038c046ceb8582d733a34c9e32699abb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 2 10:40:49 2013 -0700 slippy: Add SPD data for on-board memory Change-Id: I7a617fe06d23b906f718ed30f1378f7d220b2799 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49911 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/Makefile.inc | 21 +++++++++++++ .../google/slippy/Micron_MT41K256M16HA.spd.hex | 17 +++++++++++ src/mainboard/google/slippy/romstage.c | 34 +++++++++++++++++++++- 3 files changed, 71 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 92256e8..1b80e6b 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -23,3 +23,24 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_MT41K256M16HA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $^; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex new file mode 100644 index 0000000..a310e17 --- /dev/null +++ b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex @@ -0,0 +1,17 @@ +# Micron MT41K256M16HA-125 DDR3L-1600 +92 11 0B 03 04 19 00 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 06 F2 +34 4A 54 46 32 35 36 36 20 34 48 5A 2D 31 47 36 +45 31 45 31 80 2C 00 00 00 00 00 00 00 00 01 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index e44e485..a02a84d 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -21,6 +21,8 @@ #include <delay.h> #include <stdint.h> #include <stdlib.h> +#include <string.h> +#include <cbfs.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" @@ -73,6 +75,33 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; +/* Copy SPD data for on-board memory */ +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + struct cbfs_file *spd_file; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + if (ntohl(spd_file->len) < + ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file->len < sizeof(peid->spd_data[0])) + die("Missing SPD data."); + + memcpy(peid->spd_data[0], + ((char*)CBFS_SUBHEADER(spd_file)) + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); +} + /* * Power Sequencing for SanDisk i100/i110 SSD * @@ -124,7 +153,7 @@ void mainboard_romstage_entry(unsigned long bist) temp_mmio_base: 0xfed08000, system_type: 5, /* ULT */ tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xa2, 0x00, 0xa2, 0x00 }, + spd_addresses: { 0xff, 0x00, 0xff, 0x00 }, ec_present: 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel @@ -152,6 +181,9 @@ void mainboard_romstage_entry(unsigned long bist) .bist = bist, }; + /* Prepare SPD data */ + copy_spd(&pei_data); + /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params);

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Patch set updated for coreboot: 3ee785d lynxpoint: export mem console pointer in ACPI
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4149 -gerrit commit 3ee785d19599a297df7546e710baa0c203d80ea5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 13:41:44 2013 -0500 lynxpoint: export mem console pointer in ACPI Instead of having an OS re-parse cbmem book-keeping records for the cbmem allocator just to get the console buffer export the pointer to the memory console directly in a field named 'CBMC'. This field lives in the GNVS table. Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49764 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/slippy/acpi_tables.c | 3 +++ src/mainboard/intel/baskingridge/acpi_tables.c | 3 +++ src/mainboard/intel/wtm2/acpi_tables.c | 3 +++ src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 3 +++ src/southbridge/intel/lynxpoint/nvs.h | 3 ++- 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 16a1c6a..e08a7ce 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -103,6 +103,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index c4adcd7..f4b74bc 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -106,6 +106,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 16a1c6a..e08a7ce 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -103,6 +103,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + acpi_update_thermal_table(gnvs); } diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 8f6c825..ef05dca 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -131,6 +131,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1 S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1 + Offset (0xa0), + CBMC, 32, // 0xa0 - coreboot mem console pointer + /* IGD OpRegion */ Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 3df1da1..4283ca1 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -90,7 +90,8 @@ typedef struct { /* LynxPoint Serial IO device BARs */ u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ - u8 rsvd6[20]; + u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ + u8 rsvd6[16]; /* IGD OpRegion (not implemented yet) */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ u8 ibtt; /* 0xb8 - IGD boot type */

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Patch set updated for coreboot: 6c981bb haswell: enable monotonic timer
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4148 -gerrit commit 6c981bb0e149e8072fab1fc5b3413dd8c601e7e9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 13:29:45 2013 -0500 haswell: enable monotonic timer For all the current haswell boards enable the monotonic timer. The ULT boards use the 24MHz MSR while the non-ULT boards use the local apic. Change-Id: I8b19f526a5a49e8467f296c566a2c4263bc5a863 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49763 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/intel/baskingridge/Kconfig | 1 + src/mainboard/intel/wtm2/Kconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index b7f0b76..a53ac00 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXTERNAL_MRC_BLOB select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB + select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX hex diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index cf4a901..23f2ebe 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select CHROMEOS + select LAPIC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index dfee8ab..d5b55d8 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string

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Patch set updated for coreboot: 09b7d32 slippy: Prepare LPC IO decode ranges for EC
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4151 -gerrit commit 09b7d32bd88a4227998f68bf79e486969032d348 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 1 11:12:53 2013 -0700 slippy: Prepare LPC IO decode ranges for EC - 0x200-0x208 for host command window - 0x800-0x8ff for host command arguments and parameters - 0x900-0x9ff for exported EC memory map Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49755 --- src/mainboard/google/slippy/devicetree.cb | 4 ++++ src/southbridge/intel/lynxpoint/early_pch.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 8cf387f..5fb3cb4 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -41,6 +41,10 @@ chip northbridge/intel/haswell register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 1a78d57..7a24e1f 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -102,7 +102,7 @@ static void pch_enable_lpc(void) pci_write_config16(dev, LPC_IO_DEC, 0x0010); /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); }

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Patch set updated for coreboot: 4df07ea slippy: Add iSSD power sequencing
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4150 -gerrit commit 4df07ea33f11d59816effea62bf66d54ac5a80d1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 1 11:11:10 2013 -0700 slippy: Add iSSD power sequencing Without an LM10506-A the power sequencing for this part needs to be done manually using GPIOs. Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49648 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/romstage.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index be1caa9..e44e485 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <delay.h> #include <stdint.h> +#include <stdlib.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" @@ -71,6 +73,39 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; +/* + * Power Sequencing for SanDisk i100/i110 SSD + * + * Must be sequenced in this order with specified timing. + * + * 1. VCC_IO : 30us - 100ms + * 2. VCC_FLASH : 70us - 10ms + * 3. VCCQ : 70us - 10ms + * 4. VDDC : 30us - 100ms + * + * There is no feedback to know if the voltage has stabilized + * so this implementation will use the max ramp times. That + * means it adds significantly to the boot time. + */ +static void issd_power_sequence(void) +{ + struct gpio_seq { + int gpio; + int wait_ms; + } issd_gpio_seq[] = { + { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ + { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ + { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ + { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ + }; + int step; + + for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) { + set_gpio(issd_gpio_seq[step].gpio, 1); + udelay(issd_gpio_seq[step].wait_ms * 1000); + } +} + void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { @@ -119,4 +154,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); + + /* Power sequence the iSSD module */ + issd_power_sequence(); }

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Patch set updated for coreboot: 9de0424 smi: Update mainboard_smi_gpi() to have 32bit argument
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4145 -gerrit commit 9de04242d3d442352391f80c43b265a399d3a3ad Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 29 15:04:30 2013 -0700 smi: Update mainboard_smi_gpi() to have 32bit argument With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/smm/smm_module_handler.c | 2 +- src/include/cpu/x86/smm.h | 4 ++-- src/mainboard/getac/p470/smihandler.c | 2 +- src/mainboard/google/butterfly/mainboard_smi.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/parrot/smihandler.c | 2 +- src/mainboard/google/stout/mainboard_smi.c | 2 +- src/mainboard/kontron/ktqm77/smihandler.c | 2 +- src/mainboard/lenovo/t60/smihandler.c | 2 +- src/mainboard/lenovo/x60/smihandler.c | 2 +- src/mainboard/roda/rk9/smihandler.c | 2 +- src/mainboard/samsung/lumpy/smihandler.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 4 ++-- 13 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 116dafa..444e335 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -165,6 +165,6 @@ int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } void __attribute__((weak)) cpu_smi_handler(void) {} void __attribute__((weak)) northbridge_smi_handler() {} void __attribute__((weak)) southbridge_smi_handler() {} -void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts) {} +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cacbff0..607c0f0 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -387,7 +387,7 @@ void southbridge_smi_set_eos(void); void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); -void mainboard_smi_gpi(u16 gpi_sts); +void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); #else @@ -395,7 +395,7 @@ void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_are void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts); int __attribute__((weak)) mainboard_smi_apmc(u8 data); void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); #endif /* CONFIG_SMM_MODULES */ diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 6122c82..c66abad 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -180,7 +180,7 @@ static void mainboard_smi_hotkey(u8 hotkey) printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey); } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { u8 source, hotkey; send_ec_oem_command(0x5c); diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index e2f00e1..a40e428 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -52,7 +52,7 @@ int mainboard_io_trap_handler(int smif) return 1; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts); } diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index a4c4a50..3785121 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -80,7 +80,7 @@ static u8 mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events */ diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a5f6ba2..72a3a1b 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -125,7 +125,7 @@ static u8 mainboard_smi_ec(void) return src; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { u32 pm1_cnt; diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 0f2ecd5..44dc46e 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -72,7 +72,7 @@ static u8 mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events */ diff --git a/src/mainboard/kontron/ktqm77/smihandler.c b/src/mainboard/kontron/ktqm77/smihandler.c index fd95b93..18ff68d 100644 --- a/src/mainboard/kontron/ktqm77/smihandler.c +++ b/src/mainboard/kontron/ktqm77/smihandler.c @@ -48,7 +48,7 @@ int mainboard_io_trap_handler(int smif) return 1; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts); } diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index f4bad8b..093996b 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -152,7 +152,7 @@ static void mainboard_smi_handle_ec_sci(void) } } -void mainboard_smi_gpi(u16 gpi) +void mainboard_smi_gpi(u32 gpi) { if (gpi & (1 << 12)) mainboard_smi_handle_ec_sci(); diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 5a7130f..090f037 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -158,7 +158,7 @@ static void mainboard_smi_handle_ec_sci(void) } } -void mainboard_smi_gpi(u16 gpi) +void mainboard_smi_gpi(u32 gpi) { if (gpi & (1 << 12)) mainboard_smi_handle_ec_sci(); diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index fe68c4b..baa038e 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -50,7 +50,7 @@ int mainboard_io_trap_handler(int smif) return 1; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << 1)) { printk(BIOS_DEBUG, "EC/SMI\n"); diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 9306a02..417ccd8 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -70,7 +70,7 @@ static u8 mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending EC requests */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 491f997..99f6b51 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -626,7 +626,7 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) { - void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi; + void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi; u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); outw(reg16, pmbase + ALT_GP_SMI_STS); @@ -638,7 +638,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ mainboard_gpi(reg16); } else { if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); + printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); } outw(reg16, pmbase + ALT_GP_SMI_STS);

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Patch set updated for coreboot: 6117e43 elog: Make sure the elog data structures are initialized in elog_clear.
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4144 -gerrit commit 6117e431574ab464483cda1345c3d395b1e00cf9 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Apr 25 17:21:58 2013 -0700 elog: Make sure the elog data structures are initialized in elog_clear. If elog_clear is called before other elog functions, for instance if it's called through an SMI immediately after the system boots, then the elog data structures won't have been set up and the system will go off the deep end. This change adds a call to elog_init to elog_clear to make sure things things are always initialized before we start using them. Before this change, this command would cause the system to lock up if run immediately after boot: echo 1 > /sys/firmware/gsmi/clear_eventlog After this change, that results in the log being cleared correctly. Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49303 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/drivers/elog/elog.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 6e89b5f..6de5123 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -746,6 +746,10 @@ int elog_clear(void) elog_debug("elog_clear()\n"); + /* Make sure ELOG structures are initialized */ + if (elog_init() < 0) + return -1; + /* Erase flash area */ elog_flash_erase_area();

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coreboot-gerrit November 2013