coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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856 discussions

Patch set updated for coreboot: 4e70953 haswell: split microcode between ULT and non-ULT
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4160 -gerrit commit 4e70953115d21169aeb55e17de5b9e75c66df948 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 11:05:06 2013 -0500 haswell: split microcode between ULT and non-ULT The current microcode blobs contain both ULT and non-ULT revisions. Only include one or the other based off of the CONFIG_INTEL_LYNXPOINT_LP Kconfig option. Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50318 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/haswell/microcode_blob.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index fabadee..5b4f74a 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -17,11 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_INTEL_LYNXPOINT_LP +#include "microcode-M7240650_ffff000a.h" +#include "microcode-M7240651_0000000a.h" +#else #include "microcode-M32306c1_ffff000d.h" #include "microcode-M32306c2_ffff0003.h" #include "microcode-M3240660_ffff000b.h" -#include "microcode-M7240650_ffff000a.h" -#include "microcode-M7240651_0000000a.h" +#endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

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Patch set updated for coreboot: abab5c4 cbfstool: check potential microcode update earlier
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4161 -gerrit commit abab5c4c4212b9363d5ff84e54592f3fe8926d9e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 11:14:01 2013 -0500 cbfstool: check potential microcode update earlier The update-fit command takes in a parameter for number of slots in the FIT table. It then processes the microcobe blob in cbfs adding those entries to the FIT table. However, the tracking of the number of mircocode updates was incremented before validating the update. Therefore, move the sanity checking before an increment of the number of updates. Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50319 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- util/cbfstool/fit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 12a7e3b..02cfaee 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -206,6 +206,10 @@ static int parse_microcode_blob(struct cbfs_image *image, mcu_header = rom_buffer_pointer(image, current_offset); + /* Quickly sanity check a prospective microcode update. */ + if (mcu_header->total_size < sizeof(*mcu_header)) + break; + /* FIXME: Should the checksum be validated? */ mcus[num_mcus].offset = current_offset; mcus[num_mcus].size = mcu_header->total_size; @@ -215,10 +219,6 @@ static int parse_microcode_blob(struct cbfs_image *image, num_mcus++; file_length -= mcus[num_mcus].size; - /* Can't determine any more entries. */ - if (!mcu_header->total_size) - break; - /* Reached limit of FIT entries. */ if (num_mcus == *total_mcus) break;

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Patch set updated for coreboot: accb23a haswell: Update GT PM register value
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4166 -gerrit commit accb23a0b2d2f8cbf1bbc734ef11202cfe618fd6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 10 11:00:07 2013 -0700 haswell: Update GT PM register value This was changed to 0x80000000 in SA BWG 1.5.0. Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50852 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index e577fb5..f3ddbd3 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -124,7 +124,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write(0x12054, 0x0000000a); gtt_write(0x22054, 0x0000000a); - gtt_write(0x0a008, 0x10000000); + gtt_write(0x0a008, 0x80000000); gtt_write(0x0a024, 0x00000b92); /* Enable RC6 in idle */

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Patch set updated for coreboot: 211cfa6 slippy: Add EC to the device tree
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4167 -gerrit commit 211cfa6d52ba9ffbf27e4e5f9f3db754da6f1556 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 10 11:00:56 2013 -0700 slippy: Add EC to the device tree This lets the keyboard init get called properly. Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50853 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/devicetree.cb | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 5fb3cb4..665e6dc 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -84,7 +84,15 @@ chip northbridge/intel/haswell device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal

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Patch set updated for coreboot: 2d59284 wtm2: Set SerialIO I2C ports to 3.3V
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4164 -gerrit commit 2d59284f7ac6dbc684de86477de55030afc8ca38 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 7 13:28:56 2013 -0700 wtm2: Set SerialIO I2C ports to 3.3V These are both pulled up to 3.3V in the schematic. Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50356 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/wtm2/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 3193369..2790cb9 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -52,8 +52,8 @@ chip northbridge/intel/haswell register "sata_port_map" = "0x2" register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "1" # 1.8V + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V device pci 13.0 on end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI

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Patch set updated for coreboot: b0a47af haswell: Update ULT microcode to 0x10
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4165 -gerrit commit b0a47af49c86f66d8c35f01fc5e1b75c1a66e5e6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 9 07:41:58 2013 -0700 haswell: Update ULT microcode to 0x10 [ 1.503741] microcode: CPU0 sig=0x40651, pf=0x40, revision=0x10 [ 1.510483] microcode: CPU1 sig=0x40651, pf=0x40, revision=0x10 [ 1.517213] microcode: CPU2 sig=0x40651, pf=0x40, revision=0x10 [ 1.523947] microcode: CPU3 sig=0x40651, pf=0x40, revision=0x10 Change-Id: I19ef40b636eebeb8cc29cc0404abbe263ec8eaa7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50655 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- .../intel/haswell/microcode-M7240651_0000000a.h | 960 ----------------- .../intel/haswell/microcode-M7240651_00000010.h | 1088 ++++++++++++++++++++ src/cpu/intel/haswell/microcode_blob.h | 2 +- 3 files changed, 1089 insertions(+), 961 deletions(-) diff --git a/src/cpu/intel/haswell/microcode-M7240651_0000000a.h b/src/cpu/intel/haswell/microcode-M7240651_0000000a.h deleted file mode 100644 index 049c05e..0000000 --- a/src/cpu/intel/haswell/microcode-M7240651_0000000a.h +++ /dev/null @@ -1,960 +0,0 @@ - 0x00000001, 0x0000000a, 0x03212013, 0x00040651, - 0x12bee45c, 0x00000001, 0x00000072, 0x00003bd0, - 0x00003c00, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x000000a1, 0x00020001, 0x0000000a, - 0x00000001, 0x00000ee1, 0x20130321, 0x00000ee1, - 0x00000001, 0x00040651, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x47af0b7c, 0x2964a3ec, 0xe6424b34, 0x835e0b49, - 0xabadd491, 0xa663df2e, 0x0e49ca7c, 0x9ab3e97e, - 0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6, - 0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58, - 0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068, - 0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142, - 0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1, - 0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f, - 0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c, - 0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606, - 0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531, - 0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786, - 0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01, - 0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4, - 0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66, - 0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184, - 0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84, - 0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c, - 0x00000011, 0x31ff30ba, 0xc3d5b1f0, 0x26d63d8b, - 0x1a475daa, 0x1e3d271a, 0x329798a1, 0x6238f5b0, - 0x189bccba, 0x3c10d2bd, 0xe2da6fd8, 0xe71c822b, - 0x830b65b1, 0x619ab26d, 0x309d6fe9, 0x8f006761, - 0xbbe1e9b4, 0x6e0f8bae, 0x1d8982e1, 0x77986981, - 0xe7dd6cd6, 0xaa7391fb, 0x05f0cc21, 0xc482d525, - 0x3e6297e8, 0xb79fbca9, 0x7dd8ad2f, 0xcb0d2e71, - 0xcd28bedc, 0x0fe7d86d, 0x19451c3f, 0x527f2ea1, - 0x228bbfa5, 0x7762e609, 0xa1d39924, 0x57c28377, - 0x1a6f3509, 0x19cc4843, 0x66500238, 0x2470790e, - 0x9d0137e1, 0x6c0007d9, 0xaad1617b, 0x6998e698, - 0x22ec3171, 0xae886d57, 0x984186b9, 0x543792a0, - 0x312195d8, 0x63002239, 0xb42e73f6, 0xb6d26b79, - 0xc92b35fe, 0x6f54809a, 0xd62a2973, 0xd11bc5b3, - 0x55835450, 0x5e3c833a, 0x5f1ea6d4, 0x1ce2c3bc, - 0x9a6a73c3, 0xf4d2900a, 0xbc65b0c4, 0x28f6a545, - 0x383244cc, 0x32028823, 0xcb5e7879, 0x707d3b8c, - 0xbf8ab8ab, 0x99b6f113, 0x84c09d2d, 0xd0d46fcc, - 0x3afcbbb9, 0xf2e051d3, 0x19f50c02, 0xa8faa217, - 0x61f7522f, 0x2441ffd3, 0xa52db34d, 0x0a7dc774, - 0xb3f9728c, 0xa63050d5, 0xcb600bfd, 0x14159964, - 0x7f496dad, 0x1f6bd98e, 0xd85d1e44, 0x2af93f92, - 0x32f0f994, 0x357d2eb0, 0x7f258421, 0xfa3492da, - 0xefad2c7f, 0x6079dbea, 0xf7d162cd, 0x775bddc8, - 0x0ec06cd4, 0x71cd0a9b, 0x86a8a4f8, 0xc9725975, - 0x95016702, 0x5663c9e3, 0x6fc78f43, 0x323ac7e3, - 0x9ee9f629, 0xbb770538, 0x5f59cfe3, 0xfd22f52d, - 0xce10cb8f, 0xf6a0a49c, 0xf634bd00, 0xc6389b21, - 0xbc9a60c3, 0x105ae61c, 0x66e8f0de, 0x9e31465a, - 0xd9d48a35, 0x16f85330, 0x25985beb, 0x3f5ba1fb, - 0x7ee1ab5a, 0xcf87b754, 0xef7df38d, 0x7f21dcd3, - 0xff7d4a56, 0xfec9959c, 0x0195b65b, 0xaa8ac780, - 0x68265903, 0xe6ea2346, 0xb3383bd1, 0x714dd6f7, - 0x054f682d, 0x7d0a8e1a, 0x7aa60080, 0x138e54aa, - 0xfb9416fc, 0x0ded0711, 0xb537341e, 0x3fd6db0c, - 0x68384bd6, 0x961de7c5, 0x1355b8dd, 0x5322dfdb, - 0xdf16e732, 0x2f0289f2, 0x06b8c359, 0xefe029ba, - 0x2fd14d40, 0x564c7d88, 0xcddec76e, 0xac5bb338, - 0x5c297fab, 0xd64f7885, 0xbbd7e65d, 0xf2ef2f68, - 0x20ec9206, 0x418872bf, 0xdc0c1735, 0x2a282e20, - 0xa9642a08, 0xb8517a66, 0xf000c64d, 0x759e3e23, - 0x9fa3ac4e, 0x8145ed5f, 0x948a6d14, 0x73c92a4c, - 0x13149383, 0xc8f2dcbd, 0xb170fe20, 0xe0e1099b, - 0xa2cf5532, 0x2e910426, 0x84ec9075, 0x3a6a7f93, - 0x2b817e9b, 0xf9af4123, 0x629b88d4, 0xdd7f990c, - 0x063d2eab, 0x28d93fd2, 0xce5f551f, 0x3e204b75, - 0xb6cf5418, 0xd4a79e5a, 0x505e47cc, 0xc87e880b, - 0xabb24da4, 0xc441cf07, 0xd53d7ad6, 0x99d42cda, - 0x1692efd2, 0x92ad85c2, 0xcc7328f0, 0x900c8994, - 0x42e796a6, 0x1fb27a53, 0x058cd37f, 0xe916e200, - 0x5030b053, 0x2885143e, 0xb5ecaf1a, 0x30b55619, - 0xe73a143b, 0x236040d2, 0x945fe27e, 0x826b6cf9, - 0x4bed8166, 0x3ea8f35d, 0x9db96431, 0x9e8e5095, - 0x3bacb781, 0x8101001e, 0x24f8e703, 0x51b69763, - 0xa0495f4a, 0x66c69d36, 0x888f0ea0, 0xd1a01cb6, - 0xc84fdad0, 0xdb9579c5, 0xd479960f, 0x2db0411a, - 0x0a8db51c, 0x0e18a639, 0xa2b5108a, 0x278d1489, - 0x9d0683e2, 0x9cbaab97, 0xb21d16c7, 0xf689a585, - 0xa3a2c1ff, 0x617e39d2, 0x81c3250f, 0x6fd8feb8, - 0x70362986, 0x9089a0ba, 0xdf46cb8e, 0xc4d3b446, - 0x5bab3e95, 0xbc335380, 0x1fbe3c37, 0x2c30323d, - 0x84c1b518, 0x608fd852, 0xdbcf9228, 0xc4763124, - 0x22ad59b8, 0x809c5d8d, 0x22a52317, 0xa51f2336, - 0x9d1fa64c, 0xd89742dc, 0x4cf8f40e, 0x8dab938d, - 0xa1307678, 0x8f550815, 0xd3064c28, 0x474e3828, - 0xf74637db, 0xac29c2c0, 0x32bb34e1, 0xfc01f62e, - 0xb39a3b9b, 0x011bdcfd, 0x3e68cdfa, 0x5edd8d37, - 0xc0c1b4b7, 0x7e3ba31c, 0x64024ab0, 0x42c4df53, - 0xa7ebcbd7, 0xcac6dfee, 0xe32e2c29, 0x5684de30, - 0xb09e3874, 0x8ebf6a1d, 0xe0d165ec, 0xee1189c3, - 0x2dc2e02e, 0x91fea612, 0xdd641942, 0x1b7fc91d, - 0x22f7f5db, 0x24b37552, 0xcbe1bfa4, 0x85598c2c, - 0x398d1cfd, 0x94a5d0cd, 0xf20885b6, 0xe43a0b0c, - 0x74f0b815, 0x605f0456, 0x764d55b0, 0xc7bdf689, - 0x93d790bf, 0xf1f46098, 0xe96980e9, 0x13d78278, - 0x209a2123, 0x3f283c0b, 0xc563137f, 0x5302e0f9, - 0x7b87216e, 0x97bd2c40, 0x2e57af27, 0xb09d5bd7, - 0x232f59ad, 0x6b7a45c5, 0xeb52f5f7, 0xf4a81384, - 0x989092ff, 0xa2a91f59, 0x8f5315e7, 0x6e6f17a3, - 0xd703daf4, 0x31c98f50, 0xb8782772, 0xfb733c7f, - 0x7a4b1d63, 0xcdc6612a, 0x7f14abc9, 0x8cb812a1, - 0xb7bf80ef, 0x8400f51d, 0x9e4854c7, 0xa0bf564d, - 0x8b3e63a7, 0xbc106c5c, 0x6b637e45, 0xa458517d, - 0x265412c5, 0xb8c1145d, 0xb4c95511, 0x0e805220, - 0x2c3e4b00, 0x73548045, 0x08f1e967, 0x4bc4417c, - 0x5d14e816, 0x629e4816, 0x1939cce4, 0x2ca82f2f, - 0xdc21646e, 0xd10e6753, 0x9ef4c728, 0xaaab8be8, - 0x8840cee7, 0x939f9f9d, 0x9da9be7a, 0xe75f2cda, - 0x63e95c18, 0xc9b3f765, 0xc6b3851c, 0x297c7e6f, - 0x59db8f20, 0x2fc54ab1, 0x3f0ad7f2, 0x88972fcc, - 0x871f18be, 0xa446eb0b, 0x1f76deec, 0x8effbf69, - 0xe84c049b, 0xd800c1a2, 0x8a88b9f8, 0x3a3e07c4, - 0xf4863b24, 0x0607f5ca, 0x6dc0fdd7, 0xe7f21cab, - 0xadc15f47, 0x2c4a07a1, 0x481c9e6f, 0x6888ae69, - 0x49287c75, 0xf8e8cfe1, 0xe5bf499b, 0x6bbcd67b, - 0x647f5c17, 0xc3dbaa4a, 0xc526b197, 0xcb8b871f, - 0x8c6c33a8, 0x0ce3aa88, 0xce763e1f, 0x0b843402, - 0xb608ce54, 0xfb952446, 0x97a43b5e, 0x6f991733, - 0x428974c8, 0xff378fdd, 0x1680202b, 0x074ab0fd, - 0x1a5428c1, 0x4189678a, 0x5fff2311, 0x92259629, - 0xe8cc7f30, 0x12b9a2e3, 0xa44ddb3e, 0xaf68af87, - 0xa8777e13, 0x244ba6c6, 0xd7974e62, 0x0d2c2e12, - 0xf0d18342, 0x83564ba2, 0xfb24a914, 0x0e9a5e9e, - 0x46e23900, 0xbb7fd47a, 0xca8b6796, 0x879e5da4, - 0xb036c2aa, 0x40a7268a, 0x717b91c5, 0x9eabea1d, - 0x5882317c, 0x732f05b8, 0x4ddd046d, 0x8750fcc6, - 0xda00c46f, 0xb213414c, 0x089f592e, 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0x9bd2c14d, - 0x386486a9, 0x340aa4af, 0x6d1608fe, 0x33b3c0bd, - 0xa2060183, 0x74e5b262, 0xdf289ae1, 0x442b27a4, - 0x4ba6bc5f, 0x295d3c4b, 0x6445cdc1, 0xdc3d9088, - 0x48b91d97, 0x487da4c8, 0x46302671, 0xb7c27b54, - 0xf5817486, 0xdcced9cd, 0x87c86846, 0xf4f8dd92, - 0xb0b5fa9b, 0x39d7464d, 0x2191274a, 0x045f90dd, - 0x8316dca8, 0x83d0f38c, 0xcde29fee, 0x5c3d07f2, - 0x0954b4a2, 0x062abbd6, 0x5d7f6735, 0x116e2063, - 0x7d03cc23, 0xa3442eea, 0x7dc5a137, 0xc51f863d, - 0x6b3d02c8, 0x8d2daac6, 0xf60340f4, 0xc0321916, - 0xdbed275d, 0xae643c46, 0xfa496afd, 0x18cc85ae, - 0x73fac832, 0x07f1ea3e, 0x7c620f90, 0x581c4d3a, - 0x23241dde, 0xb7feaec5, 0xb8f0f50b, 0x5489c787, - 0xc073afc3, 0x2d41f4a3, 0x25fc5f97, 0xa32851be, - 0xb45083fa, 0x2c1c6c0a, 0x13e19846, 0x7f02b7ca, - 0xe7f9bd3b, 0xf9979b78, 0x896dc7fe, 0xcda3c3a7, - 0x58120222, 0x496057be, 0x93e3e7d7, 0x04806522, - 0x0ab7545c, 0x7f54bd38, 0x1e4fb118, 0xd724c76f, - 0x312242bf, 0xb90a1bb5, 0x6264627d, 0x7b3d161f, - 0xf73ef007, 0xb471882e, 0x5dadc64b, 0x77fcbe3c, - 0xa8021f2e, 0x8068e61c, 0x33523e1f, 0xe25885f1, - 0x68bf0bf1, 0xfa968b34, 0xeda184a3, 0x9299e0d6, - 0xa83d2ea9, 0x79539361, 0x6789226b, 0x37ae25d6, - 0x9c194e51, 0xb0d63710, 0xc30a1354, 0x26a984fe, - 0xd676f842, 0xe4c124e3, 0xee61be90, 0x7dc1fde6, - 0x41d023cd, 0x5c51d3ee, 0x7ae9bd9c, 0x026289d2, - 0xdabc7bd7, 0xff2b602b, 0xbed2eeb8, 0x87afbbc6, - 0x3bbb3c62, 0xc9905794, 0x201bdc97, 0xf00b2e98, - 0x477b6eb4, 0xb22321c6, 0x1eeeb19d, 0x3bb9a91b, - 0x80e2af06, 0x4cdaca06, 0x3e324fa2, 0xc90470db, - 0x6a3ce0f5, 0x048b7611, 0x86b30b35, 0x7c5dd969, - 0x44c182d0, 0x594634b4, 0x892db294, 0xbaeac844, - 0x946c405a, 0x705c5ce2, 0x90f395d7, 0x5a3f9e27, - 0x847f244f, 0x5ba47023, 0x8e92f748, 0xac78cdc0, - 0x3c5bbb38, 0xcb350205, 0x6cfc6707, 0xbe97aa3a, - 0x51120bf0, 0x0adc2aad, 0x0c4f56d4, 0x40c9861f, - 0x832f01ce, 0xfc8358a2, 0xe16df7ac, 0xeb1f1be9, - 0xe9915e9b, 0xa2d15e27, 0x8c482491, 0x5f25305d, - 0x07960ecb, 0xbb1e25bd, 0x90b61527, 0x24773593, - 0x39a732ac, 0x640c6a2e, 0xe43804d5, 0xa1fb65f4, - 0x38eb7068, 0x60000dad, 0xfe7cf4fb, 0x8d3b167f, - 0x91048c86, 0x758d03e8, 0xab104a32, 0xe9bc4cc4, - 0x67633d64, 0xcd246f40, 0x9e3975d4, 0x137a24dd, - 0xb97095fe, 0xa84685bf, 0xfa61761c, 0x0ba8ec11, - 0x0c568558, 0x72b953e8, 0xd9dbabf2, 0x4e42d1cd, - 0x0513ee90, 0x3c6786ef, 0xe5655a3e, 0xadfac1a3, diff --git a/src/cpu/intel/haswell/microcode-M7240651_00000010.h b/src/cpu/intel/haswell/microcode-M7240651_00000010.h new file mode 100644 index 0000000..e998261 --- /dev/null +++ b/src/cpu/intel/haswell/microcode-M7240651_00000010.h @@ -0,0 +1,1088 @@ + 0x00000001, 0x00000010, 0x05032013, 0x00040651, + 0x7e5d135d, 0x00000001, 0x00000072, 0x000043d0, + 0x00004400, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000000a1, 0x00020001, 0x00000010, + 0x00000001, 0x00001021, 0x20130503, 0x00001021, + 0x00000001, 0x00040651, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xfac3eb8d, 0x8cd6473b, 0xf8ca6c8e, 0x8005bb0b, + 0x34542635, 0xa1688336, 0x22d6f123, 0x6eb6491e, + 0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6, + 0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58, + 0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068, + 0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142, + 0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1, + 0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f, + 0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c, + 0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606, + 0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531, + 0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786, + 0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01, + 0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4, + 0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66, + 0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184, + 0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84, + 0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c, + 0x00000011, 0xf44406de, 0xd4f673d1, 0x8867b7c6, + 0xa6a39e76, 0xae2b3d65, 0x2bead941, 0x09d1d430, + 0x509c6fb9, 0xeaf065bf, 0x4e0909b7, 0x1f922a18, + 0x7827ff5e, 0x327dfd17, 0xe6427089, 0xabe4e1ae, + 0x85ff69c5, 0x6bd1415b, 0x9fb489c3, 0x00d66135, + 0x8ea9b59e, 0x67dfcd5c, 0x22abb1d5, 0x6b7ed0e7, + 0x92c87fcd, 0xd264d016, 0xf680381d, 0x118e542d, + 0xa9bba426, 0x07841789, 0x3a905400, 0x432af9a1, + 0x2e336c44, 0xb7904fd5, 0x319962b4, 0xada8dac1, + 0x5b9f9402, 0x472887a6, 0x9d0d486c, 0xd820b94e, + 0x7870e4f2, 0x1adf9dc5, 0x9fae1107, 0x02810bde, + 0xb405bd25, 0x91a2fc94, 0x442a84e1, 0x4e193284, + 0x2d4fb10e, 0xc6755c8f, 0xae3ac652, 0x570424da, + 0xa7c7e544, 0x843c14f6, 0xc2288388, 0x0a0a7e6b, + 0x3024341b, 0x5bb013fe, 0xc355fe2a, 0xfee46bc1, + 0x6f7d66c2, 0x6b9391cf, 0x209ec795, 0xa2c18e0d, + 0x94ed84d0, 0x50ada06d, 0xca846e8d, 0x5e37006c, + 0x3c9db1a4, 0xb01ab009, 0xdcdf3887, 0x461773c3, + 0xb7a48d2c, 0x3f08bb2a, 0xe95c2486, 0xc306bb1e, + 0x6da18430, 0x1c45aeec, 0x64f8bab3, 0x2262c8a6, + 0xd0155c5f, 0xe48736e4, 0x7653fffa, 0x18a714c5, + 0x8de87c8d, 0x29630439, 0x6722ea06, 0xf913592f, + 0x9d4b1f6a, 0x7b63f983, 0x4289dc2b, 0x3de11454, + 0x263d0e10, 0xa63b4b9e, 0x8a437048, 0x013164e0, + 0x05ed14fb, 0x578bc61a, 0x203fcba5, 0x52670d38, + 0xe1e6007b, 0x7c4c60fa, 0xec76abdf, 0x7fe3494f, + 0xe4337ce2, 0x3a9796d2, 0xa14ea306, 0x1142406b, + 0x4009d6a9, 0x1669bf98, 0x448eba47, 0xc777694e, + 0x59a695fb, 0x88255292, 0x40f11a66, 0x6aa9bccf, + 0xbe111528, 0x7d60a177, 0xde79a0da, 0x293faa13, + 0x46f507e8, 0x956cbe42, 0xbe842a10, 0x8d44faba, + 0x6ec3ea06, 0x85a776e3, 0xb6c111f0, 0x6e3eea68, + 0x7d66c12b, 0x66986856, 0x736d38ed, 0x0d20520c, + 0xa4738956, 0xd7b6f1d8, 0x6448b4d2, 0xa88f8aa9, + 0x597aec28, 0x53fb89e1, 0xde013bfb, 0xeb1fae1e, + 0x5bd49201, 0xeebce9a6, 0x5d6cf878, 0xb457319e, + 0x7a7f12d9, 0x3a6b33e8, 0x2c85648e, 0xc03a76ea, + 0x88b4a8f2, 0xaa176afa, 0x868ad8da, 0x6018cdae, + 0x958632ce, 0x085ac680, 0x3a49b2ef, 0x5f4898de, + 0x1bc05783, 0xa64c3d83, 0x79ec3e95, 0x5fe3153d, + 0x3570c98c, 0x4e00551d, 0x06693d69, 0x78cae658, + 0x0b6c7e0f, 0x7aba769a, 0x7fb01e3b, 0x4fda89b1, + 0xd896b9aa, 0x35ee444b, 0x0b3ef86c, 0xeff58968, + 0xb8c0241b, 0x3c4c56ee, 0xb884ad0a, 0x7ac6804a, + 0xb1dba29b, 0x8b6e4fd3, 0x928bca05, 0x13bb2a61, + 0xb34046cf, 0xa7b6988c, 0x078bf1aa, 0x42b9b199, + 0x7e558f71, 0x6e0cffe1, 0x7b445e5f, 0x12f3e96d, + 0x0a33beaf, 0x4aa7fa8c, 0x5b78a8f3, 0x80fffec3, + 0x57584e26, 0x36e3f734, 0xd80eaecb, 0xeea1887f, + 0xe7195c6d, 0x359ccc51, 0x2520f5bc, 0x5775ee1d, + 0x2bdd2077, 0xe8d2f7ee, 0x03e42fc6, 0x469a87c7, + 0xedd7eb27, 0x35fb23cd, 0x868d2ed4, 0x96babe01, + 0x96579e43, 0x3fce8a8f, 0xfbac7ff3, 0x0d7444f2, + 0xdb38ab25, 0xd3cad07b, 0x962bd1e5, 0x4b068727, + 0x1520a2fb, 0x72f6a856, 0x42bf8740, 0x7bf3e0f3, + 0x67d21367, 0xe6dd6e11, 0x822ef472, 0x177f2120, + 0xd040362d, 0xe5720ea9, 0x181b033e, 0x6ea2cd5c, + 0xd30ea38e, 0xa6b99475, 0x9b7a5b64, 0x7a316a72, + 0xc1443f24, 0x5ca76eb9, 0xde4c10ad, 0x0b522e4c, + 0x5ec202c3, 0x534eb6b3, 0xd2a45fb8, 0x87e75279, + 0xc1a0abcc, 0x68ee85e9, 0x1d861961, 0x6e76a6d2, + 0x8a0a9ab8, 0x950e441d, 0xe8a4d848, 0x2656f7ca, + 0x407a4093, 0x2f562edf, 0x19285481, 0x57a11a38, + 0xf5901687, 0x47a21b09, 0xa9ba7c98, 0xe5b5bca2, + 0xc8237ff5, 0x866c213b, 0x0f630f4b, 0x523ec8f2, + 0x3a1d8484, 0x3199a09d, 0xb18339eb, 0x5ba58aa4, + 0x07776fe1, 0x5ec026c8, 0x9fcb3a82, 0x3fd2f682, + 0x067f39db, 0x5cdb66dc, 0xca05f443, 0xe594f996, + 0x61efe60e, 0x335f69f5, 0xeafbf8c2, 0x1883288e, + 0x2bff3117, 0x2b990599, 0x89cef32b, 0x4b405835, + 0xabbc034b, 0xcc350e3e, 0x3bcd378c, 0xd0d7c360, + 0xbd33c535, 0x1cca3184, 0xcc5051e5, 0x9eb74f55, + 0x4887d797, 0xefab3ad8, 0x5079f727, 0xfbf90492, + 0xed51c9d1, 0xae943db3, 0x4e769e0e, 0x6dca3cf6, + 0x5307818f, 0x1702583d, 0xfc4b1355, 0xe4062241, + 0x58d615b7, 0x1ddf793c, 0x07e3fd37, 0xfc94ca17, + 0xc7e41bb9, 0xff76183c, 0x12bc86c0, 0x3946809a, + 0x02e67447, 0x47a3af64, 0xab324f6c, 0xdb16de82, + 0x1f712783, 0xb46b0e25, 0x2bf35553, 0x9a123bea, + 0x781ff27b, 0xf89d1139, 0x3e13204c, 0xb9a85a70, + 0xc9aefb8b, 0x4e977a3a, 0xf414c01f, 0x10415abb, + 0x01398287, 0xcdd25798, 0xdc862ec9, 0x5094b572, + 0xbf6c7a46, 0x53226477, 0x3b597075, 0x4ff6312f, + 0xa69605ed, 0xc3c7d159, 0x598e20ff, 0xa4724ea9, + 0xab67f174, 0xe323f851, 0x0dfc777c, 0xeea1a484, + 0x51e5b7c3, 0x8ff82883, 0x679cd643, 0x8a7acb85, + 0x5c926608, 0x2fd786a1, 0x55f9f608, 0xb657fcc7, + 0xede1bc11, 0x56e35ab9, 0x4c260bc6, 0x46a268c2, + 0x72d48246, 0xf0238f58, 0x94f65b24, 0x7e1e8adf, + 0x3d17d62b, 0x6f073880, 0x1e591eaa, 0x2d7836f9, + 0xce79111d, 0x42a59259, 0xb11d23f9, 0xb63bd627, + 0x57215282, 0x4f7b143e, 0x90a81fea, 0x8b4ffb1c, + 0x2281a57f, 0x98c77eb3, 0xcd4363c5, 0x95186aec, + 0x7b291ead, 0x4b4df803, 0x2196f196, 0xab00bfa4, + 0x123e2fca, 0xd67d4f5a, 0x38b5a23a, 0x4c2bca91, + 0xed26ff25, 0xc8781e41, 0x89f62c38, 0x6cad9ae1, + 0x1313ce8f, 0x46adf5ad, 0x9566c74c, 0x2356d665, + 0xc6eac3d9, 0x15ea873f, 0xabd5ff23, 0xc85180ca, + 0x658495c5, 0x7c7ae0bc, 0xea91daba, 0xffceeb3c, + 0x2172ae51, 0x23bf367a, 0x89dc4ad3, 0x2a6eafac, + 0x377ccfdd, 0xcc3bbcca, 0x10bec9a1, 0x762c02dc, + 0x50ba7ca8, 0x838fae38, 0x82b2a075, 0x8e12549e, + 0xa5d6b730, 0xa8d5ab8a, 0x71439e7b, 0xeb47aee9, + 0x9ec38e95, 0x970ffe14, 0x7d0f9b43, 0x7b205bca, + 0xb3973a4d, 0x992c2118, 0xc2ae2f7c, 0x807ea282, + 0xe22ca42b, 0xb88640df, 0x55ac361f, 0x3f378c73, + 0x6c7bab3a, 0xbd018af7, 0xff3feaf0, 0x1db365b1, + 0x7867f4b8, 0x10ae055a, 0xe8a55089, 0x98571e5b, + 0x19e42d84, 0x831adec7, 0xf881b74e, 0xaf863f8b, + 0x54aa0425, 0xca2eb910, 0x4cbe0b46, 0x4c893bbf, + 0xe165305a, 0xbe516e31, 0xdc4b03d1, 0xddb7f11c, + 0x7ecb42bd, 0x05a16aa0, 0x86ce053d, 0xbe7e3f81, + 0x3cac8851, 0xe4a6d3c8, 0xfa846009, 0xc0ae8b5b, + 0xc827985a, 0x5b96373a, 0x8b421603, 0xfddc44c7, + 0x27dc254b, 0x8ea6a7a5, 0x947012b5, 0xee6159a4, + 0x758554cc, 0x990a9274, 0x84f41e1c, 0xa9dac689, + 0x269854f3, 0xae0f7747, 0xd8f01eed, 0x6a9fc6e0, + 0x8402791d, 0xde28efdc, 0x91e4ee62, 0x407979a3, + 0xbb0b3f2d, 0x9093992f, 0xbd6fd98c, 0xf0ce2f34, + 0x47f981c9, 0x7de9a106, 0xd70d7490, 0xdce6115e, + 0xded19278, 0x9542c7a3, 0xf178e1d5, 0x02afd027, + 0xa0d96f41, 0x393b82e1, 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0xf1a577c2, 0xc5307e3f, + 0x987d053c, 0xcca5a200, 0x37a548a2, 0x93c13034, + 0xa1fefdfb, 0x4866eb81, 0x025418ba, 0x9719a226, + 0x80a9ee66, 0x76d36553, 0xbf6d6081, 0xa94bccaa, + 0x6bfb6212, 0xe6c7ee59, 0x3ab204e7, 0xc22bcaed, + 0x005bbb7e, 0xa78e2a50, 0x5cb4de80, 0xaa9253e2, + 0x5e735f57, 0xa9222d9a, 0x32636b3d, 0xc686a7e8, + 0x2ed25902, 0xbf1d4503, 0xa4e4bc1b, 0x1bd7c9cf, + 0x401e01a3, 0x5085e061, 0xf0e614b0, 0x9717fb08, + 0x6a499ee0, 0xc46fe080, 0xd30b1633, 0x04b26bb6, + 0xfe2daf45, 0x425293ab, 0x06ea5fef, 0xe3b85183, + 0x6f7aa049, 0x0006e1ee, 0x8ad85435, 0x8d29365a, + 0xc91d3722, 0x3715a751, 0x46ff4f8a, 0xed799bec, + 0x76fe8f37, 0x386717e3, 0x12bcd65d, 0xb7ae8f11, + 0x0dc91d7b, 0xbac9ff1f, 0x10e5c01f, 0xbf7504f9, + 0xff56bdce, 0x1f816db1, 0x662ad369, 0xd7c214e1, + 0xf5b661fd, 0xe44309ce, 0xc88a6463, 0x7322a58f, + 0xf9d2c21d, 0x79bc351c, 0x116f9905, 0x0b432350, + 0x7b61d0cd, 0xb0a98222, 0x664d412e, 0x9c41ead0, + 0x01daadbf, 0x48767a64, 0x1d26fb8a, 0x466fa719, + 0xc10eabae, 0x52cd59e5, 0xfe8d3f3b, 0xc53c30e3, + 0x510b4840, 0x789e3a7c, 0x4260cf04, 0x3f8b32a5, + 0x4d32ec2e, 0x6beca3e8, 0xb26d7d57, 0xb710d6e8, + 0x7ce08965, 0x0fe95d60, 0x9c0efca5, 0x483ccc9a, + 0x7d011018, 0xef35331c, 0x9e89519a, 0x6504120e, + 0x544fd401, 0xe83084e1, 0xc89b0eef, 0xc083de5a, + 0x6d90d6dd, 0x21ecd7fc, 0x87393dd1, 0x1c6bf2eb, + 0xa257b927, 0x7a630ecf, 0xd699a6f2, 0xc9ecf12a, + 0x32883a67, 0x2e91a53c, 0x1701735b, 0xdd56da35, + 0xac6d369e, 0x26c68338, 0x8d48f825, 0xa9a173c6, + 0x37bc76b6, 0x85e42535, 0x5ca0906a, 0x5be19560, + 0x943b07ce, 0xaee19b3a, 0xfaef8515, 0x8ea1567a, + 0x2aaf74a2, 0x9117dc91, 0x4fa0349e, 0xb211a216, + 0xf102afdf, 0xcc7ae3e5, 0x90efd550, 0x7f96afc0, + 0xb7df5202, 0x10c295f4, 0xe94b4f37, 0x2ae29094, + 0x11ded085, 0xc6135b38, 0x56cabe7e, 0xb87154fd, + 0xd649ba32, 0x556a2ea3, 0xd6ce1e53, 0x9cf2dda9, + 0x08e2410a, 0x0ab6dc31, 0xffa9d676, 0xcf723c60, + 0x0d3b274d, 0x00cc92a8, 0xd1c179f2, 0x43791de7, + 0x3ee8ceb5, 0x8f42bbbc, 0x656067cd, 0x099ffdbb, + 0x454d8a5c, 0x885658ba, 0x6bd69927, 0x6826567b, + 0x4e25c6c7, 0xdbbc01e9, 0x9243a437, 0xfa8d5042, + 0xc36a48d2, 0x645b0f8d, 0x10410c33, 0x06b8e8ab, + 0x30d2cc99, 0x71e45545, 0x58c48f2a, 0x2526632b, + 0x02d124c0, 0x10539bb0, 0x419213db, 0x00ec51d7, + 0x83b37d14, 0xdff87d88, 0xe654c355, 0xc4f66635, + 0x05639fec, 0x4ede13e5, 0xa1ae80fc, 0x3f53d61c, + 0x1b713fb1, 0x6ebccb56, 0x52366ca0, 0x0e90266e, + 0x54a386b4, 0x4d6857e4, 0x3cf659b9, 0xc942deac, + 0x1aa4082e, 0x22999206, 0xf78eeaa6, 0x7700d674, + 0x84cc0502, 0x6c4fd82a, 0x5f4f2dac, 0x7f2af527, + 0x9c8136f3, 0x697d4dfb, 0xd146b220, 0xb9a3bbd5, + 0x09e1934f, 0xa634d073, 0x9f1bf326, 0xee96b1ff, + 0x9f79e9f1, 0x21f48536, 0xb9ae6d43, 0xff461c4a, + 0x8312bfb5, 0x2639fcae, 0x59065083, 0xf375b9ca, + 0x69ce7032, 0xe8659a93, 0x10537734, 0x405384a8, + 0x38f47ce4, 0x7f8cfcd7, 0x0c14877d, 0x9ef97b45, + 0x601cd232, 0x8bda652a, 0x2fa1ec4e, 0xb1db4711, + 0x6ca9b4d8, 0x2a91bd7e, 0x66b7a06a, 0x89b82ecd, + 0xa9a7fcb1, 0x76d0ac42, 0xc6b29c93, 0xd3fd21e4, + 0x1a913bf6, 0xe4a75151, 0x0a9e1815, 0x1d94d30e, + 0xc2997458, 0x3927b0b3, 0x8c54b135, 0x1e9ac875, + 0xf55f0591, 0xbf7784b0, 0x1c340143, 0x747cffff, + 0x61409356, 0xa0182ce1, 0x00471651, 0x89634688, + 0x9eacbacb, 0xecdeb43a, 0xf2d3cad8, 0xa904a91c, + 0x532b91d1, 0x094f742c, 0x2fa8f9c2, 0x6c33778c, + 0x61f714e0, 0x946baf6a, 0x7eb01ba3, 0xb5ca27e7, + 0x3754da42, 0xde0c9aec, 0xb194f021, 0x74c60aa5, + 0xf71f9bd4, 0x3f68b030, 0x397374c9, 0x40b427ad, + 0x3a266ab5, 0x635ccfec, 0x50ff90e0, 0xaebfcc6a, + 0x114daa80, 0xa886b093, 0xb68a8bda, 0xef044b92, + 0x388c43ee, 0x4c6a5072, 0x18bf9a95, 0xdb012f74, + 0xbf54d90d, 0xfc10a74f, 0x282d8d84, 0x1f38a7d5, + 0xeee32769, 0xbbe19fba, 0xb6c9f05b, 0x93604caf, + 0xe2852ec7, 0xd5b77484, 0x6e16b9f1, 0x25c4676b, + 0x18eb2550, 0xa15deb0b, 0x6ba10164, 0xf7a1d465, + 0x40f4bc5f, 0x88f3875b, 0x82ec0bc0, 0x69a336ca, + 0xa7a7bb3f, 0x9ffac33c, 0xfb076ba4, 0xe0d6a91d, + 0xf8347f89, 0x80f785bb, 0x5d68daad, 0xfdb04d08, + 0x723484fe, 0xeaf094c9, 0x52caeaa9, 0xd8011d30, + 0x5589b102, 0xc5377ef7, 0x9a21aad2, 0x93e42c36, + 0x0690c016, 0xc543876a, 0xdcdce391, 0x4d1b0c29, + 0x5887ddfa, 0xef87728c, 0x831c9993, 0xe7587200, + 0x7f58234d, 0x918dae28, 0xb18f1f26, 0xcb6148ea, + 0x652e6ddf, 0x20c733d7, 0x4a07192d, 0xfa225190, + 0x837dcb03, 0x9ed4b101, 0x1f128320, 0x27ff198d, + 0xea717591, 0xc12bf3d6, 0x8a24ebe7, 0xc40c8fb9, + 0xd4e13b77, 0x1f785902, 0x3b13db87, 0xe806ba14, + 0x0238f8f4, 0x190df9ef, 0x66f58fe8, 0x2f121a64, + 0x12f9b9ec, 0xf737a7f3, 0x73a7053a, 0x5abe1ed6, + 0x4fd2fbea, 0x0f6054b1, 0xdc8e8cb1, 0x7ebd943d, + 0x96567db8, 0x4d43647e, 0x54520aa0, 0x254b6fb1, + 0xa1de03b1, 0x9aaa8ba7, 0x16a4533b, 0x7f516dad, + 0x8a267a2d, 0x0f6943dc, 0xf4550373, 0x3c9ef4fe, + 0x1ca3e9a4, 0xb19b9b21, 0xe34ea1bb, 0x19ce640c, + 0xa8abc273, 0xd3501a07, 0xc327c8b5, 0x8ac46f52, + 0xf1e4205f, 0xc832c30e, 0x96789c05, 0x29c28023, + 0x3fa4c83a, 0xc2cdb971, 0xa81fcdcc, 0xbc8512f7, + 0xeb1fcc49, 0x267ef1cb, 0xf30c0997, 0xb1f6ecea, + 0x61a8f656, 0x80446b3b, 0xaa5cafb8, 0xf453a030, diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index 5b4f74a..c03a468 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -19,7 +19,7 @@ #if CONFIG_INTEL_LYNXPOINT_LP #include "microcode-M7240650_ffff000a.h" -#include "microcode-M7240651_0000000a.h" +#include "microcode-M7240651_00000010.h" #else #include "microcode-M32306c1_ffff000d.h" #include "microcode-M32306c2_ffff0003.h"

1 0

Patch set updated for coreboot: 3510a04 peppy: Initial mainboard commit
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4200 -gerrit commit 3510a044749d989503f373c873012725651b4084 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu May 23 15:13:46 2013 -0700 peppy: Initial mainboard commit Taken directly from slippy with only constant + string changes. (Peppy port of I4172460d3b075bfd5bb22013a6225cf0e8f95b9c by dlaurie) The following changes are required in a subsequent commit: - Add Elpida SPD data. - Update GPIO map. - Remove iSSD power sequencing. - Update USB port map. Change-Id: I01dfb841f0e9186cf8a0a23f72e7be986a83be42 Reviewed-on: https://gerrit.chromium.org/gerrit/56513 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Dave Parker <dparker(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- configs/config.peppy | 34 +++ payloads/libpayload/configs/config.peppy | 71 +++++ src/mainboard/google/Kconfig | 3 + .../google/peppy/Hynix_HMT425S6AFR6A.spd.hex | 17 ++ src/mainboard/google/peppy/Kconfig | 51 ++++ src/mainboard/google/peppy/Makefile.inc | 47 ++++ .../google/peppy/Micron_4KTF25664HZ.spd.hex | 17 ++ src/mainboard/google/peppy/acpi/chromeos.asl | 24 ++ src/mainboard/google/peppy/acpi/ec.asl | 24 ++ .../google/peppy/acpi/haswell_pci_irqs.asl | 83 ++++++ src/mainboard/google/peppy/acpi/mainboard.asl | 38 +++ src/mainboard/google/peppy/acpi/platform.asl | 86 ++++++ src/mainboard/google/peppy/acpi/superio.asl | 29 ++ src/mainboard/google/peppy/acpi/thermal.asl | 173 ++++++++++++ src/mainboard/google/peppy/acpi/video.asl | 43 +++ src/mainboard/google/peppy/acpi_tables.c | 292 +++++++++++++++++++++ src/mainboard/google/peppy/chromeos.c | 114 ++++++++ src/mainboard/google/peppy/cmos.layout | 139 ++++++++++ src/mainboard/google/peppy/devicetree.cb | 106 ++++++++ src/mainboard/google/peppy/dsdt.asl | 62 +++++ src/mainboard/google/peppy/ec.c | 52 ++++ src/mainboard/google/peppy/ec.h | 62 +++++ src/mainboard/google/peppy/fadt.c | 156 +++++++++++ src/mainboard/google/peppy/gpio.h | 124 +++++++++ src/mainboard/google/peppy/hda_verb.h | 99 +++++++ src/mainboard/google/peppy/mainboard.c | 164 ++++++++++++ src/mainboard/google/peppy/romstage.c | 196 ++++++++++++++ src/mainboard/google/peppy/smihandler.c | 156 +++++++++++ src/mainboard/google/peppy/thermal.h | 43 +++ 29 files changed, 2505 insertions(+) diff --git a/configs/config.peppy b/configs/config.peppy new file mode 100644 index 0000000..0eb5f00 --- /dev/null +++ b/configs/config.peppy @@ -0,0 +1,34 @@ +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_PEPPY=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="/build/peppy/firmware/mrc.bin" +CONFIG_CBFS_SIZE=0x100000 +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_PCI_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_S3_VGA_ROM_RUN is not set +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y +CONFIG_VGA_BIOS_ID="8086,0406" +CONFIG_VGA_BIOS=y +CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/google/peppy/vgabios.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_CACHE_ROM=y +CONFIG_MARK_GRAPHICS_MEM_WRCOMB=y +CONFIG_ELOG=y +CONFIG_ELOG_GSMI=y +CONFIG_ELOG_BOOT_COUNT=y +CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 +CONFIG_SPI_FLASH_SMM=y +CONFIG_CMOS_POST=y +CONFIG_CMOS_POST_OFFSET=0x70 +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y +CONFIG_VBOOT_VERIFY_FIRMWARE=y +CONFIG_FLASHMAP_OFFSET=0x00610000 +# CONFIG_MULTIBOOT is not set +CONFIG_PAYLOAD_NONE=y diff --git a/payloads/libpayload/configs/config.peppy b/payloads/libpayload/configs/config.peppy new file mode 100644 index 0000000..b12c1a4 --- /dev/null +++ b/payloads/libpayload/configs/config.peppy @@ -0,0 +1,71 @@ +# +# Automatically generated make config: don't edit +# libpayload version: 0.2.0 +# Thu May 2 16:10:03 2013 +# + +# +# Generic Options +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_OBSOLETE is not set +# CONFIG_DEVELOPER is not set +CONFIG_CHROMEOS=y + +# +# Architecture Options +# +# CONFIG_ARCH_ARMV7 is not set +# CONFIG_ARCH_POWERPC is not set +CONFIG_ARCH_X86=y +# CONFIG_MEMMAP_RAM_ONLY is not set +# CONFIG_MULTIBOOT is not set + +# +# Standard Libraries +# +CONFIG_LIBC=y +# CONFIG_CURSES is not set +CONFIG_CBFS=y +CONFIG_LZMA=y + +# +# Console Options +# +CONFIG_SKIP_CONSOLE_INIT=y +CONFIG_CBMEM_CONSOLE=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_X86_SERIAL_CONSOLE=y +CONFIG_SERIAL_IOBASE=0x3f8 +# CONFIG_SERIAL_SET_SPEED is not set +# CONFIG_SERIAL_ACS_FALLBACK is not set +CONFIG_VIDEO_CONSOLE=y +# CONFIG_VGA_VIDEO_CONSOLE is not set +# CONFIG_GEODELX_VIDEO_CONSOLE is not set +CONFIG_COREBOOT_VIDEO_CONSOLE=y +CONFIG_PC_KEYBOARD=y +CONFIG_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set + +# +# Drivers +# +CONFIG_PCI=y +CONFIG_NVRAM=y +# CONFIG_RTC_PORT_EXTENDED_VIA is not set +# CONFIG_SPEAKER is not set +# CONFIG_STORAGE is not set +CONFIG_USB=y +CONFIG_USB_UHCI=y +CONFIG_USB_OHCI=y +CONFIG_USB_EHCI=y +# CONFIG_USB_XHCI is not set +CONFIG_USB_HID=y +CONFIG_USB_HUB=y +CONFIG_USB_MSC=y +CONFIG_USB_PCI=y +# CONFIG_USB_MEMORY is not set +# CONFIG_BIG_ENDIAN is not set +CONFIG_LITTLE_ENDIAN=y +CONFIG_IO_ADDRESS_SPACE=y +CONFIG_ARCH_SPECIFIC_OPTIONS=y diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 51df91f..4c36932 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -34,6 +34,8 @@ config BOARD_GOOGLE_LINK bool "Link" config BOARD_GOOGLE_PARROT bool "Parrot" +config BOARD_GOOGLE_PEPPY + bool "Peppy" config BOARD_GOOGLE_PIT bool "Pit" config BOARD_GOOGLE_SLIPPY @@ -49,6 +51,7 @@ source "src/mainboard/google/butterfly/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" source "src/mainboard/google/parrot/Kconfig" +source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/pit/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/snow/Kconfig" diff --git a/src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig new file mode 100644 index 0000000..b7745e1 --- /dev/null +++ b/src/mainboard/google/peppy/Kconfig @@ -0,0 +1,51 @@ +if BOARD_GOOGLE_PEPPY + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_LYNXPOINT_LP + select BOARD_ROMSIZE_KB_8192 + select EC_GOOGLE_CHROMEEC + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select CHROMEOS + select EXTERNAL_MRC_BLOB + select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB + select MONOTONIC_TIMER_MSR + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config MAINBOARD_DIR + string + default google/peppy + +config MAINBOARD_PART_NUMBER + string + default "Peppy" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc new file mode 100644 index 0000000..67b82e5 --- /dev/null +++ b/src/mainboard/google/peppy/Makefile.inc @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_4KTF25664HZ +SPD_SOURCES += Hynix_HMT425S6AFR6A + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $^; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/peppy/acpi/chromeos.asl b/src/mainboard/google/peppy/acpi/chromeos.asl new file mode 100644 index 0000000..e427821 --- /dev/null +++ b/src/mainboard/google/peppy/acpi/chromeos.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + // This GPIO is not available but the package cannot be empty + Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect +}) diff --git a/src/mainboard/google/peppy/acpi/ec.asl b/src/mainboard/google/peppy/acpi/ec.asl new file mode 100644 index 0000000..56ebddc --- /dev/null +++ b/src/mainboard/google/peppy/acpi/ec.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/peppy/ec.h> + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..82a2eba --- /dev/null +++ b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} + diff --git a/src/mainboard/google/peppy/acpi/mainboard.asl b/src/mainboard/google/peppy/acpi/mainboard.asl new file mode 100644 index 0000000..948d7df --- /dev/null +++ b/src/mainboard/google/peppy/acpi/mainboard.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/google/peppy/acpi/platform.asl b/src/mainboard/google/peppy/acpi/platform.asl new file mode 100644 index 0000000..208d76a --- /dev/null +++ b/src/mainboard/google/peppy/acpi/platform.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Update AC status */ + Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) + if (LNotEqual (Local0, \PWRS)) { + Store (Local0, \PWRS) + Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) + } + + /* Update LID status */ + Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) + if (LNotEqual (Local0, \LIDS)) { + Store (Local0, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + Return(Package(){0,0}) +} diff --git a/src/mainboard/google/peppy/acpi/superio.asl b/src/mainboard/google/peppy/acpi/superio.asl new file mode 100644 index 0000000..c652f4f --- /dev/null +++ b/src/mainboard/google/peppy/acpi/superio.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/peppy/ec.h> + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/peppy/acpi/thermal.asl b/src/mainboard/google/peppy/acpi/thermal.asl new file mode 100644 index 0000000..69b6ac9 --- /dev/null +++ b/src/mainboard/google/peppy/acpi/thermal.asl @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + // Get Temperature from TIN# set in NVS + Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + + // Check for sensor not calibrated + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (CTOK(0)) + } + + // Check for sensor not present + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (CTOK(0)) + } + + // Check for sensor not powered + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (CTOK(0)) + } + + // Check for sensor bad reading + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (CTOK(0)) + } + + // Adjust by offset to get Kelvin + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + // Convert to 1/10 Kelvin + Multiply (Local0, 10, Local0) + Return (Local0) + } + + /* CTDP Down */ + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + /* CTDP Nominal */ + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Name (_AL0, Package () { TDP0 }) + Name (_AL1, Package () { TDP1 }) + + PowerResource (TNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + \_SB.PCI0.MCHC.STND () + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + \_SB.PCI0.MCHC.STDN () + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (TNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (TDP0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { TNP0 }) + } + + Device (TDP1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { TNP1 }) + } + } +} + diff --git a/src/mainboard/google/peppy/acpi/video.asl b/src/mainboard/google/peppy/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/google/peppy/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/peppy/acpi_tables.c b/src/mainboard/google/peppy/acpi_tables.c new file mode 100644 index 0000000..7a3ccea --- /dev/null +++ b/src/mainboard/google/peppy/acpi_tables.c @@ -0,0 +1,292 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = CTDP_SENSOR_ID; + + gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; + gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON; + + gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; + gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); + ssdt = (acpi_header_t *)current; + acpi_create_serialio_ssdt(ssdt); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c new file mode 100644 index 0000000..1b70fde --- /dev/null +++ b/src/mainboard/google/peppy/chromeos.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#if CONFIG_EC_GOOGLE_CHROMEEC +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if CONFIG_EC_GOOGLE_CHROMEEC + u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); + + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + return 0; +#endif +} + +static void fill_lb_gpio(struct lb_gpio *gpio, int num, + int polarity, const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = num; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + else if (num >= 0) + gpio->value = get_gpio(num); + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", + get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif + +/* The dev-switch is virtual */ +int get_developer_mode_switch(void) +{ + return 1; +} + +/* There are actually two recovery switches. One is the magic keyboard chord, + * the other is driven by Servo. */ +int get_recovery_mode_switch(void) +{ +#if CONFIG_EC_GOOGLE_CHROMEEC + u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); + u32 ec_events; + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + return get_gpio(58); +} diff --git a/src/mainboard/google/peppy/cmos.layout b/src/mainboard/google/peppy/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/google/peppy/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb new file mode 100644 index 0000000..fc6462c --- /dev/null +++ b/src/mainboard/google/peppy/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/intel/haswell + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/haswell + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S) + register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S) + register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl new file mode 100644 index 0000000..1316ebf --- /dev/null +++ b/src/mainboard/google/peppy/dsdt.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <cpu/intel/haswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c new file mode 100644 index 0000000..0919f0f --- /dev/null +++ b/src/mainboard/google/peppy/ec.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_wake_mask(0); + + post_code(0xf1); +} diff --git a/src/mainboard/google/peppy/ec.h b/src/mainboard/google/peppy/ec.h new file mode 100644 index 0000000..11d2453 --- /dev/null +++ b/src/mainboard/google/peppy/ec.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ +#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/google/peppy/fadt.c b/src/mainboard/google/peppy/fadt.c new file mode 100644 index 0000000..7afbbfa --- /dev/null +++ b/src/mainboard/google/peppy/fadt.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = get_pmbase(); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/peppy/gpio.h b/src/mainboard/google/peppy/gpio.h new file mode 100644 index 0000000..6dfb98f --- /dev/null +++ b/src/mainboard/google/peppy/gpio.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PEPPY_GPIO_H +#define PEPPY_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 12: TRACKPAD_INT_L */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ + LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 25: TOUCH_INT_L */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_UNUSED, /* 43: UNUSED */ + LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ + LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 51: ALS_INT_L */ + LP_GPIO_IRQ_EDGE, /* 52: SIM_DET */ + LP_GPIO_ACPI_SCI, /* 53: TRACKPAD_INT_DX (WAKE) */ + LP_GPIO_ACPI_SCI, /* 54: TOUCH_INT_L_DX (WAKE) */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ + LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ + LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/peppy/hda_verb.h b/src/mainboard/google/peppy/hda_verb.h new file mode 100644 index 0000000..56275a2 --- /dev/null +++ b/src/mainboard/google/peppy/hda_verb.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 + 0x10134210, // Subsystem ID + 0x00000007, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */ + 0x00172010, + 0x00172142, + 0x00172213, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */ + 0x00571cf0, + 0x00571d20, + 0x00571e21, + 0x00571f02, + + /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */ + 0x00671c10, + 0x00671d00, + 0x00671e17, + 0x00671f90, + + /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */ + 0x00771cf0, + 0x00771d20, + 0x00771ea1, + 0x00771f02, + + /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */ + 0x00871c37, + 0x00871d00, + 0x00871ea7, + 0x00871f77, + + /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */ + 0x00971c3e, + 0x00971d00, + 0x00971ea6, + 0x00971f77, + + /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */ + 0x00a71cf0, + 0x00a71d10, + 0x00a71e45, + 0x00a71f43, + + /* coreboot specific header */ + 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x00172001, + 0x00172101, + 0x00172286, + 0x00172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c new file mode 100644 index 0000000..0159bd0 --- /dev/null +++ b/src/mainboard/google/peppy/mainboard.c @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/lynxpoint/pch.h> +#include "ec.h" + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +/* Audio Setup */ + +extern const u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c new file mode 100644 index 0000000..8679adb --- /dev/null +++ b/src/mainboard/google/peppy/romstage.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include "cpu/intel/haswell/haswell.h" +#include "northbridge/intel/haswell/haswell.h" +#include "northbridge/intel/haswell/raminit.h" +#include "southbridge/intel/lynxpoint/pch.h" +#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include "gpio.h" + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +/* Copy SPD data for on-board memory */ +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + struct cbfs_file *spd_file; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + if (ntohl(spd_file->len) < + ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file->len < sizeof(peid->spd_data[0])) + die("Missing SPD data."); + + memcpy(peid->spd_data[0], + ((char*)CBFS_SUBHEADER(spd_file)) + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); +} + +/* + * Power Sequencing for SanDisk i100/i110 SSD + * + * Must be sequenced in this order with specified timing. + * + * 1. VCC_IO : 30us - 100ms + * 2. VCC_FLASH : 70us - 10ms + * 3. VCCQ : 70us - 10ms + * 4. VDDC : 30us - 100ms + * + * There is no feedback to know if the voltage has stabilized + * so this implementation will use the max ramp times. That + * means it adds significantly to the boot time. + */ +static void issd_power_sequence(void) +{ + struct gpio_seq { + int gpio; + int wait_ms; + } issd_gpio_seq[] = { + { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ + { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ + { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ + { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ + }; + int step; + + for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) { + set_gpio(issd_gpio_seq[step].gpio, 1); + udelay(issd_gpio_seq[step].wait_ms * 1000); + } +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + pei_version: PEI_VERSION, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: DEFAULT_PCIEXBAR, + smbusbar: SMBUS_IO_BASE, + wdbbar: 0x4000000, + wdbsize: 0x1000, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBA, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, + temp_mmio_base: 0xfed08000, + system_type: 5, /* ULT */ + tseg_size: CONFIG_SMM_TSEG_SIZE, + spd_addresses: { 0xff, 0x00, 0xff, 0x00 }, + ec_present: 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + dimm_channel0_disabled: 2, + dimm_channel1_disabled: 2, + max_ddr3_freq: 1600, + usb2_ports: { + /* Length, Enable, OCn# */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ + { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ + { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ + { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ + { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ + }, + usb3_ports: { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; + + /* Prepare SPD data */ + copy_spd(&pei_data); + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); + + /* Power sequence the iSSD module */ + issd_power_sequence(); +} diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c new file mode 100644 index 0000000..7b7dd69 --- /dev/null +++ b/src/mainboard/google/peppy/smihandler.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> +#include <elog.h> + +/* Include EC functions */ +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +static u8 mainboard_smi_ec(void) +{ + u8 cmd = google_chromeec_get_event(); + u32 pm1_cnt; + +#if CONFIG_ELOG_GSMI + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, get_pmbase() + PM1_CNT); + break; + } + + return cmd; +} + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0); + } +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + break; + case 5: + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + break; + } + + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +} + +#define APMC_FINALIZE 0xcb + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + mainboard_finalized = 1; + break; + case APM_CNT_ACPI_ENABLE: + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + break; + case APM_CNT_ACPI_DISABLE: + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + break; + } + return 0; +} diff --git a/src/mainboard/google/peppy/thermal.h b/src/mainboard/google/peppy/thermal.h new file mode 100644 index 0000000..fceaeca --- /dev/null +++ b/src/mainboard/google/peppy/thermal.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* Config TDP Sensor ID */ +#define CTDP_SENSOR_ID 1 /* PECI */ + +/* Config TDP Nominal */ +#define CTDP_NOMINAL_THRESHOLD_OFF 0 +#define CTDP_NOMINAL_THRESHOLD_ON 0 + +/* Config TDP Down */ +#define CTDP_DOWN_THRESHOLD_OFF 80 +#define CTDP_DOWN_THRESHOLD_ON 90 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 100 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif

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Patch set updated for coreboot: b8c6fba peppy: Add Elipda DIMM SPD
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4201 -gerrit commit b8c6fba0dfa8683cd89271fd4f2cd14306bd332e Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Sat May 25 09:38:16 2013 -0700 peppy: Add Elipda DIMM SPD Peppy RAM ID table is as follows: 000 41K256M16HA 001 H5TC4G63AFR 010 EDJ4216EFBG Elpida SPD taken from Ib1e430cd390b4dbc013fc0802f1a59c1a0412577 by dlaurie. Change-Id: Iac156a2d25435514f28e2e73bef617d0fe2d90a1 Reviewed-on: https://gerrit.chromium.org/gerrit/56687 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Dave Parker <dparker(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex | 17 +++++++++++++++++ src/mainboard/google/peppy/Makefile.inc | 1 + 2 files changed, 18 insertions(+) diff --git a/src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex new file mode 100644 index 0000000..eb41f0b --- /dev/null +++ b/src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex @@ -0,0 +1,17 @@ +# Elpida EDJ4216EFBG-GN-F +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc index 67b82e5..be7f01e 100644 --- a/src/mainboard/google/peppy/Makefile.inc +++ b/src/mainboard/google/peppy/Makefile.inc @@ -30,6 +30,7 @@ SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ SPD_SOURCES += Hynix_HMT425S6AFR6A +SPD_SOURCES += Elpida_EDJ4216EFBG SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)

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Patch set updated for coreboot: 2cea3b6 falco: Add Elpida DIMM SPD
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4192 -gerrit commit 2cea3b6201a206c7c56ec63d0820a9d25e77f949 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 24 12:43:24 2013 -0700 falco: Add Elpida DIMM SPD This was provided by the vendor but I added the part number at byte 128-143 so it can be identified when extracted by mosys. Change-Id: Ib1e430cd390b4dbc013fc0802f1a59c1a0412577 Reviewed-on: https://gerrit.chromium.org/gerrit/56634 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex | 17 +++++++++++++++++ src/mainboard/google/falco/Makefile.inc | 1 + 2 files changed, 18 insertions(+) diff --git a/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex new file mode 100644 index 0000000..eb41f0b --- /dev/null +++ b/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex @@ -0,0 +1,17 @@ +# Elpida EDJ4216EFBG-GN-F +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index 7e6a9ac..e19db11 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -30,6 +30,7 @@ SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! SPD_SOURCES = Hynix_HMT425S6AFR6A SPD_SOURCES += Micron_4KTF25664HZ +SPD_SOURCES += Elpida_EDJ4216EFBG SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)

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Patch set updated for coreboot: 6c28803 libpayload: allow for pointers in cbfs ram media
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4193 -gerrit commit 6c2880359509f9fe3110cea0fab3e48862b0f1ba Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 24 13:34:38 2013 -0500 libpayload: allow for pointers in cbfs ram media The ram_map() handled offsets from 0->size as well as negative offsets from the top of the region. However, the cbfs core tries to map a offset that is actually a pointer within the region itself. Allow for such instances. This fixes an issue when using ram_media with tthe ebmedded SeaBIOS cbfs. Change-Id: I15b0b3b643390d3784ae5887c0f17d420d59c5b6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56641 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/libcbfs/ram_media.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 859555c..9f11a31 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -43,6 +43,12 @@ static int ram_open(struct cbfs_media *media) { static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { struct ram_media *m = (struct ram_media*)media->context; + + /* Special case an absolute pointer within the region. */ + if (offset >= (uintptr_t)m->start && + offset < ((uintptr_t)m->start + m->size)) + return (void *)offset; + /* assume addressing from top of image in this case */ if (offset > 0xf0000000) { offset = m->size + offset;

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coreboot-gerrit November 2013