coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 5d31e25 libpayload: expose cbfs ram functions
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4194 -gerrit commit 5d31e2501bebfde2a4c2cd7db529827d9a1858ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 24 13:40:51 2013 -0500 libpayload: expose cbfs ram functions The ram_media.c file is being compiled, however the global functions were not exposed through a header. Change-Id: I4588fbe320c29051566cef277bf4d20a83abf853 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56642 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/cbfs_ram.h | 61 +++++++++++++++++++++++++++++++++ payloads/libpayload/libcbfs/ram_media.c | 4 +-- 2 files changed, 62 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/include/cbfs_ram.h b/payloads/libpayload/include/cbfs_ram.h new file mode 100644 index 0000000..defe823 --- /dev/null +++ b/payloads/libpayload/include/cbfs_ram.h @@ -0,0 +1,61 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * This file is dual-licensed. You can choose between: + * - The GNU GPL, version 2, as published by the Free Software Foundation + * - The revised BSD license (without advertising clause) + * + * --------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * --------------------------------------------------------------------------- + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * --------------------------------------------------------------------------- + */ + +#ifndef _CBFS_RAM_H_ +#define _CBFS_RAM_H_ + +#include <stdint.h> + +struct cbfs_media; + +/* The following functions return 0 for success. None-zero on error. */ +int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size); +int setup_cbfs_from_ram(void *start, uint32_t size); +int setup_cbfs_from_flash(void); + +#endif /* _CBFS_RAM_H_ */ diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 9f11a31..a260b05 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ #include <cbfs.h> +#include <cbfs_ram.h> #include <string.h> #include <stdio.h> #include <stdlib.h> @@ -77,7 +78,6 @@ static int ram_close(struct cbfs_media *media) { return 0; } -int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size); int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size) { // TODO Find a way to release unused media. Maybe adding media->destroy. struct ram_media *m = (struct ram_media*)malloc(sizeof(*m)); @@ -96,7 +96,6 @@ int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size) { static int is_default_cbfs_media_initialized; static struct cbfs_media default_cbfs_media; -int setup_cbfs_from_ram(void *start, uint32_t size); int setup_cbfs_from_ram(void *start, uint32_t size) { int result = init_cbfs_ram_media(&default_cbfs_media, start, size); if (result == 0) @@ -105,7 +104,6 @@ int setup_cbfs_from_ram(void *start, uint32_t size) { } extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int setup_cbfs_from_flash(void); int setup_cbfs_from_flash(void) { int result = libpayload_init_default_cbfs_media(&default_cbfs_media); if (result == 0)

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Patch set updated for coreboot: 6c1454a slippy: Add panel power sequence timings
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4196 -gerrit commit 6c1454ac0ede1a1f446ac6a1499c889bbec6ea5d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:54:15 2013 -0700 slippy: Add panel power sequence timings These are placeholder values until we can configure for the exact panel. Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56807 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index fc6462c..b9bc47f 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -13,6 +13,14 @@ chip northbridge/intel/haswell register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000" + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end

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Patch set updated for coreboot: 51dd82d haswell: Add magic to turn on grahpics in normal mode
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4195 -gerrit commit 51dd82db1b38dec3577e3599895773181f687e72 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:49:09 2013 -0700 haswell: Add magic to turn on grahpics in normal mode The haswell i915 kernel driver apparently expects the VBIOS to set a few specific registers. This sequence is enough to make the driver happy without executing the VBIOS. This also makes graphics work after suspend/resume. Change-Id: I34937d55ffff8a9445442e6e6ca1bfc49869da63 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56806 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f3ddbd3..467ed93 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -131,17 +131,13 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write(0x0a094, 0x00040000); } -static void gma_pm_init_post_vbios(struct device *dev) +static void gma_setup_panel(struct device *dev) { struct northbridge_intel_haswell_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - /* Disable Force Wake */ - gtt_write(0x0a188, 0x00010000); - gtt_poll(0x130044, 1 << 0, 0 << 0); - /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { @@ -187,6 +183,22 @@ static void gma_pm_init_post_vbios(struct device *dev) } } +static void gma_pm_init_post_vbios(struct device *dev) +{ + extern int oprom_is_loaded; + + if (!oprom_is_loaded) { + /* Magic to force graphics into happy state for kernel */ + gtt_write(0xc7204, 0xabcd000f); /* panel power up */ + gtt_write(0x45400, 0x80000000); /* power well enable */ + gtt_write(0x64000, 0x00000091); /* DDI-A enable */ + } + + /* Disable Force Wake */ + gtt_write(0x0a188, 0x00010000); + gtt_poll(0x130044, 1 << 0, 0 << 0); +} + static void gma_func0_init(struct device *dev) { int lightup_ok = 0; @@ -203,9 +215,13 @@ static void gma_func0_init(struct device *dev) * So it's almost like having two hardcodes. */ graphics_base = dev->resource_list[1].base; + /* Init graphics power management */ gma_pm_init_pre_vbios(dev); + /* Post VBIOS init */ + gma_setup_panel(dev); + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); u32 iobase, mmiobase, physbase;

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Patch set updated for coreboot: ed21a51 falco: Add panel power sequence timings
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4197 -gerrit commit ed21a51e4ffe77f25ceb37dd3380eb112f55e4ce Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:55:02 2013 -0700 falco: Add panel power sequence timings These are placeholder values until we can configure for the exact panel. Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56808 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index fc6462c..b9bc47f 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -13,6 +13,14 @@ chip northbridge/intel/haswell register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000" + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end

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Patch set updated for coreboot: de95522 falco: Update DIMM SPD table
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4198 -gerrit commit de955224ae9458ad94969fcd9b279a861570aa8d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 08:32:21 2013 -0700 falco: Update DIMM SPD table RAM_ID indices have been changed and settled on a 2GB config that will be the same DRAM chips but only used in one channel. Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56810 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/falco/Makefile.inc | 9 ++++++--- src/mainboard/google/falco/romstage.c | 6 ++++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index e19db11..edb8cf6 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -28,9 +28,12 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Hynix_HMT425S6AFR6A -SPD_SOURCES += Micron_4KTF25664HZ -SPD_SOURCES += Elpida_EDJ4216EFBG +SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 +SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 +SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only +SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only +SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 3bf1dbd..ef6a849 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -91,6 +91,12 @@ static void copy_spd(struct pei_data *peid) if (spd_file->len < sizeof(peid->spd_data[0])) die("Missing SPD data."); + /* Index 0-2 are 4GB config with both CH0 and CH1 + * Index 3-5 are 2GB config with CH0 only + */ + if (spd_index > 2) + peid->dimm_channel1_disabled = 3; + memcpy(peid->spd_data[0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index * sizeof(peid->spd_data[0]),

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Patch set updated for coreboot: 98ecda6 libpayload: provide missing cbfs symbol
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4199 -gerrit commit 98ecda6aae3cee877ba24fd0b9145cc98e877aa0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 09:25:32 2013 -0500 libpayload: provide missing cbfs symbol The generic cbfs code relies on the libpayload_init_default_cbfs_media symbol. However, none was provided for ARM. Provide an empty implementation that returns an error as there is no generic way to locate the default cbfs media. Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56805 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/arch/armv7/Makefile.inc | 1 + payloads/libpayload/arch/armv7/dummy_media.c | 42 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index 9c7fe83..e8ca109 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -34,3 +34,4 @@ libc-y += virtual.c libc-y += memcpy.S memset.S libc-y += exception_asm.S exception.c libc-y += cache.c +libc-y += dummy_media.c diff --git a/payloads/libpayload/arch/armv7/dummy_media.c b/payloads/libpayload/arch/armv7/dummy_media.c new file mode 100644 index 0000000..7926976 --- /dev/null +++ b/payloads/libpayload/arch/armv7/dummy_media.c @@ -0,0 +1,42 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define LIBPAYLOAD + +#include <cbfs.h> +#include <string.h> + +/* The generic cbfs code relies on the libpayload_init_default_cbfs_media + * symbol. Therefore, provide an implementation that just throws an error. */ + +int libpayload_init_default_cbfs_media(struct cbfs_media *media); + +int libpayload_init_default_cbfs_media(struct cbfs_media *media) +{ + return -1; +}

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Patch set updated for coreboot: a374afc slippy: Update SPD
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4157 -gerrit commit a374afc6ee9741535a5ea6b3f062e66fd39bea99 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 3 15:59:59 2013 -0700 slippy: Update SPD Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50082 --- src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex | 17 +++++++++++++++++ src/mainboard/google/slippy/Makefile.inc | 3 ++- src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex | 17 +++++++++++++++++ .../google/slippy/Micron_MT41K256M16HA.spd.hex | 17 ----------------- 4 files changed, 36 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 1b80e6b..67b82e5 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -28,7 +28,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_MT41K256M16HA +SPD_SOURCES = Micron_4KTF25664HZ +SPD_SOURCES += Hynix_HMT425S6AFR6A SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex deleted file mode 100644 index a310e17..0000000 --- a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Micron MT41K256M16HA-125 DDR3L-1600 -92 11 0B 03 04 19 00 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2C 00 00 00 00 00 00 00 06 F2 -34 4A 54 46 32 35 36 36 20 34 48 5A 2D 31 47 36 -45 31 45 31 80 2C 00 00 00 00 00 00 00 00 01 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

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Patch set updated for coreboot: 5a29ad2e Make ssize_t an actual ssize_t
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4156 -gerrit commit 5a29ad2e2939de28bb2db2ff916fc7c8188b9292 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 2 14:02:28 2013 -0700 Make ssize_t an actual ssize_t In the process of getting rid of compiler includes during in coreboot and libpayload, we defined size_t and ssize_t ourselves, using a GCC macro for size_t: __SIZE_TYPE__. Unfortunately, there is no __SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make __SIZE_TYPE__ __SSIZE_TYPE__. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b Reviewed-on: https://gerrit.chromium.org/gerrit/49947 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/stddef.h | 8 +++++++- src/include/stddef.h | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index 91ae782..f9deaeb 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -5,7 +5,13 @@ #define __SIZE_TYPE__ unsigned long #endif typedef __SIZE_TYPE__ size_t; -typedef long ssize_t; +/* There is a GCC macro for a size_t type, but not + * for a ssize_t type. Below construct tricks GCC + * into making __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *) 0)->MEMBER) diff --git a/src/include/stddef.h b/src/include/stddef.h index 5b51c00..d0dad62 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -6,7 +6,13 @@ typedef long ptrdiff_t; #define __SIZE_TYPE__ unsigned long #endif typedef __SIZE_TYPE__ size_t; -typedef long ssize_t; +/* There is a GCC macro for a size_t type, but not + * for a ssize_t type. Below construct tricks GCC + * into making __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned typedef int wchar_t; typedef unsigned int wint_t;

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Patch set updated for coreboot: be6d385 x86: call cbfstool update-fit when fit selected
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4159 -gerrit commit be6d38520fa3839f5a4aa143d91d54693443f56a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 10:56:16 2013 -0500 x86: call cbfstool update-fit when fit selected In order for the FIT entries to be populated in the table the update-fit command needs to be done on the coreboot image. That way the microcode entries are added to the table properly. Change-Id: I44595aee1ca710f4f04d482d8900cf95fbc1797f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50317 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index dee56c5..3939122 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -130,6 +130,12 @@ endif ifeq ($(CONFIG_PXE_ROM),y) $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw endif +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) + @printf " UPDATE-FIT \n" + $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) +endif +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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Patch set updated for coreboot: 4d0e7b2 lynxpoint: Expose ACPI Device for LP GPIO controller
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4158 -gerrit commit 4d0e7b21b8b8ccedd6be9307af26d21a68022fb4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 6 14:02:27 2013 -0700 lynxpoint: Expose ACPI Device for LP GPIO controller In order to probe the gpio-lynxpoint kernel driver the LP GPIO controller needs to be exposed as a specific ACPI device. This also allows the resources to be exposed to the OS via this device instead of the catch-all LPC device. Ensure the driver loads at boot: gpiochip_find_base: found new base at 162 gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00 Also ensure the driver is visible in sysfs: $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label INT33C7:00 Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50215 --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 58 ++++------------------- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 50 +++++++++++++++++++ 2 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index f9bf578..7e26926 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -199,60 +199,22 @@ Device (LPCB) 0x1, 0xff) // GPIO region may be 128 bytes or 4096 bytes - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, - 0x1, 0x00, GPR1) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR2) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR3) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR4) + IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) }) Method (_CRS, 0, NotSerialized) { - CreateByteField (^RBUF, ^GPR1._LEN, R1LN) - CreateByteField (^RBUF, ^GPR2._LEN, R2LN) - CreateByteField (^RBUF, ^GPR3._LEN, R3LN) - CreateByteField (^RBUF, ^GPR4._LEN, R4LN) + // LynxPoint-LP GPIO resources are defined in the + // SerialIO GPIO device and LynxPoint-H GPIO resources + // are defined here. + If (LNot (\ISLP ())) { + CreateByteField (^RBUF, ^GPR1._LEN, R1LN) + CreateWordField (^RBUF, ^GPR1._MIN, R1MN) + CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - CreateWordField (^RBUF, ^GPR1._MIN, R1MN) - CreateWordField (^RBUF, ^GPR2._MIN, R2MN) - CreateWordField (^RBUF, ^GPR3._MIN, R3MN) - CreateWordField (^RBUF, ^GPR4._MIN, R4MN) - - CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - CreateWordField (^RBUF, ^GPR2._MAX, R2MX) - CreateWordField (^RBUF, ^GPR3._MAX, R3MX) - CreateWordField (^RBUF, ^GPR4._MAX, R4MX) - - // Update GPIO region for LynxPoint-LP - If (\ISLP ()) { - // LynxPoint-LP - Store (R1MN, Local0) - - // Update GPIO bank 1 - Store (Local0, R1MN) - Store (Local0, R1MX) - Store (0xff, R1LN) - - // Update GPIO bank 2 - Add (Local0, 0x100, Local0) - Store (Local0, R2MN) - Store (Local0, R2MX) - Store (0xff, R2LN) - - // Update GPIO bank 3 - Add (Local0, 0x100, Local0) - Store (Local0, R3MN) - Store (Local0, R3MN) - Store (0xff, R3LN) - - // Update GPIO bank 4 - Add (Local0, 0x100, Local0) - Store (Local0, R4MN) - Store (Local0, R4MN) - Store (0xff, R4LN) - } Else { - // LynxPoint-H // Update GPIO region length + Store (DEFAULT_GPIOBASE, R1MN) + Store (DEFAULT_GPIOBASE, R1MX) Store (DEFAULT_GPIOSIZE, R1LN) } Return (RBUF) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 6ea23c6..03f6974 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -468,3 +468,53 @@ Device (SDIO) } } } + +Device (GPIO) +{ + // GPIO Controller + Name (_HID, "INT33C7") + Name (_CID, "INT33C7") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + DWordIo (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + EntireRange, // ISARanges + 0x00000000, // AddressGranularity + 0x00000000, // AddressMinimum + 0x00000000, // AddressMaximum + 0x00000000, // AddressTranslation + 0x00000000, // RangeLength + , // ResourceSourceIndex + , // ResourceSource + BAR0) + }) + + Method (_CRS, 0, NotSerialized) + { + If (\ISLP ()) { + CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) + CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) + CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) + + Store (DEFAULT_GPIOSIZE, BLEN) + Store (DEFAULT_GPIOBASE, BMIN) + Store (Subtract (Add (DEFAULT_GPIOBASE, + DEFAULT_GPIOSIZE), 1), BMAX) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (\ISLP ()) { + Return (0xF) + } Else { + Return (0x0) + } + } +}

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coreboot-gerrit November 2013