the following patch was just integrated into master:
commit e9b50628d1c7f0cc8046903188562eebec8107bb
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Sat May 25 09:38:16 2013 -0700
peppy: Add Elipda DIMM SPD
Peppy RAM ID table is as follows:
000 41K256M16HA
001 H5TC4G63AFR
010 EDJ4216EFBG
Elpida SPD taken from Ib1e430cd390b4dbc013fc0802f1a59c1a0412577 by
dlaurie.
Change-Id: Iac156a2d25435514f28e2e73bef617d0fe2d90a1
Reviewed-on: https://gerrit.chromium.org/gerrit/56687
Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-by: Dave Parker <dparker(a)chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4201
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4201 for details.
-gerrit
the following patch was just integrated into master:
commit e9d060d42c7ae3552962804cdab282738c4eeffa
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Thu May 23 15:13:46 2013 -0700
peppy: Initial mainboard commit
Taken directly from slippy with only constant + string changes.
(Peppy port of I4172460d3b075bfd5bb22013a6225cf0e8f95b9c by dlaurie)
The following changes are required in a subsequent commit:
- Add Elpida SPD data.
- Update GPIO map.
- Remove iSSD power sequencing.
- Update USB port map.
Change-Id: I01dfb841f0e9186cf8a0a23f72e7be986a83be42
Reviewed-on: https://gerrit.chromium.org/gerrit/56513
Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-by: Dave Parker <dparker(a)chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4200
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4200 for details.
-gerrit
the following patch was just integrated into master:
commit ae1ef60dfa304450bacc475cd767ac4a610a76e0
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 28 08:32:21 2013 -0700
falco: Update DIMM SPD table
RAM_ID indices have been changed and settled on a 2GB config
that will be the same DRAM chips but only used in one channel.
Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56810
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4198
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4198 for details.
-gerrit
the following patch was just integrated into master:
commit 116aa3a1900dae2beb56f381e91c9890c1e8ca30
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 28 07:55:02 2013 -0700
falco: Add panel power sequence timings
These are placeholder values until we can configure for
the exact panel.
Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56808
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4197
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4197 for details.
-gerrit
the following patch was just integrated into master:
commit c7f2ab742b2589281efa852309e29c8da5270fbe
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 28 07:49:09 2013 -0700
haswell: Add magic to turn on grahpics in normal mode
The haswell i915 kernel driver apparently expects the VBIOS
to set a few specific registers. This sequence is enough to
make the driver happy without executing the VBIOS.
This also makes graphics work after suspend/resume.
Change-Id: I34937d55ffff8a9445442e6e6ca1bfc49869da63
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56806
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4195
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4195 for details.
-gerrit
the following patch was just integrated into master:
commit 22419e045616c344c7a2a308c5ef086a221ad006
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 24 12:37:02 2013 -0700
falco: Add on-board devices and configure GPIO irq/wake
Add the onboard I2C devices for Falco trackpad/lightsensor
and generate SMBIOS Type41 tables for them.
Add ACPI device for the trackpad to expose the interrupt map
to the OS so it can be used.
Configure interrupt GPIOs as PIRQ type and wake GPIOs as
just standard input type. The wake GPIO is reconfigured as
ACPI SCI in the specific device _DSW method. This prevents
the wake GPIO from generating a flood of SCI at runtime.
LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these
are not repurposed interrupt pins so they are not generated
at runtime.
SIM_DET and ALS_INT_L are set as input since we don't have an
interrupt handler for them.
Change-Id: Ibe9687b2f7f41ead18353c3f650219fe6e94ae2f
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56632
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4191
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4191 for details.
-gerrit
the following patch was just integrated into master:
commit d67c5dbf06f009b705bc0c2b7278504bb538d36e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 24 11:27:12 2013 -0700
slippy: Add on-board devices and configure GPIO irq/wake
Add the onboard I2C devices for Slippy trackpad/lightsensor
and generate SMBIOS Type41 tables for them.
Add ACPI device for the trackpad to expose the interrupt map
to the OS so it can be used.
Configure interrupt GPIOs as PIRQ type and wake GPIOs as
just standard input type. The wake GPIO is reconfigured as
ACPI SCI in the specific device _DSW method. This prevents
the wake GPIO from generating a flood of SCI at runtime.
LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these
are not repurposed interrupt pins so they are not generated
at runtime.
SIM_DET and ALS_INT_L are set as input since we don't have an
interrupt handler for them.
tested on slippy with trackpad with additional
kernel changes to chromeos_laptop.c to initialize devices.
1) Ensure trackpad interrupt is functional and that there
is not a flood of ACPI SCI when trackpad does interrupt:
9: 1 0 0 0 IO-APIC-fasteoi acpi
37: 421 0 0 0 IO-APIC-fasteoi cyapa
2) Ensure that devices are exposed as wake capable:
Device S-state Status Sysfs node
TPAD S3 *enabled pnp:00:00
TSCR S3 *disabled pnp:00:01
3) Ensure that trackpad can wake from S3 by default, but
that it does not cause an immediate wake when entering suspend.
4) Ensure that trackpad can be disabled as a wake source with
echo TPAD > /proc/acpi/wakeup
Change-Id: Id562d20b54eeefec56040b8f70ef238911312628
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56622
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4190
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/4190 for details.
-gerrit
the following patch was just integrated into master:
commit 14031db21f3a41966a30bfc27bc97ddf03f40458
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 24 11:10:31 2013 -0700
lynxpoint: Add ACPI Method to enable GPIO as wake source
This is an LPT-LP specific method that will enable a specific
GPIO as an ACPI SCI wake source.
It can be used by a device _DSW method to enable a pin that is
otherwise not configured to generate SCI at runtime.
It will set:
- GPIO owner to ACPI
- GPIO route to SCI
- GPIO config to GPIO, Input, Inverted
Also clean up and remove ACPI field definitions that are unused
and/or incorrect.
Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56621
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4189
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/4189 for details.
-gerrit
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4276
-gerrit
commit 3008dde4a340782e9651541d049178cb36d53880
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Mon Nov 25 23:40:01 2013 +0100
ibexpeak: set HAVE_USBDEBUG_OPTIONS
Previously, I've set this config in mobo config, yet according to
Kyösti Mälkki this parameter is southbridge-specific and not
mobo-specific.
Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/southbridge/intel/ibexpeak/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index c408dca..07e714b 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select SOUTHBRIDGE_INTEL_COMMON
+ select HAVE_USBDEBUG_OPTIONS
config EHCI_BAR
hex
the following patch was just integrated into master:
commit 96f77bd0d9436eb4259d2a132670735ac20e8b95
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 24 12:43:24 2013 -0700
falco: Add Elpida DIMM SPD
This was provided by the vendor but I added the part number at
byte 128-143 so it can be identified when extracted by mosys.
Change-Id: Ib1e430cd390b4dbc013fc0802f1a59c1a0412577
Reviewed-on: https://gerrit.chromium.org/gerrit/56634
Tested-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4192
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4192 for details.
-gerrit