coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 7fab00c lynxpoint: Fix XHCI controller device in ACPI
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 7fab00c8976bae54ed32617dd1e4c9b0ace249ab Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 22 09:51:11 2013 -0700 lynxpoint: Fix XHCI controller device in ACPI The ACPI code was defining two EHCI controllers and ignoring the XHCI controller. This changes the second EHCI controller to be XHCI instead and changes the wake resource to indicate S3 and not S4. cat /proc/acpi/wakeup Device S-state Status Sysfs node HDEF S4 *disabled pci:0000:00:1b.0 EHCI S3 *enabled pci:0000:00:1d.0 XHCI S3 *enabled pci:0000:00:14.0 Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56263 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4181 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4181 for details. -gerrit

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Patch merged into coreboot/master: 98c4062 lynxpoint: Enable SerialIO clock in PCI mode
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 98c40622feeaf1d8f211501e8f337d5bde544d13 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 16:37:40 2013 -0700 lynxpoint: Enable SerialIO clock in PCI mode The clock gating register at offset 0x800 is managed by the clock driver in the kernel when the devices are in ACPI mode. When in PCI mode we should force enable the clock here. When in ACPI mode or the device is disabled it should be put in D3Hot state. > i2cdetect -y -r 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56122 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4180 for details. -gerrit

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Patch merged into coreboot/master: 8d1b132 libpayload: Fix xcompile
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 8d1b132733ab82b689e9a7fd6677e317b1535c92 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 21 12:15:50 2013 -0700 libpayload: Fix xcompile The architecture name for our ARM port is armv7, not arm. Hence, none of those flags were ever actually used. Fix the architecture name and remove the flags, they should not be set in xcompile, but in the Makefile, like in coreboot. Change-Id: Id9c5db7ebceafddb58a1ce1988417f09c074ba6c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56084 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4179 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4179 for details. -gerrit

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Patch merged into coreboot/master: cd7bb2f slippy: Enable EC SMI
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit cd7bb2faab769a16bacac8bcbfa20fec970dce16 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 09:28:28 2013 -0700 slippy: Enable EC SMI Enable GPIO SMI for GPIO34 and set it as inverted so it is only generated when it is raised by the EC. 1) ec console command: lidopen 2) wait until booted to developer screen 3) ec console command: lidclose 4) ensure system turns off Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56052 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4177 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4177 for details. -gerrit

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Patch merged into coreboot/master: 8992e53 libpayload: Add USB support for non-PCI controllers
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 8992e53c23cb088efbdafbf3e2ba77e7d8778d71 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 2 16:16:41 2013 -0700 libpayload: Add USB support for non-PCI controllers Restructure USB stack to not depend on PCI, and make PCI stub available on x86, but provide fixed BARs for ARM (Exynos 5) Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49970 Reviewed-on: http://review.coreboot.org/4175 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4175 for details. -gerrit

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Patch merged into coreboot/master: 441a4ba libpayload (EHCI): correctly align PORTSC
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 441a4baf87ada2608a109a203a5d8040f6dc2b0d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 17 11:56:09 2013 -0700 libpayload (EHCI): correctly align PORTSC Two structures in the USB EHCI stack were pointing to hardware but not marked attribute((packed)) hence leaving it to GCC to correctly align the data structures. Next, the number of reserved bytes in hc_op_t was wrong (but implicitly aligned to the correct values on x86) It seems this worked fine on x86, but on ARM it was doing the wrong thing. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d Reviewed-on: https://gerrit.chromium.org/gerrit/55555 Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4174 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4174 for details. -gerrit

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Patch merged into coreboot/master: ed095ca lynxpoint: update azalia device ids
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit ed095ca39a99d7dcc94856612cfff5695bd87ae6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 20 15:57:16 2013 -0500 lynxpoint: update azalia device ids The vendor ids were never updated to reflect LynxPoint's device ids. Therefore, none of the initialization was being ran. Fix this. Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55821 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4173 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4173 for details. -gerrit

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Patch merged into coreboot/master: d7cb8d0 lynxpoint: Change SerialIO device enable reporting to ACPI
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit d7cb8d074f4a9e437ed897ac596ca794698b38c9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 15 15:03:57 2013 -0700 lynxpoint: Change SerialIO device enable reporting to ACPI In order to report whether coreboot enabled a SerialIO device in ACPI mode we had been relying on reading NVS in the _STA method for the SerialIO device. The ACPI _STA method has restrictions on what it can access and is unable to access OperationRegions outside its scope which means it should not be trying to read NVS. This change adds a new SSDT to the ACPI tables and fills it with constants that indicate whether or not a device is enabled in ACPI mode. The ACPI code is changed to read these variables from the SSDT and use that instead of trying to query a variable in NVS. Attempt to use lpt-clk driver to probe the device clocks for SerialIO devices and see that the kernel does not complain about accessing the GNVS region. Change-Id: I8538bee4390daed4ecca679496ab0cb313f174ce Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51369 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4170 for details. -gerrit

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Patch merged into coreboot/master: 8d783b8 slippy: Minor vboot related fixes
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 8d783b84930e2e14e4f70234ea6589acd06557e7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 14 11:16:34 2013 -0700 slippy: Minor vboot related fixes - Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4169 for details. -gerrit

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Patch merged into coreboot/master: 1c05400 Fix int15 return value for mainboard oprom handlers
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 1c0540000dc4705cee44857293285382f4ae8bad Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 10 13:50:09 2013 -0700 Fix int15 return value for mainboard oprom handlers These boards were returning 0 to indicate success when the realmode handler expects it to return 1 to indicate that it handled the interrupt. Change-Id: I2baeaf8c2774fa7668a8b2f2d9ad698302eefb21 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50881 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4168 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4168 for details. -gerrit

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coreboot-gerrit November 2013