coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 86ce7f9 RTC: Skip rtc_init() in S3 resume path
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 86ce7f92735d4e0a3c6938cf7695b2805f5f48b4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 28 12:37:08 2013 -0700 RTC: Skip rtc_init() in S3 resume path In addition to not clearing the pending interrupts, we also don't want to reset the RTC control register when booting with an S3 resume. On most new systems, when the RTC well is losing power, we will also lose state that is required to perform a resume, so we end up in a normal boot anyways. Hence don't do any RTC initialization in the S3 resume path. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I73b486082faa741e9dccd15f2b8e3a8399c98f80 Reviewed-on: https://gerrit.chromium.org/gerrit/56826 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4206 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4206 for details. -gerrit

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Patch merged into coreboot/master: 7ae7fc0 x86: fix compile error for !CONFIG_MULTIBOOT
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 7ae7fc081b3832f1f6ba80eac8c92f788cbdd554 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 16:15:01 2013 -0500 x86: fix compile error for !CONFIG_MULTIBOOT Some code was previously removed regarding elf notes. However, that code left a dangling comma under !CONFIG_MULTIBOOT configs for inline assembly constraints. Instead, place the comma within the #ifdef stanza. Change-Id: I805453ef57d34fbfb904b4d145d8874921d8d660 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56844 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: David James <davidjames(a)chromium.org> Reviewed-on: http://review.coreboot.org/4207 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4207 for details. -gerrit

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Patch merged into coreboot/master: 680b0ab baskingridge: drop incorrect USB handling code
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 680b0ab72a1db04d4ce5be52131869e3d5d0135f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Nov 19 16:07:46 2013 -0800 baskingridge: drop incorrect USB handling code These GPIO accesses were copied by accident and don't make sense for the baskingridge board. Change-Id: I03bfc2cf97b6056a746a6c1a27308823ecaa9637 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4204 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4204 for details. -gerrit

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Patch merged into coreboot/master: c593999 lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQ
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit c593999a0ad9b9f19c8171f6229faa191d055491 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 24 11:06:49 2013 -0700 lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQ LynxPoint-LP has an additional 16 entries in the IOAPIC that can be assigned to specific GPIOs when they are configured as PIRQ. The maximum redirection entries field in the IOAPIC needs to be set to 0x27 when this is enabled. Additionally specific GPIOs need to be routed to PIRQ so they interrupt via the IOAPIC instead of the GPIO IRQ 14/15. Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56620 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4203 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4203 for details. -gerrit

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Patch merged into coreboot/master: 7820c77 wtm2: add ssdt2 table
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 7820c77f2c118d604d0acfce8deb40536cae3121 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 24 11:02:06 2013 -0500 wtm2: add ssdt2 table The LynxPoint southbridge ACPI code needs the SSDT2 table to function properly. Otherwise the ACPI evaluator in the kernel spews errors. Change-Id: I73918545a07e43f4a281ff34d8537340d601b102 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56601 Reviewed-on: http://review.coreboot.org/4188 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4188 for details. -gerrit

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Patch merged into coreboot/master: 21a7870 smbios: Add generic type41 write function
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 21a78706addd15fcc682f556566c303a463fcda1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 23 14:17:05 2013 -0700 smbios: Add generic type41 write function Mainboards were defining their own SMBIOS type41 write function. Instead pull this into the generic SMBIOS code and change the existing mainboards to make use of it. Change-Id: I3c8a95ca51fe2a3118dc8d1154011ccfed5fbcbc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56619 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4187 for details. -gerrit

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Patch merged into coreboot/master: 032be82 elog: Check for successful flash erase in elog_shrink
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 032be82a11a9cee6cc45df7a5ea94778ea4280d7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 23 07:23:09 2013 -0700 elog: Check for successful flash erase in elog_shrink A parrot device with a bad flash part has been seen to hang in the elog_shrink code becuase the flash was not successfully erased and it gets stuck in a loop trying to shrink the log and then add an event. Change-Id: I8bb13dbadd293f9d892f322e213c9255c8e9acb3 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56405 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4186 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4186 for details. -gerrit

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Patch merged into coreboot/master: b1c25e7 haswell: update pei_data data structure
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit b1c25e74af0a7b1cb4aae0fc9ab8147ee9d14907 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 23 15:57:46 2013 -0500 haswell: update pei_data data structure Update and use the new pei_data data structure. Now that the reference code is fixed it's possible to properly disable/enable the USB2 and USB3 ports correctly. Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56594 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4185 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4185 for details. -gerrit

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Patch merged into coreboot/master: 5290f71 falco: Initial mainboard commit
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 5290f71569d1bf8b6fa80d34f4b176407082fec8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 22 16:31:09 2013 -0700 falco: Initial mainboard commit - Only the first two DIMM SPDs are specified so far - GPIO map is updated - iSSD power sequencing removed - USB port map updated Change-Id: I4172460d3b075bfd5bb22013a6225cf0e8f95b9c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56329 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4184 for details. -gerrit

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Patch merged into coreboot/master: 619eca0 lynxpoint: fix mem corruption during ssdt2 gen
by gerrit＠coreboot.org 25 Nov '13

25 Nov '13

the following patch was just integrated into master: commit 619eca0685ef2c7777ff0d741730a29af5db05a0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 22 15:28:20 2013 -0500 lynxpoint: fix mem corruption during ssdt2 gen The ssdt2 generation code was calling acpigen_patch_len(). However, none of the entries had AML object lengths that needed patching. That resulted in the following message: ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c', line 52 Additionally, this caused an errant write to a memory address whose value was in the variable ltop. This was the 0 address. Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56299 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4182 for details. -gerrit

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coreboot-gerrit November 2013