the following patch was just integrated into master:
commit 0e939155a332c884b2a068da6a9fc89246c34cb7
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 7 13:28:56 2013 -0700
wtm2: Set SerialIO I2C ports to 3.3V
These are both pulled up to 3.3V in the schematic.
Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50356
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4164
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4164 for details.
-gerrit
the following patch was just integrated into master:
commit 8a0cb8de65572d6cb40cd36f06fa2567953eb390
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 7 11:14:01 2013 -0500
cbfstool: check potential microcode update earlier
The update-fit command takes in a parameter for number of slots
in the FIT table. It then processes the microcobe blob in cbfs
adding those entries to the FIT table. However, the tracking of
the number of mircocode updates was incremented before validating
the update. Therefore, move the sanity checking before an increment
of the number of updates.
Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50319
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4161
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4161 for details.
-gerrit
the following patch was just integrated into master:
commit 71b81bb64c44bc4150a1a19565a8732a361ae1f7
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 7 10:56:16 2013 -0500
x86: call cbfstool update-fit when fit selected
In order for the FIT entries to be populated in the table the
update-fit command needs to be done on the coreboot image. That
way the microcode entries are added to the table properly.
Change-Id: I44595aee1ca710f4f04d482d8900cf95fbc1797f
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50317
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4159
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4159 for details.
-gerrit
the following patch was just integrated into master:
commit 92e1f15175b3ab6fc50e3614c735d5e9cb3f3a22
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon May 6 14:02:27 2013 -0700
lynxpoint: Expose ACPI Device for LP GPIO controller
In order to probe the gpio-lynxpoint kernel driver the
LP GPIO controller needs to be exposed as a specific
ACPI device.
This also allows the resources to be exposed to the OS via
this device instead of the catch-all LPC device.
Ensure the driver loads at boot:
gpiochip_find_base: found new base at 162
gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00
Also ensure the driver is visible in sysfs:
$ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label
INT33C7:00
Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50215
Reviewed-on: http://review.coreboot.org/4158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4158 for details.
-gerrit
the following patch was just integrated into master:
commit f8b36501fd3f70569b15cc8dcaa9bcd8f76870af
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu May 2 14:02:28 2013 -0700
Make ssize_t an actual ssize_t
In the process of getting rid of compiler includes during in coreboot
and libpayload, we defined size_t and ssize_t ourselves, using a GCC
macro for size_t: __SIZE_TYPE__. Unfortunately, there is no
__SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make
__SIZE_TYPE__ __SSIZE_TYPE__.
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b
Reviewed-on: https://gerrit.chromium.org/gerrit/49947
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)google.com>
Tested-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/4156
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4156 for details.
-gerrit
the following patch was just integrated into master:
commit 118b382e7d3d126da3ea4adff375cf3065df8734
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu May 2 18:23:24 2013 -0700
call fill_lb_framebuffer() earlier
fill_lb_framebuffer() now sets the framebuffer pointer according to
the EDID information, so it must be called before setting the tag
and size.
(credit to rminnich for this, I'm just uploading it)
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: I5ac783fa3a776eee504d39889284041d1dc2c92a
Reviewed-on: https://gerrit.chromium.org/gerrit/50012
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4155
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4155 for details.
-gerrit
the following patch was just integrated into master:
commit 1d048ca56080488b525077c99f94cf478efa43ed
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 1 11:30:24 2013 -0700
lynxpoint: Move ME lock down to ramstage
Now that we have RW ramstage we don't need to have the
management engine lock down step done in a final SMM.
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
PCI: 00:16.0: Disabling device
Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49757
Reviewed-on: http://review.coreboot.org/4153
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4153 for details.
-gerrit
the following patch was just integrated into master:
commit 144f7b29ad995da897ec6c6ee4f87bed2ec7d28e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 1 11:27:58 2013 -0700
lynxpoint: Add missing ME MBP entries
There were two undefined MBP types that are now defined.
These include NFC status and some interesting timing data.
ME: Wake Event to ME Reset: 6 ms
ME: ME Reset to Platform Reset: 7 ms
ME: Platform Reset to CPU Reset: 51 ms
Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49756
Reviewed-on: http://review.coreboot.org/4152
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4152 for details.
-gerrit
the following patch was just integrated into master:
commit 764d009a615a3c1bdc42aef5506fc9b199bf5047
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed May 1 13:41:44 2013 -0500
lynxpoint: export mem console pointer in ACPI
Instead of having an OS re-parse cbmem book-keeping records
for the cbmem allocator just to get the console buffer export
the pointer to the memory console directly in a field named 'CBMC'.
This field lives in the GNVS table.
Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49764
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4149
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4149 for details.
-gerrit
the following patch was just integrated into master:
commit 8f4baece7acc3e0ee2e3f04a181ce51b59ec4667
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Apr 25 17:21:58 2013 -0700
elog: Make sure the elog data structures are initialized in elog_clear.
If elog_clear is called before other elog functions, for instance if it's
called through an SMI immediately after the system boots, then the elog data
structures won't have been set up and the system will go off the deep end.
This change adds a call to elog_init to elog_clear to make sure things things
are always initialized before we start using them.
Before this change, this command would cause
the system to lock up if run immediately after boot:
echo 1 > /sys/firmware/gsmi/clear_eventlog
After this change, that results in the log being cleared correctly.
Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49303
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4144
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4144 for details.
-gerrit