Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30934
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 6 files changed, 93 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/1
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index 0e2f6bd..e9013af 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -5,6 +5,7 @@
verstage-y += memlayout.ld verstage-y += chromeos.c +verstage-y += verstage.c
romstage-y += memlayout.ld romstage-y += chromeos.c diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c new file mode 100644 index 0000000..1fad7f5 --- /dev/null +++ b/src/mainboard/google/mistral/verstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <security/vboot/vboot_common.h> +#include <spi-generic.h> + +void verstage_mainboard_init(void) +{ + struct spi_slave spi; + printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n"); + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + } +} diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 270dad3..015632f 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -87,6 +87,9 @@ static struct qcs405_clock *const blsp1_uart2_clk = (void *)GCC_BLSP1_UART2_BASE;
+static struct qcs405_clock *const blsp1_qup0_spi_clk = + (void *)GCC_BLSP1_QUP0_SPI_BASE; + static struct qcs405_clock *const blsp2_qup0_spi_clk = (void *)GCC_BLSP2_QUP0_SPI_BASE;
@@ -207,6 +210,13 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA);
+ clock_configure(blsp1_qup0_spi_clk, spi_cfg, 50000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(REG(GCC_BLSP1_QUP0_SPI_APPS_CBCR)); + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP1_AHB_CLK_ENA); + clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 2736133..7e7af3f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -45,6 +45,7 @@ #define GCC_BLSP1_UART3_APPS_CBCR 0x180400C #define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C
+#define GCC_BLSP1_QUP0_SPI_APPS_CBCR 0x1802004 #define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004
#define GCC_BLSP1_AHB_CBCR 0x1801008 diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h index 5da709f..10f259b 100644 --- a/src/soc/qualcomm/qcs405/include/soc/spi.h +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -37,60 +37,80 @@ #include <spi-generic.h>
#define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP4_QUP_REG_BASE ((void *)0x78b9000u) #define BLSP5_QUP_REG_BASE ((void *)0x7af5000u)
#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP4_SPI_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000300) #define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300)
#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP4_SPI_IO_CONTROL_REG (BLSP4_QUP_REG_BASE + 0x00000304) #define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304)
#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP4_SPI_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x00000308) #define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308)
#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP4_SPI_DEASSERT_WAIT_REG (BLSP4_QUP_REG_BASE + 0x00000310) #define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) #define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP4_SPI_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x0000030c) #define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c)
#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP4_QUP_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000000) #define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000)
#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP4_QUP_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x0000001c) #define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c)
#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP4_QUP_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x00000020) #define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020)
#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP4_QUP_OPERATIONAL_MASK (BLSP4_QUP_REG_BASE + 0x00000028) #define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028)
#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP4_QUP_OPERATIONAL_REG (BLSP4_QUP_REG_BASE + 0x00000018) #define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018)
#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP4_QUP_IO_MODES_REG (BLSP4_QUP_REG_BASE + 0x00000008) #define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008)
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP4_QUP_STATE_REG (BLSP4_QUP_REG_BASE + 0x00000004) #define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004)
#define BLSP0_QUP_INPUT_FIFOc_REG(c) \ (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP4_QUP_INPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000218 + 4 * (c)) #define BLSP5_QUP_INPUT_FIFOc_REG(c) \ (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c))
#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP4_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000110 + 4 * (c)) #define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c))
#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP4_QUP_MX_INPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000200) #define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200)
#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP4_QUP_MX_OUTPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000100) #define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100)
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP4_QUP_SW_RESET_REG (BLSP4_QUP_REG_BASE + 0x0000000c) #define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c)
#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) @@ -138,6 +158,7 @@ #define SPI_MODE2 2 #define SPI_MODE3 3 #define BLSP0_SPI 0 +#define BLSP4_SPI 4 #define BLSP5_SPI 5
struct blsp_spi { diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 245569b..d4fb29e 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -60,7 +60,29 @@ BLSP0_QUP_OPERATIONAL_MASK, BLSP0_SPI_DEASSERT_WAIT_REG, }, - {0}, {0}, {0}, {0}, + {0}, {0}, {0}, + /* BLSP4 registers for SPI interface */ + { + BLSP4_SPI_CONFIG_REG, + BLSP4_SPI_IO_CONTROL_REG, + BLSP4_SPI_ERROR_FLAGS_REG, + BLSP4_SPI_ERROR_FLAGS_EN_REG, + BLSP4_QUP_CONFIG_REG, + BLSP4_QUP_ERROR_FLAGS_REG, + BLSP4_QUP_ERROR_FLAGS_EN_REG, + BLSP4_QUP_OPERATIONAL_REG, + BLSP4_QUP_IO_MODES_REG, + BLSP4_QUP_STATE_REG, + BLSP4_QUP_INPUT_FIFOc_REG(0), + BLSP4_QUP_OUTPUT_FIFOc_REG(0), + BLSP4_QUP_MX_INPUT_COUNT_REG, + BLSP4_QUP_MX_OUTPUT_COUNT_REG, + BLSP4_QUP_SW_RESET_REG, + 0, + 0, + BLSP4_QUP_OPERATIONAL_MASK, + BLSP4_SPI_DEASSERT_WAIT_REG, + }, /* BLSP5 registers for SPI interface */ { BLSP5_SPI_CONFIG_REG, @@ -202,7 +224,7 @@ check_qup_state_valid(ds); }
-static struct ipq_spi_slave spi_slave_pool[2]; +static struct ipq_spi_slave spi_slave_pool[3];
static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) { @@ -669,6 +691,7 @@ int i; unsigned int bus = slave->bus; unsigned int cs = slave->cs; + printk(BIOS_ERR, "trying to initialize SPI bus %d\n", bus);
if ((bus < BLSP0_SPI) || (bus > BLSP5_SPI) || ((bus == BLSP0_SPI) && (cs > 2)) @@ -694,6 +717,7 @@ * to configure this */ ds->freq = 10000000; + ds->freq = 800000; ds->mode = SPI_MODE0; ds->allocated = 1;
@@ -725,6 +749,11 @@ .bus_start = BLSP5_SPI, .bus_end = BLSP5_SPI, }, + { + .ctrlr = &spi_ctrlr, + .bus_start = BLSP4_SPI, + .bus_end = BLSP4_SPI, + }, };
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30934
to look at the new patch set (#4).
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 7 files changed, 113 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 4:
(8 comments)
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@337 PS4, Line 337: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@338 PS4, Line 338: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@339 PS4, Line 339: gpio_configure(GPIO(117), 2, GPIO_PULL_DOWN, GPIO_16MA, GPIO_INPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@340 PS4, Line 340: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@343 PS4, Line 343: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@344 PS4, Line 344: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@345 PS4, Line 345: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/4/src/soc/qualcomm/qcs405/spi.c@346 PS4, Line 346: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30934
to look at the new patch set (#5).
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 7 files changed, 113 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@337 PS5, Line 337: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@338 PS5, Line 338: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@339 PS5, Line 339: gpio_configure(GPIO(117), 2, GPIO_PULL_DOWN, GPIO_16MA, GPIO_INPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@340 PS5, Line 340: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@343 PS5, Line 343: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@344 PS5, Line 344: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@345 PS5, Line 345: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@346 PS5, Line 346: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30934
to look at the new patch set (#6).
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 8 files changed, 138 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 6:
(8 comments)
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@335 PS6, Line 335: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@336 PS6, Line 336: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@337 PS6, Line 337: gpio_configure(GPIO(117), 2, GPIO_PULL_DOWN, GPIO_16MA, GPIO_INPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@338 PS6, Line 338: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@341 PS6, Line 341: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@342 PS6, Line 342: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@343 PS6, Line 343: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/6/src/soc/qualcomm/qcs405/spi.c@344 PS6, Line 344: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30934
to look at the new patch set (#7).
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 8 files changed, 169 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 7:
(8 comments)
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@353 PS7, Line 353: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@354 PS7, Line 354: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@355 PS7, Line 355: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@356 PS7, Line 356: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@359 PS7, Line 359: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@360 PS7, Line 360: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@361 PS7, Line 361: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@362 PS7, Line 362: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 7: Code-Review+2
(3 comments)
https://review.coreboot.org/#/c/30934/7/src/mainboard/google/mistral/verstag... File src/mainboard/google/mistral/verstage.c:
https://review.coreboot.org/#/c/30934/7/src/mainboard/google/mistral/verstag... PS7, Line 4: 2016 Google Inc. Nit: If significant changes were made, you might want to update the copyright.
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/include/soc/... File src/soc/qualcomm/qcs405/include/soc/spi.h:
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/include/soc/... PS7, Line 39: (void *) Unrelated to this change, but I think these should be bare numbers to avoid void pointer math.
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/7/src/soc/qualcomm/qcs405/spi.c@253 PS7, Line 253: #if 0 Nit: I know it's just moving the function, but maybe remove the dead code or comment why it's here? Since it is a move, i'll leave it up to you.
Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30934
to look at the new patch set (#8).
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 7 files changed, 182 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 8:
(8 comments)
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@353 PS8, Line 353: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@354 PS8, Line 354: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@355 PS8, Line 355: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@356 PS8, Line 356: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@359 PS8, Line 359: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@360 PS8, Line 360: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@361 PS8, Line 361: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/8/src/soc/qualcomm/qcs405/spi.c@362 PS8, Line 362: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 9:
(8 comments)
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@353 PS9, Line 353: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@354 PS9, Line 354: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@355 PS9, Line 355: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@356 PS9, Line 356: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@359 PS9, Line 359: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@360 PS9, Line 360: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@361 PS9, Line 361: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@362 PS9, Line 362: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
SANTHOSH JANARDHANA HASSAN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/9/src/soc/qualcomm/qcs405/spi.c@490 PS9, Line 490: if (val & OUTPUT_SERVICE_FLAG) { https://b.corp.google.com/issues/122992916#comment58. Is this change required? Didn't find in the change in Qualcomm patch.
nsekar@codeaurora.org has uploaded a new patch set (#10) to the change originally created by Patrick Georgi. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 6 files changed, 103 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/10
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 10:
(13 comments)
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@341 PS10, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@341 PS10, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@341 PS10, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@342 PS10, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@342 PS10, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@342 PS10, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@343 PS10, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@343 PS10, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@343 PS10, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@344 PS10, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@344 PS10, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@344 PS10, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/10/src/soc/qualcomm/qcs405/spi.c@345 PS10, Line 345: break; trailing whitespace
SANTHOSH JANARDHANA HASSAN has uploaded a new patch set (#11) to the change originally created by Patrick Georgi. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 9 files changed, 206 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/11
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 11:
(15 comments)
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@354 PS11, Line 354: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@355 PS11, Line 355: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@356 PS11, Line 356: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@357 PS11, Line 357: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@360 PS11, Line 360: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@361 PS11, Line 361: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@362 PS11, Line 362: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@363 PS11, Line 363: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@514 PS11, Line 514: printk(BIOS_ERR, "SPI FIFO read timeout \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@518 PS11, Line 518: }while(!(val & MAX_INPUT_DONE_FLAG)); space required after that close brace '}'
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@518 PS11, Line 518: }while(!(val & MAX_INPUT_DONE_FLAG)); space required before the open parenthesis '('
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@640 PS11, Line 640: printk(BIOS_ERR, "SPI FIFO write timeout \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@644 PS11, Line 644: }while(!(val & MAX_OUTPUT_DONE_FLAG)); space required after that close brace '}'
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@644 PS11, Line 644: }while(!(val & MAX_OUTPUT_DONE_FLAG)); space required before the open parenthesis '('
https://review.coreboot.org/#/c/30934/11/src/soc/qualcomm/qcs405/spi.c@666 PS11, Line 666: printk(BIOS_ERR, "SPI:DBG write not success \n"); unnecessary whitespace before a quoted newline
nsekar@codeaurora.org has uploaded a new patch set (#12) to the change originally created by Patrick Georgi. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 6 files changed, 103 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 12:
(13 comments)
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@341 PS12, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@341 PS12, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@341 PS12, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@342 PS12, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@342 PS12, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@342 PS12, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@343 PS12, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@343 PS12, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@343 PS12, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@344 PS12, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@344 PS12, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@344 PS12, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/12/src/soc/qualcomm/qcs405/spi.c@345 PS12, Line 345: break; trailing whitespace
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/#/c/30934/11/src/mainboard/google/mistral/versta... File src/mainboard/google/mistral/verstage.c:
https://review.coreboot.org/#/c/30934/11/src/mainboard/google/mistral/versta... PS11, Line 40: setup set up
Hello SANTHOSH JANARDHANA HASSAN, build bot (Jenkins), nsekar@codeaurora.org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30934
to look at the new patch set (#13).
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 7 files changed, 125 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/13
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 13:
(8 comments)
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@351 PS13, Line 351: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@352 PS13, Line 352: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@353 PS13, Line 353: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@354 PS13, Line 354: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@357 PS13, Line 357: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@358 PS13, Line 358: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@359 PS13, Line 359: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/13/src/soc/qualcomm/qcs405/spi.c@360 PS13, Line 360: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
nsekar@codeaurora.org has uploaded a new patch set (#14) to the change originally created by Patrick Georgi. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 6 files changed, 103 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/14
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 14:
(13 comments)
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@341 PS14, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@341 PS14, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@341 PS14, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@342 PS14, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@342 PS14, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@342 PS14, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@343 PS14, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@343 PS14, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@343 PS14, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@344 PS14, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@344 PS14, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@344 PS14, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/14/src/soc/qualcomm/qcs405/spi.c@345 PS14, Line 345: break; trailing whitespace
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 15:
(8 comments)
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@351 PS15, Line 351: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@352 PS15, Line 352: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@353 PS15, Line 353: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@354 PS15, Line 354: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@357 PS15, Line 357: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@358 PS15, Line 358: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@359 PS15, Line 359: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/15/src/soc/qualcomm/qcs405/spi.c@360 PS15, Line 360: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 16:
(8 comments)
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@351 PS16, Line 351: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@352 PS16, Line 352: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@353 PS16, Line 353: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@354 PS16, Line 354: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@357 PS16, Line 357: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@358 PS16, Line 358: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@359 PS16, Line 359: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/16/src/soc/qualcomm/qcs405/spi.c@360 PS16, Line 360: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 17:
(13 comments)
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@341 PS17, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@341 PS17, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@341 PS17, Line 341: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@342 PS17, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@342 PS17, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@342 PS17, Line 342: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@343 PS17, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@343 PS17, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@343 PS17, Line 343: gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@344 PS17, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@344 PS17, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@344 PS17, Line 344: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/30934/17/src/soc/qualcomm/qcs405/spi.c@345 PS17, Line 345: break; trailing whitespace
nsekar@codeaurora.org has uploaded a new patch set (#19) to the change originally created by Patrick Georgi. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: TEMP: NOT FOR REVIEW: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
TEMP: NOT FOR REVIEW: qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 7 files changed, 127 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/19
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 28: Code-Review+2
Nitheesh Sekar has uploaded a new patch set (#29) to the change originally created by Patrick Georgi. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c 2 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/29
Stefan Reinauer has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi pgeorgi@google.com Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934 Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c 2 files changed, 32 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index 2cb9631..ca191d1 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -7,6 +7,7 @@ verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += reset.c +verstage-y += verstage.c
romstage-y += memlayout.ld romstage-y += chromeos.c diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c new file mode 100644 index 0000000..a34e4fa --- /dev/null +++ b/src/mainboard/google/mistral/verstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <security/vboot/vboot_common.h> +#include <soc/clock.h> +#include <spi-generic.h> + +void verstage_mainboard_init(void) +{ + struct spi_slave spi; + + printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n"); + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + } +}
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build bot (Jenkins) (Code Review) -
Martin Roth (Code Review)
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Name of user not set (Code Review)
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Nitheesh Sekar (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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SANTHOSH JANARDHANA HASSAN (Code Review)
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Stefan Reinauer (Code Review)