Patrick Georgi has uploaded this change for review.
qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
---
M src/mainboard/google/mistral/Makefile.inc
A src/mainboard/google/mistral/verstage.c
M src/soc/qualcomm/qcs405/clock.c
M src/soc/qualcomm/qcs405/include/soc/clock.h
M src/soc/qualcomm/qcs405/include/soc/spi.h
M src/soc/qualcomm/qcs405/spi.c
6 files changed, 93 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/1
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc
index 0e2f6bd..e9013af 100644
--- a/src/mainboard/google/mistral/Makefile.inc
+++ b/src/mainboard/google/mistral/Makefile.inc
@@ -5,6 +5,7 @@
verstage-y += memlayout.ld
verstage-y += chromeos.c
+verstage-y += verstage.c
romstage-y += memlayout.ld
romstage-y += chromeos.c
diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c
new file mode 100644
index 0000000..1fad7f5
--- /dev/null
+++ b/src/mainboard/google/mistral/verstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+#include <security/vboot/vboot_common.h>
+#include <spi-generic.h>
+
+void verstage_mainboard_init(void)
+{
+ struct spi_slave spi;
+ printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n");
+ if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS,
+ CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) {
+ printk(BIOS_ERR, "Failed to setup TPM SPI slave\n");
+ }
+}
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index 270dad3..015632f 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -87,6 +87,9 @@
static struct qcs405_clock *const blsp1_uart2_clk =
(void *)GCC_BLSP1_UART2_BASE;
+static struct qcs405_clock *const blsp1_qup0_spi_clk =
+ (void *)GCC_BLSP1_QUP0_SPI_BASE;
+
static struct qcs405_clock *const blsp2_qup0_spi_clk =
(void *)GCC_BLSP2_QUP0_SPI_BASE;
@@ -207,6 +210,13 @@
REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE),
BLSP1_AHB_CLK_ENA);
+ clock_configure(blsp1_qup0_spi_clk, spi_cfg, 50000000,
+ ARRAY_SIZE(spi_cfg));
+ clock_enable(REG(GCC_BLSP1_QUP0_SPI_APPS_CBCR));
+ clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR),
+ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE),
+ BLSP1_AHB_CLK_ENA);
+
clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000,
ARRAY_SIZE(spi_cfg));
clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR));
diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h
index 2736133..7e7af3f 100644
--- a/src/soc/qualcomm/qcs405/include/soc/clock.h
+++ b/src/soc/qualcomm/qcs405/include/soc/clock.h
@@ -45,6 +45,7 @@
#define GCC_BLSP1_UART3_APPS_CBCR 0x180400C
#define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C
+#define GCC_BLSP1_QUP0_SPI_APPS_CBCR 0x1802004
#define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004
#define GCC_BLSP1_AHB_CBCR 0x1801008
diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h
index 5da709f..10f259b 100644
--- a/src/soc/qualcomm/qcs405/include/soc/spi.h
+++ b/src/soc/qualcomm/qcs405/include/soc/spi.h
@@ -37,60 +37,80 @@
#include <spi-generic.h>
#define BLSP0_QUP_REG_BASE ((void *)0x78b5000u)
+#define BLSP4_QUP_REG_BASE ((void *)0x78b9000u)
#define BLSP5_QUP_REG_BASE ((void *)0x7af5000u)
#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300)
+#define BLSP4_SPI_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000300)
#define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300)
#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304)
+#define BLSP4_SPI_IO_CONTROL_REG (BLSP4_QUP_REG_BASE + 0x00000304)
#define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304)
#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308)
+#define BLSP4_SPI_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x00000308)
#define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308)
#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310)
+#define BLSP4_SPI_DEASSERT_WAIT_REG (BLSP4_QUP_REG_BASE + 0x00000310)
#define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310)
#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c)
+#define BLSP4_SPI_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x0000030c)
#define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c)
#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000)
+#define BLSP4_QUP_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000000)
#define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000)
#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c)
+#define BLSP4_QUP_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x0000001c)
#define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c)
#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020)
+#define BLSP4_QUP_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x00000020)
#define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020)
#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028)
+#define BLSP4_QUP_OPERATIONAL_MASK (BLSP4_QUP_REG_BASE + 0x00000028)
#define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028)
#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018)
+#define BLSP4_QUP_OPERATIONAL_REG (BLSP4_QUP_REG_BASE + 0x00000018)
#define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018)
#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
+#define BLSP4_QUP_IO_MODES_REG (BLSP4_QUP_REG_BASE + 0x00000008)
#define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008)
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
+#define BLSP4_QUP_STATE_REG (BLSP4_QUP_REG_BASE + 0x00000004)
#define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004)
#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
(BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
+#define BLSP4_QUP_INPUT_FIFOc_REG(c) \
+ (BLSP4_QUP_REG_BASE + 0x00000218 + 4 * (c))
#define BLSP5_QUP_INPUT_FIFOc_REG(c) \
(BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c))
#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
(BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
+#define BLSP4_QUP_OUTPUT_FIFOc_REG(c) \
+ (BLSP4_QUP_REG_BASE + 0x00000110 + 4 * (c))
#define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \
(BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c))
#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200)
+#define BLSP4_QUP_MX_INPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000200)
#define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200)
#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
+#define BLSP4_QUP_MX_OUTPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000100)
#define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100)
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
+#define BLSP4_QUP_SW_RESET_REG (BLSP4_QUP_REG_BASE + 0x0000000c)
#define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c)
#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
@@ -138,6 +158,7 @@
#define SPI_MODE2 2
#define SPI_MODE3 3
#define BLSP0_SPI 0
+#define BLSP4_SPI 4
#define BLSP5_SPI 5
struct blsp_spi {
diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c
index 245569b..d4fb29e 100644
--- a/src/soc/qualcomm/qcs405/spi.c
+++ b/src/soc/qualcomm/qcs405/spi.c
@@ -60,7 +60,29 @@
BLSP0_QUP_OPERATIONAL_MASK,
BLSP0_SPI_DEASSERT_WAIT_REG,
},
- {0}, {0}, {0}, {0},
+ {0}, {0}, {0},
+ /* BLSP4 registers for SPI interface */
+ {
+ BLSP4_SPI_CONFIG_REG,
+ BLSP4_SPI_IO_CONTROL_REG,
+ BLSP4_SPI_ERROR_FLAGS_REG,
+ BLSP4_SPI_ERROR_FLAGS_EN_REG,
+ BLSP4_QUP_CONFIG_REG,
+ BLSP4_QUP_ERROR_FLAGS_REG,
+ BLSP4_QUP_ERROR_FLAGS_EN_REG,
+ BLSP4_QUP_OPERATIONAL_REG,
+ BLSP4_QUP_IO_MODES_REG,
+ BLSP4_QUP_STATE_REG,
+ BLSP4_QUP_INPUT_FIFOc_REG(0),
+ BLSP4_QUP_OUTPUT_FIFOc_REG(0),
+ BLSP4_QUP_MX_INPUT_COUNT_REG,
+ BLSP4_QUP_MX_OUTPUT_COUNT_REG,
+ BLSP4_QUP_SW_RESET_REG,
+ 0,
+ 0,
+ BLSP4_QUP_OPERATIONAL_MASK,
+ BLSP4_SPI_DEASSERT_WAIT_REG,
+ },
/* BLSP5 registers for SPI interface */
{
BLSP5_SPI_CONFIG_REG,
@@ -202,7 +224,7 @@
check_qup_state_valid(ds);
}
-static struct ipq_spi_slave spi_slave_pool[2];
+static struct ipq_spi_slave spi_slave_pool[3];
static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave)
{
@@ -669,6 +691,7 @@
int i;
unsigned int bus = slave->bus;
unsigned int cs = slave->cs;
+ printk(BIOS_ERR, "trying to initialize SPI bus %d\n", bus);
if ((bus < BLSP0_SPI) || (bus > BLSP5_SPI)
|| ((bus == BLSP0_SPI) && (cs > 2))
@@ -694,6 +717,7 @@
* to configure this
*/
ds->freq = 10000000;
+ ds->freq = 800000;
ds->mode = SPI_MODE0;
ds->allocated = 1;
@@ -725,6 +749,11 @@
.bus_start = BLSP5_SPI,
.bus_end = BLSP5_SPI,
},
+ {
+ .ctrlr = &spi_ctrlr,
+ .bus_start = BLSP4_SPI,
+ .bus_end = BLSP4_SPI,
+ },
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
To view, visit change 30934. To unsubscribe, or for help writing mail filters, visit settings.