Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to review the following change.
Change subject: [WIP] autoport: Add BroadWell SoC support ......................................................................
[WIP] autoport: Add BroadWell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- A util/autoport/soc_broadwell.go 1 file changed, 420 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/1
diff --git a/util/autoport/soc_broadwell.go b/util/autoport/soc_broadwell.go new file mode 100644 index 0000000..ee61407 --- /dev/null +++ b/util/autoport/soc_broadwell.go @@ -0,0 +1,420 @@ +package main + +import "fmt" +import "os" + +type broadwellsoc struct {} + +/* FIXME: southbridge interface */ +func (bdw broadwellsoc) GetGPIOHeader() string { + return "soc/pch.h" +} + +func (bdw broadwellsoc) EncodeGPE(in int) int { + return in + 0x10 +} + +func (bdw broadwellsoc) DecodeGPE(in int) int { + return in + 0x10 +} + +func (bdw broadwellsoc) EnableGPE(in int) { +} + +func (bdw broadwellsoc) NeedRouteGPIOManually() { +} + +func PrintUSB2(pei *os.File, inteltool InteltoolData) { + pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64] + ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78] + + xusb2pr := GetLE16(PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xd0:0xd4]) + + for port := 0; port < 8; port++ { + var port_oc int = -1 + var port_pos string + var port_disable uint8 + + port_disable = ((pdo1 >> port) & (uint8(xusb2pr>>port) ^ 1)) & 1 + for oc := 0; oc < 4; oc++ { + if (ocmap1[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + + /* get USB2 port length and location from IOBP */ + /* FIXME: the following is from LPT-LP */ + port_iobp := inteltool.IOBP[0xe5004100+uint32(port)*0x100] + loc_param := (port_iobp >> 8) & 7 + txamp := (port_iobp >> 11) & 7 + var port_length int + + if loc_param == 6 { + /* back panel or mini pcie, length >= 0x70 */ + port_pos = "USB_PORT_MINI_PCIE" + if txamp <= 2 { + port_length = 0x80 + } else { + port_length = 0x110 + } + } else if loc_param == 4 { + port_pos = "USB_PORT_DOCK" + if txamp <= 1 { + port_length = 0x40 + } else { + port_length = 0x80 + } + } else { + port_pos = "USB_PORT_BACK_PANEL" + port_length = 0x40 + } + + if port_disable == 1 { + port_pos = "USB_PORT_SKIP" + } + + if port_oc == -1 { + fmt.Fprintf(pei, "\tpei_data_usb2_port(pei_data, %d, 0x%04x, %d, USB_OC_PIN_SKIP,\n\t\t\t %s);\n", + port, port_length, (port_disable ^ 1), port_pos) + } else { + fmt.Fprintf(pei, "\tpei_data_usb2_port(pei_data, %d, 0x%04x, %d, %d,\n\t\t\t %s);\n", + port, port_length, (port_disable ^ 1), port_oc, port_pos) + } + } +} + +func PrintUSB3(pei *os.File) { + xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8] + u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0] + + for port := 0; port < 4; port++ { + var port_oc int = -1 + port_disable := (xpdo >> port) & 1 + for oc := 0; oc < 8; oc++ { + if (u3ocm[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + /* FIXME: how to get the fix_eq value? */ + if port_oc == -1 { + fmt.Fprintf(pei, "\tpei_data_usb3_port(pei_data, %d, %d, USB_OC_PIN_SKIP, 0);\n", + port, (port_disable ^ 1)) + } else { + fmt.Fprintf(pei, "\tpei_data_usb3_port(pei_data, %d, %d, %d, 0);\n", + port, (port_disable ^ 1), port_oc) + } + } +} + +func AddBroadwellPEIData(ctx Context, inteltool InteltoolData) { + pei := Create(ctx, "pei_data.c") + defer pei.Close() + + AddROMStageFile("pei_data.c", "") + AddRAMStageFile("pei_data.c", "") + + Add_gpl(pei) + pei.WriteString(`#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* FIXME: check these values */ + pei_data->dimm_channel0_disabled = 0; + pei_data->dimm_channel1_disabled = 0; + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0xa2; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0xa6; + pei_data->dq_pins_interleaved = 0; + + /* FIXME: USB2 ports */ +`) + PrintUSB2(pei, inteltool) + + pei.WriteString(` + /* FIXME: USB3 ports */ +`) + PrintUSB3(pei) + + pei.WriteString(`} +`) +} + +func BDWLPGPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString(`#include <soc/gpio.h> + +const struct gpio_config mainboard_gpio_config[] = { +`) + PrintLPGPIO(gpio, inteltool, "PCH") + gpio.WriteString("\tPCH_GPIO_END\n};\n") +} + +func (bdw broadwellsoc) Scan(ctx Context, addr PCIDevData) { + SouthBridge = &bdw + + inteltool := ctx.InfoSource.GetInteltool() + + BDWLPGPIO(ctx, inteltool) + + /* FIXME:XX Move this somewhere else. */ + MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") + MainboardEnable += (` /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +`) + + romstage := Create(ctx, "romstage.c") + defer romstage.Close() + Add_gpl(romstage) + romstage.WriteString(`#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> + +void mainboard_pre_raminit(struct romstage_params *rp) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(&rp->pei_data); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} +`) + + acpi := Create(ctx, "acpi_tables.c") + defer acpi.Close() + Add_gpl(acpi) + acpi.WriteString(`#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} +`) + + var refclk uint32 + var pwm_hz uint32 + refclk = 24000000 + + if (inteltool.IGD[0xc8254] >> 16) != 0 { + pwm_hz = refclk / 128 / (inteltool.IGD[0xc8254] >> 16) + } else { + pwm_hz = 0 + } + + /* FIXME */ + sata_dtle := []uint32{0,0,0,0} + sata_tx := []uint32{0,0,0,0} + + DevTree = DevTreeNode{ + Chip: "soc/intel/broadwell", + MissingParent: "northbridge", + Comment: "FIXME: check these values", + Registers: map[string]string{ + /* power management */ + "gpe0_en_1": "0", + "gpe0_en_2": "0", + "gpe0_en_3": "0", + "gpe0_en_4": "0", + "alt_gp_smi_en": "0", + /* SATA */ + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + "sata_port0_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]), + "sata_port1_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]), + "sata_port2_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]), + "sata_port3_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]), + "sata_port0_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[0]), + "sata_port1_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[1]), + "sata_port2_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[2]), + "sata_port3_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[3]), + "sata_devslp_mux": "0", + "sata_devslp_disable": "0", + /* I/O decode */ + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + /* PCIe */ + "pcie_port_coalesce": "1", + "pcie_port_force_aspm": "0", + /* serial I/O */ + "sio_acpi_mode": "0", + "sio_i2c0_voltage": "0", + "sio_i2c1_voltage": "0", + /* graphics */ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), + "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), + "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), + "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), + "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), + "gpu_pch_backlight_pwm_hz": FormatInt32(pwm_hz), + "gfx": "GMA_STATIC_DISPLAYS(0)", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true }, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x13, Func: 0}, writeEmpty: true, additionalComment: "Smart Sound Audio DSP"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: true, additionalComment: "xHCI Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 0}, writeEmpty: true, additionalComment: "Serial I/O DMA"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 1}, writeEmpty: true, additionalComment: "I2C0"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 2}, writeEmpty: true, additionalComment: "I2C1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 3}, writeEmpty: true, additionalComment: "GSPI0"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 4}, writeEmpty: true, additionalComment: "GSPI1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 5}, writeEmpty: true, additionalComment: "UART0"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 6}, writeEmpty: true, additionalComment: "UART1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x17, Func: 0}, writeEmpty: true, additionalComment: "SDIO"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller (AHCI)"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + }, + }, + } + + PutPCIDev(addr, "Host bridge") + + KconfigBool["SOC_INTEL_BROADWELL"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + lpPchGetFlashSize(ctx) + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "soc/intel/broadwell/acpi/platform.asl", + }, DSDTInclude{ + File: "soc/intel/broadwell/acpi/globalnvs.asl", + }, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }, DSDTInclude{ + File: "southbridge/intel/common/acpi/sleepstates.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "soc/intel/broadwell/acpi/systemagent.asl", + }, DSDTInclude{ + File: "soc/intel/broadwell/acpi/pch.asl", + }) + + AddBroadwellPEIData(ctx, inteltool) +} + +func init() { + /* Host bridge */ + RegisterPCI(0x8086, 0x1604, broadwellsoc{}) + /* Graphics */ + for _, id := range []uint16{ + 0x1606, 0x1616, 0x1626, 0x162b, + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + } + /* Audio */ + RegisterPCI(0x8086, 0x160c, GenericPCI{}) + /* SATA */ + for _, id := range []uint16{ + 0x9c83, 0x9c85, 0x9c87, 0x9c8f, 0x282a, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + /* PCIe */ + for _, id := range []uint16{ + 0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, + 0x2448, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + /* HD audio */ + RegisterPCI(0x8086, 0x9ca0, azalia{}) + /* SMBus */ + RegisterPCI(0x8086, 0x9ca2, GenericPCI{}) + /* Thermal */ + RegisterPCI(0x8086, 0x9ca4, GenericPCI{}) + /* EHCI */ + RegisterPCI(0x8086, 0x9ca6, GenericPCI{}) + /* xHCI */ + RegisterPCI(0x8086, 0x9cb1, GenericPCI{}) + /* LAN */ + RegisterPCI(0x8086, 0x155a, GenericPCI{}) + /* SDIO */ + RegisterPCI(0x8086, 0x9cb5, GenericPCI{}) + /* Intel Smart Sound Technology*/ + RegisterPCI(0x8086, 0x9cb6, GenericPCI{}) + /* Intel ME and children */ + for id := uint16(0x9cba); id <= 0x9cbd; id++ { + RegisterPCI(0x8086, id, GenericPCI{}) + } + /* LPC */ + for _, id := range []uint16{ + 0x9cc1, 0x9cc2, 0x9cc3, 0x9cc5, + 0x9cc6, 0x9cc7, 0x9cc9, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + /* Serial I/O */ + for id := uint16(0x9ce0); id <= 0x9ce6; id++ { + RegisterPCI(0x8086, id, GenericPCI{}) + } +}
Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#2).
Change subject: [WIP] autoport: Add BroadWell SoC support ......................................................................
[WIP] autoport: Add BroadWell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 467 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/2
Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#3).
Change subject: [WIP] autoport: Add BroadWell SoC support ......................................................................
[WIP] autoport: Add BroadWell SoC support
Not tested.
We need to remove mb/platform.asl in dsdt.asl to make the code buildable, because Broadwell SoC ACPI code has _WAK and _PTS defined.
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 404 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/3
Attention is currently required from: Iru Cai (vimacs). Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: [WIP] autoport: Add BroadWell SoC support ......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/46832/comment/288a6c30_4ec962a3 PS3, Line 7: BroadWell Broadwell
Attention is currently required from: Iru Cai (vimacs). Juanita Harvey has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: [WIP] autoport: Add BroadWell SoC support ......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3: thank you so much. u r awesome
Attention is currently required from: Iru Cai (vimacs). Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#4).
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
[WIP] autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 421 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/4
Attention is currently required from: Paul Menzel. Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/46832/comment/10634694_6112b7fc PS3, Line 7: BroadWell
Broadwell
Done
Attention is currently required from: Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
Patch Set 4:
(3 comments)
File util/autoport/wildcatpoint.go:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117812): https://review.coreboot.org/c/coreboot/+/46832/comment/6545aade_54ecddf8 PS4, Line 266: Comment: "Splitted from soc/intel/broadwell/acpi/platform.asl", 'Splitted' may be misspelled - perhaps 'Split'?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117812): https://review.coreboot.org/c/coreboot/+/46832/comment/047931d7_c4915201 PS4, Line 269: Comment: "Splitted from soc/intel/broadwell/acpi/platform.asl", 'Splitted' may be misspelled - perhaps 'Split'?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117812): https://review.coreboot.org/c/coreboot/+/46832/comment/9f30e4df_81e933a1 PS4, Line 272: Comment: "Splitted from soc/intel/broadwell/acpi/platform.asl", 'Splitted' may be misspelled - perhaps 'Split'?
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#5).
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
[WIP] autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 426 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/5
Attention is currently required from: Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
Patch Set 5:
(3 comments)
File util/autoport/wildcatpoint.go:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119487): https://review.coreboot.org/c/coreboot/+/46832/comment/dfa7b1b5_996a1fd5 PS5, Line 271: Comment: "Splitted from soc/intel/broadwell/acpi/platform.asl", 'Splitted' may be misspelled - perhaps 'Split'?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119487): https://review.coreboot.org/c/coreboot/+/46832/comment/caec7d0a_48b2ecca PS5, Line 274: Comment: "Splitted from soc/intel/broadwell/acpi/platform.asl", 'Splitted' may be misspelled - perhaps 'Split'?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119487): https://review.coreboot.org/c/coreboot/+/46832/comment/e34b37fc_0e535a91 PS5, Line 277: Comment: "Splitted from soc/intel/broadwell/acpi/platform.asl", 'Splitted' may be misspelled - perhaps 'Split'?
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#6).
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
[WIP] autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 435 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/6
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: [WIP] autoport: Add Broadwell SoC support ......................................................................
[WIP] autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 424 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/7
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#8).
Change subject: autoport: Add Broadwell SoC support ......................................................................
autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 425 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/8
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#9).
Change subject: autoport: Add Broadwell SoC support ......................................................................
autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 434 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/9
Attention is currently required from: Paul Menzel, Iru Cai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Patch Set 9:
(4 comments)
File util/autoport/wildcatpoint.go:
https://review.coreboot.org/c/coreboot/+/46832/comment/c6b44125_72beaadf PS9, Line 43: if bdw.variant == CORE_M { : nPorts = 10 : } else { : nPorts = 8 : } Where does this information come from?
https://review.coreboot.org/c/coreboot/+/46832/comment/7aa3940b_0360f600 PS9, Line 148: /* FIXME: check these values */ : pei_data->dimm_channel0_disabled = 0; : pei_data->dimm_channel1_disabled = 0; : pei_data->spd_addresses[0] = 0xa0; : pei_data->spd_addresses[1] = 0xa2; : pei_data->spd_addresses[2] = 0xa4; : pei_data->spd_addresses[3] = 0xa6; Broadwell ULT/ULX only supports 1 DIMM per channel. I'd just write:
/* FIXME: check these values */ pei_data->dimm_channel0_disabled = 2; pei_data->dimm_channel1_disabled = 2; pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4;
https://review.coreboot.org/c/coreboot/+/46832/comment/6235ac60_edd5452e PS9, Line 237: "pcie_port_coalesce": "1", Why enabled by default?
https://review.coreboot.org/c/coreboot/+/46832/comment/42609ea6_6bd7b1d1 PS9, Line 287: Split from soc/intel/broadwell/acpi/platform.asl Why?
Attention is currently required from: Paul Menzel, Iru Cai. Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46832
to look at the new patch set (#10).
Change subject: autoport: Add Broadwell SoC support ......................................................................
autoport: Add Broadwell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d Signed-off-by: Iru Cai mytbk920423@gmail.com --- M util/autoport/azalia.go A util/autoport/broadwell.go A util/autoport/wildcatpoint.go 3 files changed, 429 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/10
Attention is currently required from: Paul Menzel, Angel Pons. Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Patch Set 10:
(3 comments)
File util/autoport/wildcatpoint.go:
https://review.coreboot.org/c/coreboot/+/46832/comment/612ede10_77200b6f PS9, Line 43: if bdw.variant == CORE_M { : nPorts = 10 : } else { : nPorts = 8 : }
Where does this information come from?
Mobile 5th Generation Intel Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor Family I/O Datasheet (330837-004), 1.3 SKU Definition.
Table 1-2 (Mobile 5th Generation Intel Core Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Intel Celeron Processor Family I/O SKUs (U-Processor Line)) says U-processor has 8 USB ports. Table 1-4 (Intel Core M Processor I/O Platform SKUs) says Core M has 10 USB ports.
https://review.coreboot.org/c/coreboot/+/46832/comment/da6d236e_905a227d PS9, Line 237: "pcie_port_coalesce": "1",
Why enabled by default?
I see many boards set this.
https://review.coreboot.org/c/coreboot/+/46832/comment/60e8b37a_3988dcea PS9, Line 287: Split from soc/intel/broadwell/acpi/platform.asl
Why?
I see librem_bdw uses one broadwell/acpi/platform.asl, which is the combination of soc/intel/broadwell/acpi/device_nvs.asl, southbridge/intel/common/acpi/platform.asl, soc/intel/common/acpi/acpi_wake_source.asl, and empty _WAK and _PTS (which are generated in mainboard acpi/platform.asl).
I can see google/jecht has all these asl files except acpi_wake_source.asl.
Comments are removed now.
Attention is currently required from: Paul Menzel, Angel Pons. Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Patch Set 10:
(1 comment)
File util/autoport/wildcatpoint.go:
https://review.coreboot.org/c/coreboot/+/46832/comment/c53a16a4_02ed6a71 PS9, Line 148: /* FIXME: check these values */ : pei_data->dimm_channel0_disabled = 0; : pei_data->dimm_channel1_disabled = 0; : pei_data->spd_addresses[0] = 0xa0; : pei_data->spd_addresses[1] = 0xa2; : pei_data->spd_addresses[2] = 0xa4; : pei_data->spd_addresses[3] = 0xa6;
Broadwell ULT/ULX only supports 1 DIMM per channel. I'd just write: […]
Done
Attention is currently required from: Angel Pons, Iru Cai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/46832/comment/2eb781cc_4c70723c PS10, Line 8: Did you successfully create a port with this change?
Attention is currently required from: Iru Cai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Patch Set 10:
(1 comment)
File util/autoport/wildcatpoint.go:
https://review.coreboot.org/c/coreboot/+/46832/comment/43ebe892_921fa314 PS9, Line 237: "pcie_port_coalesce": "1",
I see many boards set this.
Coalescing is only needed if PCIe root port 1 (function 0) is disabled. The PCI spec (I don't remember which) requires that function 0 of a multi-function device be present, so Intel southbridges/PCHs have a mechanism to change root port function numbers. On WPT-LP and earlier, the RPFN (Root Port Function Number) register controls this.
I don't think autoport knows about coalescing. When vendor firmware uses coalescing, autoport enables the wrong PCIe root ports.
I'd enable coalescing when the RPFN register differs from its reset default value, and also tell the user to double-check the PCH PCIe root ports. Or even (pretty-)print the RPFN value, which one can use to manually fix up the devicetree?
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46832?usp=email )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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