Iru Cai (vimacs) would like Iru Cai to review this change.
[WIP] autoport: Add BroadWell SoC support
Change-Id: I62ab51b8a9c5873695bd7d75543c452ec422f11d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
---
A util/autoport/soc_broadwell.go
1 file changed, 420 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46832/1
diff --git a/util/autoport/soc_broadwell.go b/util/autoport/soc_broadwell.go
new file mode 100644
index 0000000..ee61407
--- /dev/null
+++ b/util/autoport/soc_broadwell.go
@@ -0,0 +1,420 @@
+package main
+
+import "fmt"
+import "os"
+
+type broadwellsoc struct {}
+
+/* FIXME: southbridge interface */
+func (bdw broadwellsoc) GetGPIOHeader() string {
+ return "soc/pch.h"
+}
+
+func (bdw broadwellsoc) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (bdw broadwellsoc) DecodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (bdw broadwellsoc) EnableGPE(in int) {
+}
+
+func (bdw broadwellsoc) NeedRouteGPIOManually() {
+}
+
+func PrintUSB2(pei *os.File, inteltool InteltoolData) {
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+
+ xusb2pr := GetLE16(PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xd0:0xd4])
+
+ for port := 0; port < 8; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ port_disable = ((pdo1 >> port) & (uint8(xusb2pr>>port) ^ 1)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if (ocmap1[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+
+ /* get USB2 port length and location from IOBP */
+ /* FIXME: the following is from LPT-LP */
+ port_iobp := inteltool.IOBP[0xe5004100+uint32(port)*0x100]
+ loc_param := (port_iobp >> 8) & 7
+ txamp := (port_iobp >> 11) & 7
+ var port_length int
+
+ if loc_param == 6 {
+ /* back panel or mini pcie, length >= 0x70 */
+ port_pos = "USB_PORT_MINI_PCIE"
+ if txamp <= 2 {
+ port_length = 0x80
+ } else {
+ port_length = 0x110
+ }
+ } else if loc_param == 4 {
+ port_pos = "USB_PORT_DOCK"
+ if txamp <= 1 {
+ port_length = 0x40
+ } else {
+ port_length = 0x80
+ }
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ port_length = 0x40
+ }
+
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ }
+
+ if port_oc == -1 {
+ fmt.Fprintf(pei, "\tpei_data_usb2_port(pei_data, %d, 0x%04x, %d, USB_OC_PIN_SKIP,\n\t\t\t %s);\n",
+ port, port_length, (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(pei, "\tpei_data_usb2_port(pei_data, %d, 0x%04x, %d, %d,\n\t\t\t %s);\n",
+ port, port_length, (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+}
+
+func PrintUSB3(pei *os.File) {
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := 0; port < 4; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ /* FIXME: how to get the fix_eq value? */
+ if port_oc == -1 {
+ fmt.Fprintf(pei, "\tpei_data_usb3_port(pei_data, %d, %d, USB_OC_PIN_SKIP, 0);\n",
+ port, (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(pei, "\tpei_data_usb3_port(pei_data, %d, %d, %d, 0);\n",
+ port, (port_disable ^ 1), port_oc)
+ }
+ }
+}
+
+func AddBroadwellPEIData(ctx Context, inteltool InteltoolData) {
+ pei := Create(ctx, "pei_data.c")
+ defer pei.Close()
+
+ AddROMStageFile("pei_data.c", "")
+ AddRAMStageFile("pei_data.c", "")
+
+ Add_gpl(pei)
+ pei.WriteString(`#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 1;
+
+ /* FIXME: check these values */
+ pei_data->dimm_channel0_disabled = 0;
+ pei_data->dimm_channel1_disabled = 0;
+ pei_data->spd_addresses[0] = 0xa0;
+ pei_data->spd_addresses[1] = 0xa2;
+ pei_data->spd_addresses[2] = 0xa4;
+ pei_data->spd_addresses[3] = 0xa6;
+ pei_data->dq_pins_interleaved = 0;
+
+ /* FIXME: USB2 ports */
+`)
+ PrintUSB2(pei, inteltool)
+
+ pei.WriteString(`
+ /* FIXME: USB3 ports */
+`)
+ PrintUSB3(pei)
+
+ pei.WriteString(`}
+`)
+}
+
+func BDWLPGPIO(ctx Context, inteltool InteltoolData) {
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString(`#include <soc/gpio.h>
+
+const struct gpio_config mainboard_gpio_config[] = {
+`)
+ PrintLPGPIO(gpio, inteltool, "PCH")
+ gpio.WriteString("\tPCH_GPIO_END\n};\n")
+}
+
+func (bdw broadwellsoc) Scan(ctx Context, addr PCIDevData) {
+ SouthBridge = &bdw
+
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ BDWLPGPIO(ctx, inteltool)
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ romstage := Create(ctx, "romstage.c")
+ defer romstage.Close()
+ Add_gpl(romstage)
+ romstage.WriteString(`#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+
+void mainboard_pre_raminit(struct romstage_params *rp)
+{
+ /* Fill out PEI DATA */
+ mainboard_fill_pei_data(&rp->pei_data);
+}
+
+void mainboard_post_raminit(struct romstage_params *rp)
+{
+}
+`)
+
+ acpi := Create(ctx, "acpi_tables.c")
+ defer acpi.Close()
+ Add_gpl(acpi)
+ acpi.WriteString(`#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
+#include <arch/ioapic.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ return acpi_madt_irq_overrides(current);
+}
+`)
+
+ var refclk uint32
+ var pwm_hz uint32
+ refclk = 24000000
+
+ if (inteltool.IGD[0xc8254] >> 16) != 0 {
+ pwm_hz = refclk / 128 / (inteltool.IGD[0xc8254] >> 16)
+ } else {
+ pwm_hz = 0
+ }
+
+ /* FIXME */
+ sata_dtle := []uint32{0,0,0,0}
+ sata_tx := []uint32{0,0,0,0}
+
+ DevTree = DevTreeNode{
+ Chip: "soc/intel/broadwell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check these values",
+ Registers: map[string]string{
+ /* power management */
+ "gpe0_en_1": "0",
+ "gpe0_en_2": "0",
+ "gpe0_en_3": "0",
+ "gpe0_en_4": "0",
+ "alt_gp_smi_en": "0",
+ /* SATA */
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ "sata_port0_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]),
+ "sata_port1_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]),
+ "sata_port2_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]),
+ "sata_port3_gen3_tx": fmt.Sprintf("0x%x", sata_tx[0]),
+ "sata_port0_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[0]),
+ "sata_port1_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[1]),
+ "sata_port2_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[2]),
+ "sata_port3_gen3_dtle": fmt.Sprintf("0x%x", sata_dtle[3]),
+ "sata_devslp_mux": "0",
+ "sata_devslp_disable": "0",
+ /* I/O decode */
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ /* PCIe */
+ "pcie_port_coalesce": "1",
+ "pcie_port_force_aspm": "0",
+ /* serial I/O */
+ "sio_acpi_mode": "0",
+ "sio_i2c0_voltage": "0",
+ "sio_i2c1_voltage": "0",
+ /* graphics */
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_pch_backlight_pwm_hz": FormatInt32(pwm_hz),
+ "gfx": "GMA_STATIC_DISPLAYS(0)",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true },
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x13, Func: 0}, writeEmpty: true, additionalComment: "Smart Sound Audio DSP"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: true, additionalComment: "xHCI Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 0}, writeEmpty: true, additionalComment: "Serial I/O DMA"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 1}, writeEmpty: true, additionalComment: "I2C0"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 2}, writeEmpty: true, additionalComment: "I2C1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 3}, writeEmpty: true, additionalComment: "GSPI0"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 4}, writeEmpty: true, additionalComment: "GSPI1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 5}, writeEmpty: true, additionalComment: "UART0"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 6}, writeEmpty: true, additionalComment: "UART1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x17, Func: 0}, writeEmpty: true, additionalComment: "SDIO"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller (AHCI)"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ KconfigBool["SOC_INTEL_BROADWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ lpPchGetFlashSize(ctx)
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "soc/intel/broadwell/acpi/platform.asl",
+ }, DSDTInclude{
+ File: "soc/intel/broadwell/acpi/globalnvs.asl",
+ }, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ }, DSDTInclude{
+ File: "southbridge/intel/common/acpi/sleepstates.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "soc/intel/broadwell/acpi/systemagent.asl",
+ }, DSDTInclude{
+ File: "soc/intel/broadwell/acpi/pch.asl",
+ })
+
+ AddBroadwellPEIData(ctx, inteltool)
+}
+
+func init() {
+ /* Host bridge */
+ RegisterPCI(0x8086, 0x1604, broadwellsoc{})
+ /* Graphics */
+ for _, id := range []uint16{
+ 0x1606, 0x1616, 0x1626, 0x162b,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+ /* Audio */
+ RegisterPCI(0x8086, 0x160c, GenericPCI{})
+ /* SATA */
+ for _, id := range []uint16{
+ 0x9c83, 0x9c85, 0x9c87, 0x9c8f, 0x282a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+ /* PCIe */
+ for _, id := range []uint16{
+ 0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a,
+ 0x2448,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+ /* HD audio */
+ RegisterPCI(0x8086, 0x9ca0, azalia{})
+ /* SMBus */
+ RegisterPCI(0x8086, 0x9ca2, GenericPCI{})
+ /* Thermal */
+ RegisterPCI(0x8086, 0x9ca4, GenericPCI{})
+ /* EHCI */
+ RegisterPCI(0x8086, 0x9ca6, GenericPCI{})
+ /* xHCI */
+ RegisterPCI(0x8086, 0x9cb1, GenericPCI{})
+ /* LAN */
+ RegisterPCI(0x8086, 0x155a, GenericPCI{})
+ /* SDIO */
+ RegisterPCI(0x8086, 0x9cb5, GenericPCI{})
+ /* Intel Smart Sound Technology*/
+ RegisterPCI(0x8086, 0x9cb6, GenericPCI{})
+ /* Intel ME and children */
+ for id := uint16(0x9cba); id <= 0x9cbd; id++ {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+ /* LPC */
+ for _, id := range []uint16{
+ 0x9cc1, 0x9cc2, 0x9cc3, 0x9cc5,
+ 0x9cc6, 0x9cc7, 0x9cc9,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+ /* Serial I/O */
+ for id := uint16(0x9ce0); id <= 0x9ce6; id++ {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+}
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