Attention is currently required from: Paul Menzel, Angel Pons.
3 comments:
File util/autoport/wildcatpoint.go:
if bdw.variant == CORE_M {
nPorts = 10
} else {
nPorts = 8
}
Where does this information come from?
Mobile 5th Generation Intel Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor Family I/O Datasheet (330837-004), 1.3 SKU Definition.
Table 1-2 (Mobile 5th Generation Intel Core Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Intel Celeron Processor Family I/O SKUs (U-Processor Line)) says U-processor has 8 USB ports.
Table 1-4 (Intel Core M Processor I/O Platform SKUs) says Core M has 10 USB ports.
Patch Set #9, Line 237: "pcie_port_coalesce": "1",
Why enabled by default?
I see many boards set this.
Patch Set #9, Line 287: Split from soc/intel/broadwell/acpi/platform.asl
Why?
I see librem_bdw uses one broadwell/acpi/platform.asl, which is the combination of soc/intel/broadwell/acpi/device_nvs.asl, southbridge/intel/common/acpi/platform.asl, soc/intel/common/acpi/acpi_wake_source.asl, and empty _WAK and _PTS (which are generated in mainboard acpi/platform.asl).
I can see google/jecht has all these asl files except acpi_wake_source.asl.
Comments are removed now.
To view, visit change 46832. To unsubscribe, or for help writing mail filters, visit settings.