Attention is currently required from: Paul Menzel, Iru Cai.

View Change

4 comments:

• File util/autoport/wildcatpoint.go:

  • Patch Set #9, Line 43:

    if bdw.variant == CORE_M {
    		nPorts = 10
    	} else {
    		nPorts = 8
    	}
    

    Where does this information come from?

  • Patch Set #9, Line 148:

    /* FIXME: check these values */
    	pei_data->dimm_channel0_disabled = 0;
    	pei_data->dimm_channel1_disabled = 0;
    	pei_data->spd_addresses[0] = 0xa0;
    	pei_data->spd_addresses[1] = 0xa2;
    	pei_data->spd_addresses[2] = 0xa4;
    	pei_data->spd_addresses[3] = 0xa6;
    

    Broadwell ULT/ULX only supports 1 DIMM per channel. I'd just write:

     	/* FIXME: check these values */
     	pei_data->dimm_channel0_disabled = 2;
     	pei_data->dimm_channel1_disabled = 2;
     	pei_data->spd_addresses[0] = 0xa0;
     	pei_data->spd_addresses[2] = 0xa4;

  • Patch Set #9, Line 237: "pcie_port_coalesce": "1",

    Why enabled by default?

  • Patch Set #9, Line 287: Split from soc/intel/broadwell/acpi/platform.asl

    Why?

To view, visit change 46832. To unsubscribe, or for help writing mail filters, visit settings.