New subject: [M] Change in coreboot[master]: soc/intel/cannonlake: Add romstage common stage file

21 Dec 2019

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37883 )
Change subject: soc/intel/cannonlake: Add romstage common stage file
......................................................................
soc/intel/cannonlake: Add romstage common stage file
Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/romstage/romstage.c
3 files changed, 124 insertions(+), 115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37883/1

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index c744e99..16bcad6 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -113,6 +113,7 @@
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
+CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include
# DSP firmware settings files.
 NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 5c74d4a..9adae3d 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -27,109 +27,6 @@
#include "../chip.h"
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
-{
-	unsigned int i;
-	uint32_t mask = 0;
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH);
-
-	/* Set IGD stolen size to 64MB. */
-	m_cfg->IgdDvmt50PreAlloc = 2;
-	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
-	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
-	m_cfg->SaGv = config->SaGv;
-	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
-		m_cfg->UserBd = BOARD_TYPE_DESKTOP;
-	else
-		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
-	m_cfg->RMT = config->RMT;
-
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-	m_cfg->PcieRpEnableMask = mask;
-	m_cfg->PrmrrSize = get_prmrr_size();
-	m_cfg->EnableC6Dram = config->enable_c6dram;
-#if CONFIG(SOC_INTEL_COMETLAKE)
-	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
-#else
-	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
-#endif
-	/*
-	 * PcdDebugInterfaceFlags
-	 * This config will allow coreboot to pass information to the FSP
-	 * regarding which debug interface is being used.
-	 * Debug Interfaces:
-	 * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub
-	 * BIT2 - Not used.
-	 */
-	m_cfg->PcdDebugInterfaceFlags =
-				CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
-
-	/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
-	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-
-#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
-	m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
-#endif
-
-	if (config->cpu_ratio_override) {
-		m_cfg->CpuRatio = config->cpu_ratio_override;
-	} else {
-		/* Set CpuRatio to match existing MSR value */
-		msr_t flex_ratio;
-		flex_ratio = rdmsr(MSR_FLEX_RATIO);
-		m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
-	}
-
-	/* If ISH is enabled, enable ISH elements */
-	if (!dev)
-		m_cfg->PchIshEnable = 0;
-	else
-		m_cfg->PchIshEnable = dev->enabled;
-
-	/* If HDA is enabled, enable HDA elements */
-	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
-	if (!dev)
-		m_cfg->PchHdaEnable = 0;
-	else
-		m_cfg->PchHdaEnable = dev->enabled;
-
-	/* Enable IPU only if the device is enabled */
-	m_cfg->SaIpuEnable = 0;
-	dev = pcidev_path_on_root(SA_DEVFN_IPU);
-	if (dev)
-		m_cfg->SaIpuEnable = dev->enabled;
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS);
-	assert(dev != NULL);
-	const config_t *config = config_of(dev);
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-	FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
-
-	soc_memory_init_params(m_cfg, config);
-
-	/* Enable SMBus controller based on config */
-	if (!smbus)
-		m_cfg->SmbusEnable = 0;
-	else
-		m_cfg->SmbusEnable = smbus->enabled;
-
-	/* Set debug probe type */
-	m_cfg->PlatformDebugConsent =
-		CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
-
-	/* Configure VT-d */
-	tconfig->VtdDisable = 0;
-
-	mainboard_memory_init_params(mupd);
-}
-
 __weak void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
    printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index f782f63..668ca50 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -27,6 +27,11 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <string.h>
+#include <intelbasecode/romstage.h>
+#include <assert.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/msr.h>
+#include <cpu/x86/msr.h>
#include "../chip.h"
@@ -41,6 +46,121 @@
    /* Default weak implementation, no need to override part number. */
 }
+void cnlk_soc_post_mem_init(void);
+
+void cnlk_soc_mem_init_params(FSPM_UPD *mupd);
+
+static struct romstage_ops cnlk_rs_ops = {
+	&romstage_cmn_soc_init,
+	&romstage_cmn_pch_init,
+	&romstage_cmn_cpu_init,
+	&romstage_cmn_is_s3wake,
+	&romstage_cmn_soc_mem_init_param,
+	&mainboard_memory_init_params,
+	&cnlk_soc_post_mem_init,
+	&cnlk_soc_post_mem_init
+};
+
+struct romstage_ops *soc_get_ops(void)
+{
+	return &cnlk_rs_ops;
+}
+
+void cnlk_soc_mem_init_params(FSPM_UPD *mupd)
+{
+	unsigned int i;
+	uint32_t mask = 0;
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+	const config_t *config = config_of(dev);
+
+	assert(dev != NULL);
+	config = config_of(dev);
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
+	/* Set IGD stolen size to 64MB. */
+	m_cfg->IgdDvmt50PreAlloc = 2;
+	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+	m_cfg->SaGv = config->SaGv;
+	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+		m_cfg->UserBd = BOARD_TYPE_DESKTOP;
+	else
+		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+	m_cfg->RMT = config->RMT;
+
+	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+		if (config->PcieRpEnable[i])
+			mask |= (1 << i);
+	}
+	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PrmrrSize = get_prmrr_size();
+	m_cfg->EnableC6Dram = config->enable_c6dram;
+#if CONFIG(SOC_INTEL_COMETLAKE)
+	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+#else
+	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+#endif
+	/*
+	 * PcdDebugInterfaceFlags
+	 * This config will allow coreboot to pass information to the FSP
+	 * regarding which debug interface is being used.
+	 * Debug Interfaces:
+	 * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub
+	 * BIT2 - Not used.
+	 */
+	m_cfg->PcdDebugInterfaceFlags =
+				CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
+
+	/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
+	m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+#endif
+
+	if (config->cpu_ratio_override) {
+		m_cfg->CpuRatio = config->cpu_ratio_override;
+	} else {
+		/* Set CpuRatio to match existing MSR value */
+		msr_t flex_ratio;
+		flex_ratio = rdmsr(MSR_FLEX_RATIO);
+		m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+	}
+
+	/* If ISH is enabled, enable ISH elements */
+	if (!dev)
+		m_cfg->PchIshEnable = 0;
+	else
+		m_cfg->PchIshEnable = dev->enabled;
+
+	/* If HDA is enabled, enable HDA elements */
+	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+	if (!dev)
+		m_cfg->PchHdaEnable = 0;
+	else
+		m_cfg->PchHdaEnable = dev->enabled;
+
+	/* Enable IPU only if the device is enabled */
+	m_cfg->SaIpuEnable = 0;
+	dev = pcidev_path_on_root(SA_DEVFN_IPU);
+	if (dev)
+		m_cfg->SaIpuEnable = dev->enabled;
+
+	/* Enable SMBus controller based on config */
+	dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
+	if (!dev)
+		m_cfg->SmbusEnable = 0;
+	else
+		m_cfg->SmbusEnable = dev->enabled;
+
+	/* Set debug probe type */
+	m_cfg->PlatformDebugConsent =
+		CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
+
+	/* Configure VT-d */
+	mupd->FspmTestConfig.VtdDisable = 0;
+}
+
 /* Save the DIMM information for SMBIOS table 17 */
 static void save_dimm_info(void)
 {
@@ -125,19 +245,10 @@
    printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 }
-void mainboard_romstage_entry(void)
+void cnlk_soc_post_mem_init(void)
 {
-	bool s3wake;
-	struct chipset_power_state *ps = pmc_get_power_state();
-
-	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
-	systemagent_early_init();
-	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
-
-	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
-	fsp_memory_init(s3wake);
    pmc_set_disb();
-	if (!s3wake)
+	if (!cnlk_rs_ops.is_s3wake())
    	save_dimm_info();
 }
+
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/37883
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc
Gerrit-Change-Number: 37883
Gerrit-PatchSet: 1
Gerrit-Owner: Bernardo Perez Priego bernardo.perez.priego@intel.com
Gerrit-MessageType: newchange



    