[M] Change in coreboot[master]: soc/intel/tigerlake: Add romstage common stage file

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39222?usp=email )

Change subject: soc/intel/tigerlake: Add romstage common stage file
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Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9480649aedd9f3aee1033b8f53dd0be03877e338
Gerrit-Change-Number: 39222
Gerrit-PatchSet: 6
Gerrit-Owner: Bernardo Perez Priego <[e-mail]>
Gerrit-Reviewer: Bora Guvendik <[e-mail]>
Gerrit-Reviewer: Martin L Roth <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Selma Bensaid <[e-mail]>
Gerrit-Reviewer: Thejaswani Putta <[e-mail]>
Gerrit-Reviewer: Varun Joshi <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-MessageType: abandon