[S] Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25442?usp=email )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 23
Gerrit-Owner: Julien Viard de Galbert <[e-mail]>
Gerrit-Reviewer: David Guckian <[e-mail]>
Gerrit-Reviewer: David Guckian <[e-mail]>
Gerrit-Reviewer: Jay Talbott <[e-mail]>
Gerrit-Reviewer: Julien Viard de Galbert <[e-mail]>
Gerrit-Reviewer: Mariusz Szafrański <[e-mail]>
Gerrit-Reviewer: Michal Motyl <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Paul Menzel <[e-mail]>
Gerrit-Reviewer: Steve Mooney
Gerrit-Reviewer: Suresh Bellampalli <[e-mail]>
Gerrit-Reviewer: Vanessa Eusebio <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Lijian Zhao <[e-mail]>
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