Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30993

Change subject: nb/intel/i945: Use macro instead of magic number
......................................................................

nb/intel/i945: Use macro instead of magic number

Aslo add comments on Read/Write-Once bits.
ULBA register is 64bits, so maybe there is a typo
on RCBA(0x114) and it should be 0x11b insted.

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M 3rdparty/blobs
M src/northbridge/intel/i945/early_init.c
2 files changed, 8 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/1

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 16058e5..998982d 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc
+Subproject commit 998982d714a08481bb4944f456929be06b5e696f
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 6bfa1c7..70b8152 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -883,10 +883,13 @@

static void ich7_setup_root_complex_topology(void)
 {
-	RCBA32(0x104) = 0x00000802;
-	RCBA32(0x110) = 0x00000001;
-	RCBA32(0x114) = 0x00000000;
-	RCBA32(0x118) = 0x00000000;
+	/* FIXME: ESD [23:16] is R/WO */
+	RCBA32(ESD) = 0x00000802;
+	/* FIXME: ULD [31:16] is R/WO */
+	RCBA32(ULD) = 0x00000001;
+	/* FIXME: ULBA [63:0] is R/WO */
+	RCBA32(0x114) = 0x00000000; // RCBA32(0x11b) ?
+	RCBA32(ULBA) = 0x00000000;
 }

static void ich7_setup_pci_express(void)

[HAOUAS Elyes (Code Review)]

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#2).

Change subject: nb/intel/i945: Use macro instead of magic number
......................................................................

nb/intel/i945: Use macro instead of magic number

Aslo add comments on Read/Write-Once bits.
ULBA register is 64bits, so maybe there is a typo
on RCBA(0x114) and it should be 0x11b insted.
(Please see ICH7 datasheet page 271).

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 7 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/2

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Use macro instead of magic number
......................................................................

Patch Set 2:

(4 comments)

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
File src/northbridge/intel/i945/early_init.c:

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
PS2, Line 349: 810
this RO and reserved bits.
and inany case , it will never happen as it is already done at ich7_setup_root_complex_topology function.
(this RCBA register is R/WO)

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
PS2, Line 371: 	RCBA32(ESD) |= (2 << 16);
             : 
             : 	RCBA32(ULD) |= (1 << 24) | (1 << 16);
             : 
             : 	RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
this will never happen
the registers are R/WO
and we already did it at function ich7_setup_root_complex_topology()

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
PS2, Line 887: 802
this RO and reserved.
so is this write needed ?

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
PS2, Line 889: 1
this write do not make sense
this bit is RO if I'm not wrong

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Use macro instead of magic number
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
File src/northbridge/intel/i945/early_init.c:

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
PS2, Line 350: RCBA32(RP1D) = 0x01000003
[23:16] is R/WO .
this write is not needed and it will prevent as to write 
RCBA32(RP1D) |= (2 << 16); (line 377)

https://review.coreboot.org/#/c/30993/2/src/northbridge/intel/i945/early_ini... 
PS2, Line 351: RCBA32(RP2D) = 0x02000002;
             : 	RCBA32(RP3D) = 0x03000002;
             : 	RCBA32(RP4D) = 0x04000002;
             : 	RCBA32(HDD) = 0x0f000003;
             : 	RCBA32(RP5D) = 0x05000002;
same ...

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#3).

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

nb/intel/i945: Don't rewrite R/WO RCBA registers

Element Self Description register (ESD) [23:16] is R/WO,so let
write the ESD.CID when we start ich7_setup_root_complex_topology
This value is also used to programme the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once is done, no need to rewrite on them as they become RO(or reserved).
(For more information, please see ICH7 datasheet page 271).

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/3

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#4).

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

nb/intel/i945: Don't rewrite R/WO RCBA registers

Element Self Description register (ESD) [23:16] is R/WO,so let
write the ESD.CID when we start ich7_setup_root_complex_topology
This value is also used to programme the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271).

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/4

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

Patch Set 5: Code-Review+1

(1 comment)

Can you test this somehow?

https://review.coreboot.org/#/c/30993/5//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30993/5//COMMIT_MSG@11 
PS5, Line 11: programme
program

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#6).

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

nb/intel/i945: Don't rewrite R/WO RCBA registers

Element Self Description register (ESD) [23:16] is R/WO,so let
write the ESD.CID when we start ich7_setup_root_complex_topology
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271).

Tested on 945G-M4:
befor this change, writing on those registers have no effect.
The check is done using printk before and after writing.
With this change, those R/WO got the "right" values.

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/6

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

Patch Set 6:

(3 comments)

https://review.coreboot.org/#/c/30993/6/src/northbridge/intel/i945/early_ini... 
File src/northbridge/intel/i945/early_init.c:

https://review.coreboot.org/#/c/30993/6/src/northbridge/intel/i945/early_ini... 
PS6, Line 349: 
             : 
             : 
             : 
             : 
             : 
             : 
here printk before and after the "write" shows that no thing happen. the "write" have no effect.

https://review.coreboot.org/#/c/30993/6/src/northbridge/intel/i945/early_ini... 
PS6, Line 371: 
             : 
             : 
             : 
             : 
             : 
             : 
             : 
             : 
             : 
             : 
             : 
             : 
here also, using printk, we can see that the "write" have no effect, as those registers are R/WO and we already write on them

https://review.coreboot.org/#/c/30993/6/src/northbridge/intel/i945/early_ini... 
PS6, Line 867: RCBA32(ESD) |= (2 << 16);
             : 
             : 	RCBA32(ULD) |= (1 << 24) | (1 << 16);
             : 
             : 	RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
             : 	/* Write ESD.CID to TCID */
             : 	RCBA32(RP1D) |= (2 << 16);
             : 	RCBA32(RP2D) |= (2 << 16);
             : 	RCBA32(RP3D) |= (2 << 16);
             : 	RCBA32(RP4D) |= (2 << 16);
             : 	RCBA32(HDD)  |= (2 << 16);
             : 	RCBA32(RP5D) |= (2 << 16);
             : 	RCBA32(RP6D) |= (2 << 16);
here using printk, we can clearly see that we write on those registers

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#7).

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

nb/intel/i945: Don't rewrite R/WO RCBA registers

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271).

Tested on 945G-M4:
befor this change, writing on those registers have no effect.
The check is done using printk before and after writing.
With this change, those R/WO got the "right" values.

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/7

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#10).

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

nb/intel/i945: Don't rewrite R/WO RCBA registers

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271).

Tested on 945G-M4:
befor this change, writing on those registers have no effect.
The check is done using printk before and after writing.
With this change, those R/WO got the "right" values.
Here is the values: (witout this patch --> with this patch):
ESD:  0x0104: 0x00000802 --> 0x0104: 0x00020802
ULD:  0x0110: 0x00000001 --> 0x0110: 0x01010001
ULBA: 0x0118: 0x00000000 --> 0x0118: 0xfed18000
RP1D: 0x0120: 0x01000003 --> 0x0120: 0x01020003
RP2D: 0x0130: 0x02000003 --> 0x0130: 0x02020003
RP3D: 0x0140: 0x03000002 --> 0x0140: 0x03020002
RP4D: 0x0150: 0x04000002 --> 0x0150: 0x04020002
HDD:  0x0160: 0x0f000002 --> 0x0160: 0x0f020002
RP5D: 0x0170: 0x05000002 --> 0x0170: 0x05020002
RP6D: 0x0180: 0x06000002 --> 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/10

Change in ...coreboot[master]: nb/intel/i945: Don't rewrite R/WO RCBA registers

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#11).

Change subject: nb/intel/i945: Don't rewrite R/WO RCBA registers
......................................................................

nb/intel/i945: Don't rewrite R/WO RCBA registers

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271).

Tested on 945G-M4:
befor this change, writing on those registers have no effect.
The check is done using printk before and after writing.
With this change, those R/WO got the "right" values.
Here is the values: (without this patch --> with this patch):
ESD:  0x0104: 0x00000802 --> 0x0104: 0x00020802
ULD:  0x0110: 0x00000001 --> 0x0110: 0x01010001
ULBA: 0x0118: 0x00000000 --> 0x0118: 0xfed18000
RP1D: 0x0120: 0x01000003 --> 0x0120: 0x01020003
RP2D: 0x0130: 0x02000003 --> 0x0130: 0x02020003
RP3D: 0x0140: 0x03000002 --> 0x0140: 0x03020002
RP4D: 0x0150: 0x04000002 --> 0x0150: 0x04020002
HDD:  0x0160: 0x0f000002 --> 0x0160: 0x0f020002
RP5D: 0x0170: 0x05000002 --> 0x0170: 0x05020002
RP6D: 0x0180: 0x06000002 --> 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/11

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#12).

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

nb/intel/i945: Fix ich7_setup_root_complex_topology

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271).

Tested on 945G-M4:
befor this change, writing on those registers have no effect.
The check is done using printk before and after writing.
With this change, those R/WO got the "right" values.
i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR.
Here is the values: (without this patch --> with this patch):
ESD:  0x0104: 0x00000802 --> 0x0104: 0x00020802
ULD:  0x0110: 0x00000001 --> 0x0110: 0x01010001
ULBA: 0x0118: 0x00000000 --> 0x0118: 0xfed18000
RP1D: 0x0120: 0x01000003 --> 0x0120: 0x01020003
RP2D: 0x0130: 0x02000003 --> 0x0130: 0x02020003
RP3D: 0x0140: 0x03000002 --> 0x0140: 0x03020002
RP4D: 0x0150: 0x04000002 --> 0x0150: 0x04020002
HDD:  0x0160: 0x0f000002 --> 0x0160: 0x0f020002
RP5D: 0x0170: 0x05000002 --> 0x0170: 0x05020002
RP6D: 0x0180: 0x06000002 --> 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/12

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

Patch Set 13: Code-Review+1

(4 comments)

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@14 
PS13, Line 14: (For more information, please see ICH7 datasheet page 271).
Please move the dot into the brackets: ….).

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@17 
PS13, Line 17: befor
Before

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@17 
PS13, Line 17: have
had

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@19 
PS13, Line 19: got
get

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#14).

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

nb/intel/i945: Fix ich7_setup_root_complex_topology

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271.)

Tested on 945G-M4:
before this change, writing on those registers had no effect.
The check is done using printk before and after writing.
With this change, those R/WO get the "right" values.
i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR.
Here is the values: (without this patch --> with this patch):
ESD:  0x0104: 0x00000802 --> 0x0104: 0x00020802
ULD:  0x0110: 0x00000001 --> 0x0110: 0x01010001
ULBA: 0x0118: 0x00000000 --> 0x0118: 0xfed18000
RP1D: 0x0120: 0x01000003 --> 0x0120: 0x01020003
RP2D: 0x0130: 0x02000003 --> 0x0130: 0x02020003
RP3D: 0x0140: 0x03000002 --> 0x0140: 0x03020002
RP4D: 0x0150: 0x04000002 --> 0x0150: 0x04020002
HDD:  0x0160: 0x0f000002 --> 0x0160: 0x0f020002
RP5D: 0x0170: 0x05000002 --> 0x0170: 0x05020002
RP6D: 0x0180: 0x06000002 --> 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/14

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

Patch Set 13:

(4 comments)

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@14 
PS13, Line 14: (For more information, please see ICH7 datasheet page 271).
> Please move the dot into the brackets: ….).

Done

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@17 
PS13, Line 17: have
> had

Done

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@17 
PS13, Line 17: befor
> Before

Done

https://review.coreboot.org/#/c/30993/13//COMMIT_MSG@19 
PS13, Line 19: got
> get

Done

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[HAOUAS Elyes (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30993

to look at the new patch set (#16).

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

nb/intel/i945: Fix ich7_setup_root_complex_topology

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271.)

Tested done on 945G-M4 using printk before and after writing.
Before this change, writing on those registers had no effect:
ESD:  0x0104: 0x00000802
ULD:  0x0110: 0x00000001
ULBA: 0x0118: 0x00000000
RP1D: 0x0120: 0x01000003
RP2D: 0x0130: 0x02000003
RP3D: 0x0140: 0x03000002
RP4D: 0x0150: 0x04000002
HDD:  0x0160: 0x0f000002
RP5D: 0x0170: 0x05000002
RP6D: 0x0180: 0x06000002

Using this patche, those R/WO get the "right" values.
i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR.
ESD:  0x0104: 0x00020802
ULD:  0x0110: 0x01010001
ULBA: 0x0118: 0xfed18000
RP1D: 0x0120: 0x01020003
RP2D: 0x0130: 0x02020003
RP3D: 0x0140: 0x03020002
RP4D: 0x0150: 0x04020002
HDD:  0x0160: 0x0f020002
RP5D: 0x0170: 0x05020002
RP6D: 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/16

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

Patch Set 16: Code-Review+2

Change in ...coreboot[master]: nb/intel/i945: Fix ich7_setup_root_complex_topology

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30993 )

Change subject: nb/intel/i945: Fix ich7_setup_root_complex_topology
......................................................................

nb/intel/i945: Fix ich7_setup_root_complex_topology

Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271.)

Tested done on 945G-M4 using printk before and after writing.
Before this change, writing on those registers had no effect:
ESD:  0x0104: 0x00000802
ULD:  0x0110: 0x00000001
ULBA: 0x0118: 0x00000000
RP1D: 0x0120: 0x01000003
RP2D: 0x0130: 0x02000003
RP3D: 0x0140: 0x03000002
RP4D: 0x0150: 0x04000002
HDD:  0x0160: 0x0f000002
RP5D: 0x0170: 0x05000002
RP6D: 0x0180: 0x06000002

Using this patche, those R/WO get the "right" values.
i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR.
ESD:  0x0104: 0x00020802
ULD:  0x0110: 0x01010001
ULBA: 0x0118: 0xfed18000
RP1D: 0x0120: 0x01020003
RP2D: 0x0130: 0x02020003
RP3D: 0x0140: 0x03020002
RP4D: 0x0150: 0x04020002
HDD:  0x0160: 0x0f020002
RP5D: 0x0170: 0x05020002
RP6D: 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30993
Reviewed-by: Patrick Georgi 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 15 insertions(+), 25 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 08dd675..0c92c4b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -341,13 +341,6 @@

RCBA32(V0CTL) = 0x80000001;
    RCBA32(V1CAP) = 0x03128010;
-	RCBA32(ESD) = 0x00000810;
-	RCBA32(RP1D) = 0x01000003;
-	RCBA32(RP2D) = 0x02000002;
-	RCBA32(RP3D) = 0x03000002;
-	RCBA32(RP4D) = 0x04000002;
-	RCBA32(HDD) = 0x0f000003;
-	RCBA32(RP5D) = 0x05000002;

pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141);
    pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141);
@@ -361,20 +354,6 @@
    reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
    RCBA32(V1CTL) = reg32;

-	RCBA32(ESD) |= (2 << 16);
-
-	RCBA32(ULD) |= (1 << 24) | (1 << 16);
-
-	RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
-
-	RCBA32(RP1D) |= (2 << 16);
-	RCBA32(RP2D) |= (2 << 16);
-	RCBA32(RP3D) |= (2 << 16);
-	RCBA32(RP4D) |= (2 << 16);
-	RCBA32(HDD)  |= (2 << 16);
-	RCBA32(RP5D) |= (2 << 16);
-	RCBA32(RP6D) |= (2 << 16);
-
    RCBA32(LCAP) |= (3 << 10);
 }

@@ -871,10 +850,21 @@

static void ich7_setup_root_complex_topology(void)
 {
-	RCBA32(0x104) = 0x00000802;
-	RCBA32(0x110) = 0x00000001;
-	RCBA32(0x114) = 0x00000000;
-	RCBA32(0x118) = 0x00000000;
+	/* Write the R/WO registers */
+
+	RCBA32(ESD) |= (2 << 16);
+
+	RCBA32(ULD) |= (1 << 24) | (1 << 16);
+
+	RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
+	/* Write ESD.CID to TCID */
+	RCBA32(RP1D) |= (2 << 16);
+	RCBA32(RP2D) |= (2 << 16);
+	RCBA32(RP3D) |= (2 << 16);
+	RCBA32(RP4D) |= (2 << 16);
+	RCBA32(HDD)  |= (2 << 16);
+	RCBA32(RP5D) |= (2 << 16);
+	RCBA32(RP6D) |= (2 << 16);
 }

static void ich7_setup_pci_express(void)